Changeset 5e3096db in rtems


Ignore:
Timestamp:
Jul 4, 2016, 6:05:43 PM (5 years ago)
Author:
Punit Vara <punitvara@…>
Branches:
5, master
Children:
c3058473
Parents:
6dc5c03f
git-author:
Punit Vara <punitvara@…> (07/04/16 18:05:43)
git-committer:
Martin Galvan <martin.galvan@…> (07/04/16 18:09:06)
Message:

Beaglebone: Update PWM driver imported from BBBIO

This patch adapts the previously added Beaglebone PWM code from BBBIO to RTEMS.
This work was done in the context of the Google Summer of Code 2016, and further
patches will follow to improve the code quality and documentation.

Location:
c/src/lib
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/beagle/Makefile.am

    r6dc5c03f r5e3096db  
    4242include_bsp_HEADERS += include/beagleboneblack.h
    4343include_bsp_HEADERS += include/bbb-gpio.h
     44include_bsp_HEADERS += include/bbb-pwm.h
    4445
    4546include_libcpu_HEADERS =
     
    118119libbsp_a_SOURCES += gpio/bbb-gpio.c
    119120
     121#pwm
     122libbsp_a_SOURCES += pwm/pwm.c
     123
    120124#RTC
    121125libbsp_a_SOURCES += rtc.c
  • c/src/lib/libbsp/arm/beagle/include/bbb-pwm.h

    r6dc5c03f r5e3096db  
     1/**
     2 * @file
     3 *
     4 * @ingroup arm_beagle
     5 *
     6 * @brief BeagleBone Black BSP definitions.
     7 */
     8
     9/**
     10 * Copyright (c) 2016 Punit Vara <punitvara at gmail.com>
     11 *
     12 * The license and distribution terms for this file may be
     13 * found in the file LICENSE in this distribution or at
     14 * http://www.rtems.org/license/LICENSE.
     15 */
     16
     17/** Some constants are taken from
     18 * https://github.com/VegetableAvenger/BBBIOlib/blob/master/BBBio_lib/BBBiolib_PWMSS.h
     19 */
     20
    121#ifndef LIBBSP_ARM_BEAGLE_BBB_PWM_H
    222#define LIBBSP_ARM_BEAGLE_BBB_PWM_H
     
    929 * @brief  BeagleBone Black PWM Macros.
    1030 */
    11 #define BBBIO_PWMSS_COUNT       3
    12 #define BBBIO_PWMSS0           0
    13 #define BBBIO_PWMSS1           1
    14 #define BBBIO_PWMSS2           2
     31#define BBB_CONTROL_CONF_GPMC_AD(n)   (0x800 + (n * 4))
     32#define BBB_CONTROL_CONF_LCD_DATA(n)   (0x8a0 + (n * 4))
    1533
    16 #define MUXMODE0               0
    17 #define MUXMODE1                1
    18 #define MUXMODE2               2
    19 #define MUXMODE3               3
    20 #define MUXMODE4               4
    21 #define MUXMODE5               5
    22 #define MUXMODE6               6
    23 #define MUXMODE7               7
     34#define BBB_PWMSS_COUNT       3
     35#define BBB_PWMSS0  0
     36#define BBB_PWMSS1  1 
     37#define BBB_PWMSS2  2
    2438
    25 #define EPWM_GROUP1    1
    26 #define EPWM_GROUP2    2
    27 #define EPWM_GROUP0    0
     39#define BBB_P8_13_2B  3
     40#define BBB_P8_19_2A  4
     41#define BBB_P8_45_2A  5
     42#define BBB_P8_46_2B  6
     43#define BBB_P8_34_1B  7
     44#define BBB_P8_36_1A  8
     45#define BBB_P9_14_1A  9
     46#define BBB_P9_16_1B  10
     47#define BBB_P9_21_0B  11
     48#define BBB_P9_22_0A  12
     49#define BBB_P9_29_0B  13
     50#define BBB_P9_31_0A  14
    2851
    29 int BBBIO_PWMSS_Setting(unsigned int PWMID , float HZ ,float dutyA ,float dutyB);
    30 int BBBIO_PWM_Init();
    31 void BBBIO_PWM_Release();
    32 int BBBIO_PWMSS_Status(unsigned int PWMID);
    33 void BBBIO_ehrPWM_Enable(unsigned int PWMSS_ID);
    34 void BBBIO_ehrPWM_Disable(unsigned int PWMSS_ID);
     52#define BBB_MUX0      0
     53#define BBB_MUX1      1
     54#define BBB_MUX2      2
     55#define BBB_MUX3      3
     56#define BBB_MUX4      4
     57#define BBB_MUX5      5
     58#define BBB_MUX6      6
     59#define BBB_MUX7      7
    3560
     61#define BBB_EPWM1     1
     62#define BBB_EPWM2     2
     63#define BBB_EPWM0     0
     64
     65/**
     66 * @brief  BeagleBone Black PWM API.
     67 */
     68
     69/**
     70 * @brief This function intilize clock and pinmuxing for pwm sub system.
     71 *
     72 * @param PWMSS_ID It is the instance number of EPWM of pwm sub system.
     73 *
     74 * @return true if successful
     75 * @return false if not successful
     76 *
     77 **/
     78bool beagle_pwm_init(uint32_t pwmss_id);
     79
     80/* PWMSS setting
     81 *      set pulse argument of epwm module
     82 *
     83 *      @param pwm_id    : EPWMSS number , 0~2
     84 *      @param pwm_freq : frequency to be generated
     85 *      @param dutyA    : Duty Cycle in ePWM A
     86 *      @param dutyB    : Duty Cycle in ePWM B
     87 *
     88 *      @return         : 1 for success
     89 *      @return         : 0 for failed
     90 *
     91 *      @example        :  PWMSS_Setting(0 , 50.0f , 50.0f , 25.0f);      // Generate 50HZ pwm in PWM0 ,
     92 *                                                                              // duty cycle is 50% for ePWM0A , 25% for ePWM0B
     93 *
     94 *      @Note :
     95 *              find an number nearst 65535 for TBPRD , to improve duty precision,
     96 *
     97 *              Using big TBPRD can increase the range of CMPA and CMPB ,
     98 *              and it means we can get better precision on duty cycle.
     99 *
     100 *              EX : 20.25% duty cycle
     101 *                  on TBPRD = 62500 , CMPA = 12656.25 ( .25 rejection) , real duty : 20.2496% (12656 /62500)
     102 *                  on TBPRD = 6250  , CMPA = 1265.625 ( .625 rejection), real duty : 20.24%   (1265 6250)
     103 *                  on TBPRD = 500   , CMPA = 101.25   ( .25 rejection) , real duty : 20.2%    (101/500)
     104 *
     105 *              Divisor = CLKDIV * HSPCLKDIV
     106 *                      1 TBPRD : 10 ns (default)
     107 *                      65535 TBPRD : 655350 ns
     108 *                      65535 TBPRD : 655350 * Divisor ns  = X TBPRD : Cyclens
     109 *
     110 *              accrooding to that , we must find a Divisor value , let X nearest 65535 .
     111 *              so , Divisor must  Nearest Cyclens/655350
     112 */
     113int beagle_pwmss_setting(uint32_t pwm_id, float pwm_freq, float dutyA, float dutyB);
     114
     115/**
     116 * @brief   This API enables the particular PWM module.
     117 *
     118 * @param   pwmid  It is the instance number of EPWM of pwm sub system.
     119 *
     120 * @return  true if successful
     121 * @return  false if fail
     122 *
     123 **/
     124bool beagle_ehrpwm_enable(uint32_t pwmid);
     125
     126/**
     127 * @brief   This API disables the HR sub-module.
     128 *
     129 * @param   pwmid  It is the instance number of EPWM of pwm sub system.
     130 *
     131 * @return  true if successful
     132 * @return  false if fail
     133 *
     134 **/
     135bool beagle_ehrpwm_disable(uint32_t pwmid);
     136
     137/**
     138 * @brief   This function Enables pinmuxing for PWM module.
     139 *
     140 * @param   pin_no  It is individual pin at which freuqency need to be generated.
     141 *                  It should be according to pwm sub system.
     142 *
     143 * @param   pwm_id  It is the instance number of EPWM of pwmsubsystem.
     144 *
     145 * @return  true if successful
     146 * @return  false if fail
     147 *
     148 **/
     149bool beagle_epwm_pinmux_setup(uint32_t pin_no, uint32_t pwm_id);
    36150
    37151#ifdef __cplusplus
  • c/src/lib/libbsp/arm/beagle/pwm/pwm.c

    r6dc5c03f r5e3096db  
     1/**
     2 * @file
     3 *
     4 * @ingroup arm_beagle
     5 *
     6 * @brief Support for PWM for the BeagleBone Black.
     7 */
     8
     9/**
     10 * Copyright (c) 2016 Punit Vara <punitvara at gmail.com>
     11 *
     12 * The license and distribution terms for this file may be
     13 * found in the file LICENSE in this distribution or at
     14 * http://www.rtems.org/license/LICENSE.
     15 */
     16
     17/** This file is based on
     18  * https://github.com/VegetableAvenger/BBBIOlib/blob/master/BBBio_lib/BBBiolib_PWMSS.c
     19  */
     20
     21#include <libcpu/am335x.h>
    122#include <stdio.h>
    2 #include <stdlib.h>
    3 #include <sys/mman.h>
    4 #include <sys/stat.h>
    5 #include <fcntl.h>
    6 #include <errno.h>
    7 #include <time.h>
    8 #include "BBBiolib.h"
    9 /*-----------------------------------------------------------------------------------------------*/
     23#include <bsp/gpio.h>
     24#include <bsp/bbb-gpio.h>
     25#include <bsp.h>
     26#include <bsp/bbb-pwm.h>
     27
     28/* Currently these definitions are for BeagleBone Black board only
     29 * Later on Beagle-xM board support can be added in this code.
     30 * After support gets added if condition should be removed
     31 */
     32#if IS_AM335X
     33
    1034/*
    11  * PWMSS Registers
    12  *
    13  * @Source : AM335x Technical Reference Manual ,page 1991
    14  *           Table 15-5. PWMSS REGISTERS
    15  *
     35 * @brief This function select PWM module to be enabled
     36 * 
     37 * @param pwm_id It is the instance number of EPWM of pwm sub system.
     38 *
     39 * @return Base Address of respective pwm instant.
    1640*/
    17 
    18 #define PWMSS0_MMAP_ADDR   0x48300000
    19 #define PWMSS1_MMAP_ADDR   0x48302000
    20 #define PWMSS2_MMAP_ADDR   0x48304000
    21 #define PWMSS_MMAP_LEN     0x1000
    22 
    23 #define PWMSS_IDVER    0x0
    24 #define PWMSS_SYSCONFIG    0x4
    25 #define PWMSS_CLKCONFIG    0x8
    26 #define PWMSS_CLKSTATUS    0xC
    27 
    28 /* EPWM Registers
    29  *
    30  * @Source : AM335x Technical Reference Manual ,page 2084
    31  *           Table 15-58. EPWM REGISTERS
    32  *
    33 */
    34 #define EPWM_TBCTL 0x0
    35 #define EPWM_TBSTS 0x2
    36 #define EPWM_TBPHSHR   0x4
    37 #define EPWM_TBPHS 0x6
    38 #define EPWM_TBCNT 0x8
    39 #define EPWM_TBPRD 0xA
    40 #define EPWM_CMPCTL    0xE
    41 #define EPWM_CMPAHR    0x10
    42 #define EPWM_CMPA  0x12
    43 #define EPWM_CMPB  0x14
    44 #define EPWM_AQCTLA    0x16
    45 #define EPWM_AQCTLB    0x18
    46 #define EPWM_AQSFRC    0x1A
    47 #define EPWM_AQCSFRC   0x1C
    48 #define EPWM_DBCTL 0x1E
    49 #define EPWM_DBRED 0x20
    50 #define EPWM_DBFED 0x22
    51 /*-----------------------------------------------------------------------------------------------*/
    52 extern int memh;
    53 extern volatile unsigned int *CM_ptr;  /*c ontrol module */
    54 volatile unsigned int *cm_per_addr;
    55 
    56 
    57 const unsigned int PWMSS_AddressOffset[]={PWMSS0_MMAP_ADDR,
    58                      PWMSS1_MMAP_ADDR,
    59                      PWMSS2_MMAP_ADDR};
    60 volatile unsigned int *pwmss_ptr[3]     ={NULL, NULL, NULL} ;
    61 volatile unsigned int *epwm_ptr[3]      ={NULL, NULL, NULL} ;
    62 volatile unsigned int *ecap_ptr[3]      ={NULL, NULL, NULL} ;
    63 volatile unsigned int *eqep_ptr[3]      ={NULL, NULL, NULL} ;
    64 
    65 #define TBCTL_CTRMODE_UP        0x0
    66 #define TBCTL_CTRMODE_DOWN      0x1
    67 #define TBCTL_CTRMODE_UPDOWN    0x2
    68 #define TBCTL_CTRMODE_FREEZE    0x3
    69 /* ----------------------------------------------------------------------------------------------- */
    70 /* PWMSS Timebase clock check
    71  *     check the timenase clock enable or not
    72  *
    73  * @param PWMSS_ID :  PWM sumsystem ID (BBBIO_PWMSS0 ,BBBIO_PWMSS1, BBBIO_PWMSS2)
    74  *
    75  * @return : 0 for disable timebase clock , 1 for enable for timebase clock
     41static uint32_t select_pwmss(uint32_t pwm_id)
     42{
     43uint32_t baseAddr=0;
     44   if (pwm_id == BBB_PWMSS0)
     45   {
     46   baseAddr = AM335X_EPWM_0_REGS;
     47   return baseAddr;
     48   }
     49   else if (pwm_id == BBB_PWMSS1)
     50   {
     51   baseAddr = AM335X_EPWM_1_REGS;
     52   return baseAddr;
     53   }
     54   else if (pwm_id == BBB_PWMSS2)
     55   {
     56   baseAddr = AM335X_EPWM_2_REGS;
     57   return baseAddr;
     58   }
     59   else
     60   {
     61   printf("Invalid PWM Id\n");
     62   return 0;   
     63   }
     64}
     65
     66bool beagle_epwm_pinmux_setup(uint32_t pin_no, uint32_t pwm_id)
     67{
     68  switch(pwm_id)  {
     69   case BBB_PWMSS2:
     70       switch(pin_no) {
     71           case BBB_P8_13_2B:
     72               REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_GPMC_AD(9)) = BBB_MUXMODE(BBB_MUX4);
     73               break;
     74           case BBB_P8_19_2A:
     75               REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_GPMC_AD(8)) = BBB_MUXMODE(BBB_MUX4);
     76               break;
     77           case BBB_P8_45_2A:
     78               REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_LCD_DATA(0)) = BBB_MUXMODE(BBB_MUX3);
     79               break;
     80           case BBB_P8_46_2B:
     81               REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_LCD_DATA(1)) = BBB_MUXMODE(BBB_MUX3);
     82               break;
     83           default :
     84               printf("Invalid pin for module 2\n");
     85               return false;
     86       }
     87       break;
     88   case BBB_PWMSS1:
     89       switch(pin_no) {
     90           case BBB_P8_34_1B:
     91               REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_LCD_DATA(11)) = BBB_MUXMODE(BBB_MUX2);
     92               break;
     93           case BBB_P8_36_1A:
     94               REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_LCD_DATA(10)) = BBB_MUXMODE(BBB_MUX2);
     95               break;
     96           case BBB_P9_14_1A:
     97               REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_GPMC_AD(2)) = BBB_MUXMODE(BBB_MUX6);
     98               break;
     99           case BBB_P9_16_1B:
     100               REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_GPMC_AD(3)) = BBB_MUXMODE(BBB_MUX6);
     101               break;
     102           default :
     103               printf("Invalid pin for module 1\n");
     104               return false;
     105       }   
     106       break;
     107   case BBB_PWMSS0:
     108       switch(pin_no) {
     109           case BBB_P9_21_0B:
     110               REG(AM335X_PADCONF_BASE + AM335X_CONF_SPI0_D0) = BBB_MUXMODE(BBB_MUX3);
     111               break;
     112           case BBB_P9_22_0A:
     113               REG(AM335X_PADCONF_BASE + AM335X_CONF_SPI0_SCLK) = BBB_MUXMODE(BBB_MUX3);
     114               break;
     115           case BBB_P9_29_0B:
     116               REG(AM335X_PADCONF_BASE + AM335X_CONF_MCASP0_FSX) = BBB_MUXMODE(BBB_MUX1);
     117               break;
     118           case BBB_P9_31_0A:
     119               REG(AM335X_PADCONF_BASE + AM335X_CONF_MCASP0_ACLKX) = BBB_MUXMODE(BBB_MUX1);
     120               break;
     121           default:
     122               printf("Invalid pin for module 0\n");
     123               return false;
     124       }
     125       break;
     126   
     127   default:
     128       printf("Invalid PWM sub system\n");
     129       return false;
     130}
     131}
     132
     133/**
     134 * @brief   This function Enables TBCLK(Time Base Clock) for specific
     135 *          EPWM instance of pwmsubsystem.
     136 *
     137 * @param   instance  It is the instance number of EPWM of pwmsubsystem.
     138 *
     139 * @return  true if successful
     140 **/
     141static bool pwmss_tbclk_enable(unsigned int instance)
     142{
     143uint32_t enable_bit;
     144bool is_valid = true;
     145 
     146  if (instance == BBB_PWMSS0)
     147  {
     148       enable_bit = AM335X_PWMSS_CTRL_PWMSS0_TBCLKEN;
     149  }
     150  else if (instance == BBB_PWMSS1)
     151  {
     152       enable_bit = AM335X_PWMSS_CTRL_PWMSS1_TBCLKEN;
     153  }
     154  else if (instance == BBB_PWMSS2)
     155  {
     156       enable_bit = AM335X_PWMSS_CTRL_PWMSS2_TBCLKEN;
     157  }
     158  else
     159  {
     160       is_valid = false;
     161  }
     162
     163  if (is_valid)
     164  {
     165       REG(AM335X_PADCONF_BASE + AM335X_PWMSS_CTRL) |= enable_bit;
     166  }
     167
     168  return is_valid;
     169 }
     170
     171/**
     172 * @brief   This functions enables clock for EHRPWM module in PWMSS subsystem.
     173 *
     174 * @param   pwm_id  It is the instance number of EPWM of pwm sub system.
     175 *
     176 * @return  None.
     177 *
     178 **/
     179static void epwm_clock_enable(uint32_t pwm_id)
     180
     181   if((pwm_id <3) && (pwm_id >=0)) {
     182       uint32_t baseAddr;
     183       baseAddr = select_pwmss(pwm_id);
     184               REG(baseAddr - AM335X_EPWM_REGS + AM335X_PWMSS_CLKCONFIG) |= AM335X_PWMSS_CLK_EN_ACK;
     185        } else {
     186       printf("Invalid pwm_id\n");
     187   }
     188}
     189
     190/**
     191 * @brief   This function configures the L3 and L4_PER system clocks.
     192 *          It also configures the system clocks for the specified ePWMSS
     193 *          instance.
     194 *
     195 * @param   pwmss_id    The instance number of ePWMSS whose system clocks
     196 *                         have to be configured.
     197 *
     198 * 'pwmss_id' can take one of the following values:
     199 * (0 <= pwmss_id <= 2)
     200 *
     201 * @return  None.
     202 *
    76203 */
    77 static int PWMSS_TB_clock_check(unsigned int PWMSS_ID)
    78 {
    79    volatile unsigned int* reg;
    80    unsigned int reg_value ;
    81 
    82    /* Control module check */
    83    reg =(void *)CM_ptr + BBBIO_PWMSS_CTRL;
    84    reg_value = *reg ;
    85 
    86    return (reg_value & (1 << PWMSS_ID)) ;
    87 }
    88 
    89 /* ----------------------------------------------------------------------------------------------- */
    90 /* PWM subsystem system control
    91  *     enable or disable module clock
    92  *
    93  * @param PWMSS_ID :  PWM sumsystem ID (BBBIO_PWMSS0 ,BBBIO_PWMSS1, BBBIO_PWMSS2).
    94  * @param enable : 0 for disable , else for enable .
    95  *
    96  * @return : 1 for success ,  0 for error
    97  */
    98 static int PWMSS_module_ctrl(unsigned int PWMSS_ID, int enable)
    99 {
    100    volatile unsigned int *reg = NULL;
    101    unsigned int module_set[] = {BBBIO_PWMSS0, BBBIO_PWMSS1, BBBIO_PWMSS2};
    102    unsigned int module_clk_set[] = {BBBIO_CM_PER_EPWMSS0_CLKCTRL, BBBIO_CM_PER_EPWMSS1_CLKCTRL, BBBIO_CM_PER_EPWMSS2_CLKCTRL};
    103    int ret = 1;
    104 
    105    reg = (void*)cm_per_addr + module_clk_set[PWMSS_ID];
    106    if(enable) {
    107        if(PWMSS_TB_clock_check(module_set[PWMSS_ID])) {
    108            /* Enable module clock */
    109            *reg = 0x2; /* Module enable and fully functional */
    110            return ret;
    111        }
    112 #ifdef BBBIO_LIB_DBG
    113        else {
    114            printf("PWMSS_module_ctrl : PWMSS-%d timebase clock disable in Control Module\n", PWMSS_ID);
    115        }
    116 #endif
    117        ret = 0 ;
    118    }
    119    *reg = 0x3 << 16;   /* Module is disabled and cannot be accessed */
    120    return ret;
    121 }
    122 
    123 /* ----------------------------------------------------------------------------------------------- */
    124 /* PWM init
    125  * iolib_init will run this function automatically
    126  *
    127  *      @return         : 1 for success , 0 for failed
    128  */
    129 
    130 int BBBIO_PWM_Init()
    131 {
    132    int i = 0;
    133 
    134    if (memh == 0) {
    135 #ifdef BBBIO_LIB_DBG
    136        printf("BBBIO_PWM_Init: memory not mapped?\n");
    137 #endif
    138        return 0;
    139        }
    140 
    141    /* Create Memory map */
    142    for (i = 0 ; i < 3 ; i ++) {
    143        pwmss_ptr[i] = mmap(0, PWMSS_MMAP_LEN, PROT_READ | PROT_WRITE, MAP_SHARED, memh, PWMSS_AddressOffset[i]);
    144        if(pwmss_ptr[i] == MAP_FAILED) {
    145 #ifdef BBBIO_LIB_DBG
    146            printf("BBBIO_PWM_Init: PWMSS %d mmap failure!\n", i);
    147 #endif
    148            goto INIT_ERROR ;
    149        }
    150        ecap_ptr[i] = (void *)pwmss_ptr[i] + 0x100 ;
    151        eqep_ptr[i] = (void *)pwmss_ptr[i] + 0x180 ;
    152        epwm_ptr[i] = (void *)pwmss_ptr[i] + 0x200 ;
    153 
    154        if(!PWMSS_module_ctrl(i, 1)) {
    155 #ifdef BBBIO_LIB_DBG
    156            printf("BBBIO_PWM_Init: PWMSS %d clock  failure!\n", i);
    157 #endif
    158            goto INIT_ERROR ;
    159        }
    160        }
    161    return 1;
    162 
    163 INIT_ERROR :
    164    BBBIO_PWM_Release();
     204static void module_clk_config(uint32_t pwmss_id)
     205{
     206        if(pwmss_id == 0)
     207        {
     208                REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS0_CLKCTRL) |=
     209                        AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_ENABLE;
     210   
     211    while(AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_ENABLE !=
     212              (REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS0_CLKCTRL) &
     213               AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE));
     214
     215    while((AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_FUNC <<
     216               AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_SHIFT) !=
     217              (REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS0_CLKCTRL) &
     218               AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST));
     219        }
     220        else if(pwmss_id == 1)
     221        {
     222                REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS1_CLKCTRL) |=
     223                        AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_ENABLE;
     224   while(AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_ENABLE !=
     225              (REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS1_CLKCTRL) &
     226               AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE));
     227
     228        while((AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_FUNC <<
     229               AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_SHIFT) !=
     230               (REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS1_CLKCTRL) &
     231               AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST));
     232        }
     233        else if(pwmss_id == 2)
     234        {
     235                REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS2_CLKCTRL) |=
     236                        AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_ENABLE;
     237   while(AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_ENABLE !=
     238              (REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS2_CLKCTRL) &
     239               AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE));
     240
     241        while((AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_FUNC <<
     242               AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_SHIFT) !=
     243               (REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS2_CLKCTRL) &
     244                AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST));
     245        }
     246        else
     247        {
     248       printf("Please enter valid pwm Id \n");
     249        }
     250}
     251
     252bool beagle_pwm_init(uint32_t pwmss_id)
     253{
     254  bool status = true;
     255  if((pwmss_id <3) && (pwmss_id >=0))
     256  {
     257  module_clk_config(pwmss_id);
     258  epwm_clock_enable(pwmss_id);
     259  pwmss_tbclk_enable(pwmss_id);
     260  return status;
     261  }
     262  else {
     263   status =false;
     264  return status;
     265  }
     266}
     267
     268int beagle_pwmss_setting(uint32_t pwm_id, float pwm_freq, float dutyA, float dutyB)
     269
     270  uint32_t baseAddr;
     271  int status = 1;
     272   
     273  if(pwm_freq <= 0.5) {
     274   status =0;
     275   return status;
     276  }
     277  if(dutyA < 0.0f || dutyA > 100.0f || dutyB < 0.0f || dutyB > 100.0f) {
     278   status = 0;
     279   return status;
     280  }
     281  dutyA /= 100.0f;
     282  dutyB /= 100.0f;
     283
     284  /*Compute necessary TBPRD*/
     285  float Cyclens = 0.0f;
     286  float Divisor =0;
     287  int i,j;
     288  const float CLKDIV_div[] = {1.0,2.0,4.0,8.0,16.0,32.0,64.0,128.0};
     289  const float HSPCLKDIV_div[] = {1.0, 2.0, 4.0, 6.0, 8.0, 10.0,12.0, 14.0};
     290  int NearCLKDIV =7;
     291  int NearHSPCLKDIV =7;
     292  int NearTBPRD =0;
     293
     294  /** 10^9 /Hz compute time per cycle (ns) */
     295  Cyclens = 1000000000.0f / pwm_freq;
     296
     297  /** am335x provide (128* 14) divider and per TBPRD means 10ns when divider
     298    * and max TBPRD is 65535 so max cycle is 128 * 8 * 14 * 65535 * 10ns */
     299  Divisor = (Cyclens / 655350.0f);
     300   
     301  if(Divisor > (128 * 14)) {
     302   printf("Can't generate %f HZ",pwm_freq);
    165303   return 0;
    166 }
    167 
    168 /* ----------------------------------------------------------------------------------------------- */
    169 void BBBIO_PWM_Release()
    170 {
    171    int i = 0;
    172    for(i = 0 ; i < 3 ; i ++) {
    173        if(pwmss_ptr[i] != NULL) {
    174            munmap((void *)pwmss_ptr[i], PWMSS_MMAP_LEN);
    175            pwmss_ptr[i] = NULL;
    176            ecap_ptr[i] = NULL;
    177            eqep_ptr[i] = NULL;
    178            epwm_ptr[i] = NULL;
     304  }
     305  else {
     306   for (i=0;i<8;i++) {
     307       for(j=0 ; j<8; j++) {
     308           if((CLKDIV_div[i] * HSPCLKDIV_div[j]) < (CLKDIV_div[NearCLKDIV]
     309                       * HSPCLKDIV_div[NearHSPCLKDIV]) && (CLKDIV_div[i] * HSPCLKDIV_div[j] > Divisor)) {
     310               NearCLKDIV = i;
     311               NearHSPCLKDIV = j;
     312           }
    179313       }
    180314   }
    181 }
    182 
    183 /* ----------------------------------------------------------------------------------------------- */
    184 /* PWMSS status (no effect now)
    185  *     set pluse rgument of epwm module
    186  *
    187  *      @param PWMID    : EPWMSS number , 0~3
    188  *
    189  *      @return         : 1 for success , 0 for failed
     315  baseAddr = select_pwmss(pwm_id);
     316  REG16(baseAddr + AM335X_EPWM_TBCTL) &= ~(AM335X_TBCTL_CLKDIV_MASK | AM335X_TBCTL_HSPCLKDIV_MASK);
     317           
     318  REG16(baseAddr + AM335X_EPWM_TBCTL) = (REG16(baseAddr + AM335X_EPWM_TBCTL) &
     319  (~AM335X_EPWM_TBCTL_CLKDIV)) | ((NearCLKDIV
     320  << AM335X_EPWM_TBCTL_CLKDIV_SHIFT) & AM335X_EPWM_TBCTL_CLKDIV);
     321
     322  REG16(baseAddr + AM335X_EPWM_TBCTL) = (REG16(baseAddr + AM335X_EPWM_TBCTL) &
     323  (~AM335X_EPWM_TBCTL_HSPCLKDIV)) | ((NearHSPCLKDIV <<
     324  AM335X_EPWM_TBCTL_HSPCLKDIV_SHIFT) & AM335X_EPWM_TBCTL_HSPCLKDIV);
     325
     326  NearTBPRD = (Cyclens / (10.0 * CLKDIV_div[NearCLKDIV] * HSPCLKDIV_div[NearHSPCLKDIV]));
     327       
     328  REG16(baseAddr + AM335X_EPWM_TBCTL) = (REG16(baseAddr + AM335X_EPWM_TBCTL) &
     329  (~AM335X_EPWM_PRD_LOAD_SHADOW_MASK)) | (((bool)AM335X_EPWM_SHADOW_WRITE_DISABLE <<
     330  AM335X_EPWM_TBCTL_PRDLD_SHIFT) & AM335X_EPWM_PRD_LOAD_SHADOW_MASK);
     331
     332  REG16(baseAddr + AM335X_EPWM_TBCTL) = (REG16(baseAddr + AM335X_EPWM_TBCTL) &
     333  (~AM335X_EPWM_COUNTER_MODE_MASK)) | (((unsigned int)AM335X_EPWM_COUNT_UP <<
     334  AM335X_TBCTL_CTRMODE_SHIFT) &  AM335X_EPWM_COUNTER_MODE_MASK);
     335
     336  /*setting clock divider and freeze time base*/
     337  REG16(baseAddr + AM335X_EPWM_CMPB) = (unsigned short)((float)(NearTBPRD) * dutyB);
     338  REG16(baseAddr + AM335X_EPWM_CMPA) = (unsigned short)((float)(NearTBPRD) * dutyA);
     339  REG16(baseAddr + AM335X_EPWM_TBPRD) = (unsigned short)NearTBPRD;
     340  REG16(baseAddr + AM335X_EPWM_TBCNT) = 0;
     341  }
     342  return status;
     343}
     344
     345bool beagle_ehrpwm_enable(uint32_t pwmid)
     346{
     347  bool status = true;
     348  uint32_t baseAddr;
     349  if((pwmid<3) && (pwmid >=0)) {
     350  baseAddr = select_pwmss(pwmid);
     351  REG16(baseAddr + AM335X_EPWM_AQCTLA) = AM335X_EPWM_AQCTLA_ZRO_XAHIGH | (AM335X_EPWM_AQCTLA_CAU_EPWMXATOGGLE << AM335X_EPWM_AQCTLA_CAU_SHIFT);
     352  REG16(baseAddr + AM335X_EPWM_AQCTLB) = AM335X_EPWM_AQCTLB_ZRO_XBHIGH | (AM335X_EPWM_AQCTLB_CBU_EPWMXBTOGGLE << AM335X_EPWM_AQCTLB_CBU_SHIFT);
     353  REG16(baseAddr + AM335X_EPWM_TBCNT) = 0;
     354  REG16(baseAddr + AM335X_EPWM_TBCTL) |=  AM335X_TBCTL_FREERUN  | AM335X_TBCTL_CTRMODE_UP;
     355  return status;
     356  }
     357  else {
     358   status =false;
     359   return status;
     360  }
     361}
     362
     363bool beagle_ehrpwm_disable(uint32_t pwmid)
     364{
     365  bool status = true;
     366  uint32_t baseAddr;
     367  if((pwmid<3) && (pwmid >=0)) {
     368  baseAddr = select_pwmss(pwmid);
     369  REG16(baseAddr + AM335X_EPWM_TBCTL) = AM335X_EPWM_TBCTL_CTRMODE_STOPFREEZE;
     370  REG16(baseAddr + AM335X_EPWM_AQCTLA) = AM335X_EPWM_AQCTLA_ZRO_XALOW | (AM335X_EPWM_AQCTLA_CAU_EPWMXATOGGLE << AM335X_EPWM_AQCTLA_CAU_SHIFT);
     371  REG16(baseAddr + AM335X_EPWM_AQCTLB) = AM335X_EPWM_AQCTLA_ZRO_XBLOW | (AM335X_EPWM_AQCTLB_CBU_EPWMXBTOGGLE << AM335X_EPWM_AQCTLB_CBU_SHIFT);
     372  REG16(baseAddr + AM335X_EPWM_TBCNT)  = 0;
     373  return status;
     374  }
     375  else {
     376   status = false;
     377   return status;
     378  }
     379}
     380
     381#endif
     382
     383/* For support of BeagleboardxM */
     384#if IS_DM3730
     385
     386/* Currently this section is just to satisfy
     387 * GPIO API and to make the build successful.
     388 * Later on support can be added here.
    190389 */
    191 int BBBIO_PWMSS_Status(unsigned int PWMID)
    192 {
    193    int param_error = 1;
    194    volatile unsigned int* reg;
    195    unsigned int reg_value ;
    196 
    197    if (memh == 0)
    198             param_error = 0;
    199 
    200        if (PWMID > 2)      /* if input is not EPWMSS 0~ WPEMSS 2 */
    201             param_error = 0;
    202 
    203        if (param_error == 0) {
    204 #ifdef BBBIO_LIB_DBG
    205        printf("BBBIO_PWM_Status: parameter error!\n");
     390uint32_t select_pwmss(uint32_t pwm_id)
     391{
     392return -1;
     393}
     394bool pwmss_tbclk_enable(unsigned int instance)
     395{
     396return false;
     397}
     398bool beagle_pwm_init(uint32_t pwmss_id)
     399{
     400return false;
     401}
     402bool beagle_ehrpwm_disable(uint32_t pwmid)
     403{
     404return false;
     405}
     406bool beagle_ehrpwm_enable(uint32_t pwmid)
     407{
     408return false;
     409}
     410int beagle_pwmss_setting(uint32_t pwm_id, float pwm_freq, float dutyA, float dutyB)
     411{
     412return -1;
     413}
     414bool beagle_epwm_pinmux_setup(uint32_t pin_no, uint32_t pwm_id)
     415{
     416return false;
     417}
     418
    206419#endif
    207        return 0;
    208    }
    209 
    210    reg =(void *)CM_ptr + BBBIO_PWMSS_CTRL;
    211 
    212    reg_value = *reg >> PWMID & 0x01 ;
    213    if(reg_value == 0) {
    214        printf("PWMSS [%d] Timebase clock Disable , Control Module [pwmss_ctrl register]\n", PWMID);
    215    }
    216    else {
    217        reg=(void *)pwmss_ptr[PWMID] + PWMSS_CLKSTATUS;
    218        reg_value = *reg ;
    219 
    220        printf("PWMSS [%d] :\tCLKSTOP_ACK %d , CLK_EN_ACK %d , CLKSTOP_ACK %d , CLK_EN_ACK %d , CLKSTOP_ACK %d , CLK_EN_ACK %d\n",
    221            PWMID ,
    222            reg_value >>9 & 0x1 ,
    223            reg_value >>8 & 0x1 ,
    224            reg_value >>5 & 0x1 ,
    225            reg_value >>4 & 0x1 ,
    226            reg_value >>1 & 0x1 ,
    227            reg_value >>0 & 0x1 );
    228    }
    229    return 1 ;
    230 }
    231 /* ----------------------------------------------------------------------------------------------- */
    232 /* PWMSS setting
    233  *     set pluse rgument of epwm module
    234  *
    235  *      @param PWMID    : EPWMSS number , 0~2
    236  *      @param HZ      : pluse HZ
    237  *      @param dutyA    : Duty Cycle in ePWM A
    238  *      @param dutyB    : Duty Cycle in ePWM B
    239  *
    240  *      @return         : 1 for success , 0 for failed
    241  *
    242  *      @example        :  BBBIO_PWMSS_Setting(0 , 50.0f , 50.0f , 25.0f);     // Generate 50HZ pwm in PWM0 ,
    243  *                                     // duty cycle is 50% for ePWM0A , 25% for ePWM0B
    244  *
    245  *     @Note :
    246  *         find an number nearst 65535 for TBPRD , to improve duty precision,
    247  *
    248  *     Using big TBPRD can increase the range of CMPA and CMPB ,
    249  *         and it means we can get better precision on duty cycle.
    250  *
    251  *     EX : 20.25% duty cycle
    252  *                  on TBPRD = 62500 , CMPA = 12656.25 ( .25 rejection) , real duty : 20.2496% (12656 /62500)
    253  *                  on TBPRD = 6250  , CMPA = 1265.625 ( .625 rejection), real duty : 20.24%   (1265 6250)
    254  *                  on TBPRD = 500   , CMPA = 101.25   ( .25 rejection) , real duty : 20.2%    (101/500)
    255  *
    256  *     Divisor = CLKDIV * HSPCLKDIV
    257  *                 1 TBPRD : 10 ns (default)
    258  *         65535 TBPRD : 655350 ns
    259  *         65535 TBPRD : 655350 * Divisor ns  = X TBPRD : Cyclens
    260  *
    261  *         accrooding to that , we must find a Divisor value , let X nearest 65535 .
    262  *         so , Divisor must  Nearest Cyclens/655350
    263 */
    264 
    265 int BBBIO_PWMSS_Setting(unsigned int PWMID , float HZ ,float dutyA ,float dutyB)
    266 {
    267    int param_error = 1;
    268    volatile unsigned short* reg16 ;
    269         if (memh == 0)
    270             param_error = 0;
    271         if (PWMID > 2)              // if input is not EPWMSS 0~ WPEMSS 2
    272             param_error = 0;
    273    if (HZ < 0 )
    274        param_error = 0;
    275    if(dutyA < 0.0f || dutyA > 100.0f || dutyB < 0.0f || dutyB > 100.0f)
    276        param_error = 0;
    277 
    278         if (param_error == 0) {
    279 #ifdef BBBIO_LIB_DBG
    280        printf("BBBIO_PWMSS_Setting: parameter error!\n");
    281 #endif
    282        return 0;
    283         }
    284 
    285    dutyA /= 100.0f ;
    286    dutyB /= 100.0f ;
    287 
    288    /* compute neccessary TBPRD */
    289    float Cyclens =0.0f ;
    290    float Divisor =0;
    291    int i , j ;
    292    const float CLKDIV_div[] = {1.0 ,2.0 ,4.0 ,8.0 ,16.0 ,32.0 , 64.0 , 128.0};
    293    const float HSPCLKDIV_div[] ={1.0 ,2.0 ,4.0 ,6.0 ,8.0 ,10.0 , 12.0 , 14.0};
    294    int NearCLKDIV =7;
    295    int NearHSPCLKDIV =7;
    296    int NearTBPRD =0;
    297 
    298    Cyclens = 1000000000.0f / HZ ; /* 10^9 / HZ , comput time per cycle (ns) */
    299 
    300 
    301    Divisor =  (Cyclens / 655350.0f) ;  /* am335x provide (128*14) divider , and per TBPRD means 10 ns when divider /1 ,
    302                         * and max TBPRD is 65535 , so , the max cycle is 128*14* 65535 *10ns
    303                         */
    304 #ifdef BBBIO_LIB_DBG
    305    printf("Cyclens %f , Divisor %f\n", Cyclens, Divisor);
    306 #endif
    307 
    308    if(Divisor > (128 * 14)) {
    309 #ifdef BBBIO_LIB_DBG
    310        printf("BBBIO_PWMSS_Setting : Can't generate %f HZ \n", HZ);
    311 #endif
    312        return 0;
    313    }
    314    else {
    315        /* using Exhaustive Attack metho */
    316        for(i = 0 ; i < 8 ; i ++) {
    317            for(j = 0 ; j < 8 ; j ++) {
    318                if((CLKDIV_div[i] * HSPCLKDIV_div[j]) < (CLKDIV_div[NearCLKDIV] * HSPCLKDIV_div[NearHSPCLKDIV]) &&
    319                  ((CLKDIV_div[i] * HSPCLKDIV_div[j]) > Divisor)) {
    320                    NearCLKDIV = i ;
    321                    NearHSPCLKDIV = j ;
    322                }
    323            }
    324        }
    325 #ifdef BBBIO_LIB_DBG
    326        printf("nearest CLKDIV %f , HSPCLKDIV %f\n" ,CLKDIV_div[NearCLKDIV] ,HSPCLKDIV_div[NearHSPCLKDIV]);
    327 #endif
    328        NearTBPRD = (Cyclens / (10.0 *CLKDIV_div[NearCLKDIV] *HSPCLKDIV_div[NearHSPCLKDIV])) ;
    329 
    330 #ifdef BBBIO_LIB_DBG
    331        printf("nearest TBPRD %d, %f %f\n ",NearTBPRD,NearTBPRD * dutyA, NearTBPRD * dutyB);
    332 #endif
    333 
    334        /* setting clock diver and freeze time base */
    335        reg16=(void*)epwm_ptr[PWMID] +EPWM_TBCTL;
    336        *reg16 = TBCTL_CTRMODE_FREEZE | (NearCLKDIV << 10) | (NearHSPCLKDIV << 7);
    337 
    338        /*  setting duty A and duty B */
    339        reg16=(void*)epwm_ptr[PWMID] +EPWM_CMPB;
    340        *reg16 =(unsigned short)((float)NearTBPRD * dutyB);
    341 
    342        reg16=(void*)epwm_ptr[PWMID] +EPWM_CMPA;
    343        *reg16 =(unsigned short)((float)NearTBPRD * dutyA);
    344 
    345        reg16=(void*)epwm_ptr[PWMID] +EPWM_TBPRD;
    346        *reg16 =(unsigned short)NearTBPRD;
    347 
    348        /* reset time base counter */
    349        reg16 = (void *)epwm_ptr[PWMID] + EPWM_TBCNT;
    350        *reg16 = 0;
    351    }
    352    return 1;
    353 }
    354 /* ----------------------------------------------------------------------------------------------- */
    355 /* Enable/Disable ehrPWM module
    356  *      @param PWMID    : PWMSS number , 0~2
    357  *
    358  *      @return         : void
    359  *
    360  *      @example        : BBBIO_PWMSS_Enable(0) ;// Enable PWMSS 0
    361  */
    362 
    363 void BBBIO_ehrPWM_Enable(unsigned int PWMSS_ID)
    364 {
    365    volatile unsigned short *reg16 ;
    366 
    367    reg16=(void*)epwm_ptr[PWMSS_ID] +EPWM_AQCTLA;
    368    *reg16 = 0x2 | ( 0x3 << 4) ;
    369        
    370    reg16=(void*)epwm_ptr[PWMSS_ID] +EPWM_AQCTLB;
    371    *reg16 = 0x2 | ( 0x3 << 8) ;
    372 
    373    reg16 = (void *)epwm_ptr[PWMSS_ID] + EPWM_TBCNT;
    374    *reg16 = 0;
    375 
    376         reg16=(void *)epwm_ptr[PWMSS_ID] + EPWM_TBCTL;
    377    *reg16 &= ~0x3;
    378 }
    379 
    380 void BBBIO_ehrPWM_Disable(unsigned int PWMSS_ID)
    381 {
    382    volatile unsigned short *reg16 ;
    383         reg16=(void *)epwm_ptr[PWMSS_ID] + EPWM_TBCTL;
    384         *reg16 |= 0x3;
    385 
    386    reg16=(void*)epwm_ptr[PWMSS_ID] +EPWM_AQCTLA;
    387    *reg16 = 0x1 | ( 0x3 << 4) ;
    388        
    389    reg16=(void*)epwm_ptr[PWMSS_ID] +EPWM_AQCTLB;
    390    *reg16 = 0x1 | ( 0x3 << 8) ;
    391 
    392    reg16 = (void *)epwm_ptr[PWMSS_ID] + EPWM_TBCNT;
    393    *reg16 = 0;
    394 }
    395 //--------------------------------------------------------
    396 
    397 
    398 
    399 
    400 
    401 
    402 
    403 
    404 
    405 
    406 
    407 
  • c/src/lib/libcpu/arm/shared/include/am335x.h

    r6dc5c03f r5e3096db  
    469469#define AM335X_CONF_USB0_DRVVBUS 0xA1C
    470470#define AM335X_CONF_USB1_DRVVBUS 0xA34
     471
     472/* Registers for PWM Subsystem */
     473#define AM335X_PWMSS_CTRL      (0x664)
     474#define AM335X_CM_PER_EPWMSS0_CLKCTRL    (0xD4)
     475#define AM335X_CM_PER_EPWMSS1_CLKCTRL    (0xCC)
     476#define AM335X_CM_PER_EPWMSS2_CLKCTRL    (0xD8)
     477#define AM335X_CONTROL_MODULE      (0x44e10000)
     478#define AM335X_CM_PER_ADDR     (0x44e00000)
     479#define AM335X_PWMSS_CLKSTATUS         (0xC)
     480#define AM335X_PWMSS0_MMAP_ADDR        0x48300000
     481#define AM335X_PWMSS1_MMAP_ADDR        0x48302000
     482#define AM335X_PWMSS2_MMAP_ADDR        0x48304000
     483#define AM335X_PWMSS_MMAP_LEN          0x1000
     484#define AM335X_PWMSS_IDVER         0x0
     485#define AM335X_PWMSS_SYSCONFIG     0x4
     486#define AM335X_PWMSS_CLKCONFIG     0x8
     487#define AM335X_PWMSS_CLK_EN_ACK        0x100
     488#define AM335X_PWMSS_CLKSTATUS     0xC
     489#define AM335X_EPWM_TBCTL          0x0
     490#define AM335X_EPWM_TBSTS          0x2
     491#define AM335X_EPWM_TBPHSHR        0x4
     492#define AM335X_EPWM_TBPHS          0x6
     493#define AM335X_EPWM_TBCNT          0x8
     494#define AM335X_EPWM_TBPRD          0xA
     495#define AM335X_EPWM_CMPCTL         0xE
     496#define AM335X_EPWM_CMPAHR         0x10
     497#define AM335X_EPWM_CMPA           0x12
     498#define AM335X_EPWM_CMPB           0x14
     499#define AM335X_EPWM_AQCTLA         0x16
     500#define AM335X_EPWM_AQCTLB         0x18
     501#define AM335X_EPWM_AQSFRC         0x1A
     502#define AM335X_EPWM_AQCSFRC        0x1C
     503#define AM335X_EPWM_DBCTL          0x1E
     504#define AM335X_EPWM_DBRED          0x20
     505#define AM335X_EPWM_DBFED          0x22
     506#define AM335X_TBCTL_CTRMODE_UP        0x0
     507#define AM335X_TBCTL_CTRMODE_DOWN      0x1
     508#define AM335X_TBCTL_CTRMODE_UPDOWN    0x2
     509#define AM335X_TBCTL_CTRMODE_FREEZE    0x3
     510#define AM335X_EPWM_AQCTLA_ZRO_XALOW         (0x0001u)
     511#define AM335X_EPWM_AQCTLA_ZRO_XAHIGH        (0x0002u)
     512#define AM335X_EPWM_AQCTLA_CAU_EPWMXATOGGLE   (0x0003u)
     513#define AM335X_EPWM_AQCTLA_CAU_SHIFT          (0x0004u)
     514#define AM335X_EPWM_AQCTLA_ZRO_XBLOW         (0x0001u)
     515#define AM335X_EPWM_AQCTLB_ZRO_XBHIGH        (0x0002u)
     516#define AM335X_EPWM_AQCTLB_CBU_EPWMXBTOGGLE   (0x0003u)
     517#define AM335X_EPWM_AQCTLB_CBU_SHIFT          (0x0008u)
     518#define AM335X_EPWM_TBCTL_CTRMODE_STOPFREEZE  (0x0003u)
     519#define AM335X_PWMSS_CTRL_PWMSS0_TBCLKEN      (0x00000001u)
     520#define AM335X_PWMSS_CTRL_PWMSS1_TBCLKEN      (0x00000002u)
     521#define AM335X_PWMSS_CTRL_PWMSS2_TBCLKEN      (0x00000004u)
     522#define AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
     523#define AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
     524#define AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
     525#define AM335X_TBCTL_CLKDIV_MASK              (3 << 10)
     526#define AM335X_TBCTL_HSPCLKDIV_MASK           (3 << 7)
     527#define AM335X_EPWM_TBCTL_CLKDIV              (0x1C00u)
     528#define AM335X_EPWM_TBCTL_CLKDIV_SHIFT        (0x000Au)
     529#define AM335X_EPWM_TBCTL_HSPCLKDIV           (0x0380u)
     530#define AM335X_EPWM_TBCTL_HSPCLKDIV_SHIFT     (0x0007u)
     531#define AM335X_EPWM_TBCTL_PRDLD               (0x0008u)
     532#define AM335X_EPWM_PRD_LOAD_SHADOW_MASK      AM335X_EPWM_TBCTL_PRDLD
     533#define AM335X_EPWM_SHADOW_WRITE_ENABLE       0x0
     534#define AM335X_EPWM_SHADOW_WRITE_DISABLE      0x1
     535#define AM335X_EPWM_TBCTL_PRDLD_SHIFT         (0x0003u)
     536#define AM335X_EPWM_TBCTL_CTRMODE             (0x0003u)
     537#define AM335X_EPWM_COUNTER_MODE_MASK         AM335X_EPWM_TBCTL_CTRMODE
     538#define AM335X_TBCTL_FREERUN                  (2 << 14)
     539#define AM335X_TBCTL_CTRMODE_UP               (0x0000u)
     540#define AM335X_TBCTL_CTRMODE_SHIFT            (0x0000u)
     541#define AM335X_EPWM_COUNT_UP                  (AM335X_TBCTL_CTRMODE_UP << \
     542                                                     AM335X_TBCTL_CTRMODE_SHIFT)
     543
     544#define AM335X_EPWM_REGS                       (0x00000200)
     545#define AM335X_EPWM_0_REGS                     (AM335X_PWMSS0_MMAP_ADDR + AM335X_EPWM_REGS)
     546#define AM335X_EPWM_1_REGS                     (AM335X_PWMSS1_MMAP_ADDR + AM335X_EPWM_REGS)
     547#define AM335X_EPWM_2_REGS                     (AM335X_PWMSS2_MMAP_ADDR + AM335X_EPWM_REGS)
     548
     549#define AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE   (0x00000003u)
     550#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_FUNC  (0x0u)
     551#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_SHIFT (0x00000010u)
     552#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST       (0x00030000u)
     553
     554#define AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE   (0x00000003u)
     555#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST       (0x00030000u)
     556#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_FUNC  (0x0u)
     557#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_SHIFT (0x00000010u)
     558
     559#define AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE   (0x00000003u)
     560#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_FUNC  (0x0u)
     561#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_SHIFT (0x00000010u)
     562#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST       (0x00030000u)
     563
     564
     565
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