Changeset 5e14d89 in rtems


Ignore:
Timestamp:
Sep 11, 2006, 9:41:56 PM (14 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
957d886
Parents:
ea1d598
Message:

2006-09-11 Joel Sherrill <joel@…>

  • at91rm9200/include/at91rm9200.h, at91rm9200/include/at91rm9200_dbgu.h, at91rm9200/include/at91rm9200_emac.h, at91rm9200/include/at91rm9200_gpio.h, at91rm9200/include/at91rm9200_mem.h, at91rm9200/include/at91rm9200_pmc.h, s3c2400/include/s3c2400.h: Convert C++ style comments to C style.
Location:
c/src/lib/libcpu/arm
Files:
8 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/arm/ChangeLog

    rea1d598 r5e14d89  
     12006-09-11      Joel Sherrill <joel@OARcorp.com>
     2
     3        * at91rm9200/include/at91rm9200.h,
     4        at91rm9200/include/at91rm9200_dbgu.h,
     5        at91rm9200/include/at91rm9200_emac.h,
     6        at91rm9200/include/at91rm9200_gpio.h,
     7        at91rm9200/include/at91rm9200_mem.h,
     8        at91rm9200/include/at91rm9200_pmc.h, s3c2400/include/s3c2400.h:
     9        Convert C++ style comments to C style.
     10
    1112006-09-11      Chris Johns <chrisj@rtems.org>
    212
  • c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200.h

    rea1d598 r5e14d89  
    3333/* Register Offsets */
    3434/* offsets from AIC_SMR_BASE and AIC_SVR_BASE */
    35 #define AIC_SMR_FIQ             0x00    // Advanced Interrupt Controller FIQ
    36 #define AIC_SMR_SYSIRQ          0x04    // Advanced Interrupt Controller SYSIRQ
    37 #define AIC_SMR_PIOA            0x08    // Parallel I/O Controller A
    38 #define AIC_SMR_PIOB            0x0c    // Parallel I/O Controller B
    39 #define AIC_SMR_PIOC            0x10    // Parallel I/O Controller C
    40 #define AIC_SMR_PIOD            0x14    // Parallel I/O Controller D
    41 #define AIC_SMR_US0             0x18    // USART 0
    42 #define AIC_SMR_US1             0x1c    // USART 1
    43 #define AIC_SMR_US2             0x20    // USART 2
    44 #define AIC_SMR_US3             0x24    // USART 3
    45 #define AIC_SMR_MCI             0x28    // Multimedia Card Interface
    46 #define AIC_SMR_UDP             0x2c    // USB Device Port
    47 #define AIC_SMR_TWI             0x30    // Two-wire Interface
    48 #define AIC_SMR_SPI             0x34    // Serial Peripheral Interface
    49 #define AIC_SMR_SSC0            0x38    // Synchronous Serial Controller 0
    50 #define AIC_SMR_SSC1            0x3c    // Synchronous Serial Controller 1
    51 #define AIC_SMR_SSC2            0x40    // Synchronous Serial Controller 2
    52 #define AIC_SMR_TC0             0x44    // Timer/Counter 0
    53 #define AIC_SMR_TC1             0x48    // Timer/Counter 1
    54 #define AIC_SMR_TC2             0x4c    // Timer/Counter 2
    55 #define AIC_SMR_TC3             0x50    // Timer/Counter 3
    56 #define AIC_SMR_TC4             0x54    // Timer/Counter 4
    57 #define AIC_SMR_TC5             0x58    // Timer/Counter 5
    58 #define AIC_SMR_UHP             0x5c    // USB Host Port
    59 #define AIC_SMR_EMAC            0x60    // Ethernet MAC
    60 #define AIC_SMR_IRQ0            0x64    // Advanced Interrupt Controller IRQ0
    61 #define AIC_SMR_IRQ1            0x68    // Advanced Interrupt Controller IRQ1
    62 #define AIC_SMR_IRQ2            0x6c    // Advanced Interrupt Controller IRQ2
    63 #define AIC_SMR_IRQ3            0x70    // Advanced Interrupt Controller IRQ3
    64 #define AIC_SMR_IRQ4            0x74    // Advanced Interrupt Controller IRQ4
    65 #define AIC_SMR_IRQ5            0x78    // Advanced Interrupt Controller IRQ5
    66 #define AIC_SMR_IRQ6            0x7c    // Advanced Interrupt Controller IRQ6
     35#define AIC_SMR_FIQ             0x00    /* Advanced Interrupt Controller FIQ */
     36#define AIC_SMR_SYSIRQ          0x04    /* Advanced Interrupt Controller SYSIRQ */
     37#define AIC_SMR_PIOA            0x08    /* Parallel I/O Controller A */
     38#define AIC_SMR_PIOB            0x0c    /* Parallel I/O Controller B */
     39#define AIC_SMR_PIOC            0x10    /* Parallel I/O Controller C */
     40#define AIC_SMR_PIOD            0x14    /* Parallel I/O Controller D */
     41#define AIC_SMR_US0             0x18    /* USART 0 */
     42#define AIC_SMR_US1             0x1c    /* USART 1 */
     43#define AIC_SMR_US2             0x20    /* USART 2 */
     44#define AIC_SMR_US3             0x24    /* USART 3 */
     45#define AIC_SMR_MCI             0x28    /* Multimedia Card Interface */
     46#define AIC_SMR_UDP             0x2c    /* USB Device Port */
     47#define AIC_SMR_TWI             0x30    /* Two-wire Interface */
     48#define AIC_SMR_SPI             0x34    /* Serial Peripheral Interface */
     49#define AIC_SMR_SSC0            0x38    /* Synchronous Serial Controller 0 */
     50#define AIC_SMR_SSC1            0x3c    /* Synchronous Serial Controller 1 */
     51#define AIC_SMR_SSC2            0x40    /* Synchronous Serial Controller 2 */
     52#define AIC_SMR_TC0             0x44    /* Timer/Counter 0 */
     53#define AIC_SMR_TC1             0x48    /* Timer/Counter 1 */
     54#define AIC_SMR_TC2             0x4c    /* Timer/Counter 2 */
     55#define AIC_SMR_TC3             0x50    /* Timer/Counter 3 */
     56#define AIC_SMR_TC4             0x54    /* Timer/Counter 4 */
     57#define AIC_SMR_TC5             0x58    /* Timer/Counter 5 */
     58#define AIC_SMR_UHP             0x5c    /* USB Host Port */
     59#define AIC_SMR_EMAC            0x60    /* Ethernet MAC */
     60#define AIC_SMR_IRQ0            0x64    /* Advanced Interrupt Controller IRQ0 */
     61#define AIC_SMR_IRQ1            0x68    /* Advanced Interrupt Controller IRQ1 */
     62#define AIC_SMR_IRQ2            0x6c    /* Advanced Interrupt Controller IRQ2 */
     63#define AIC_SMR_IRQ3            0x70    /* Advanced Interrupt Controller IRQ3 */
     64#define AIC_SMR_IRQ4            0x74    /* Advanced Interrupt Controller IRQ4 */
     65#define AIC_SMR_IRQ5            0x78    /* Advanced Interrupt Controller IRQ5 */
     66#define AIC_SMR_IRQ6            0x7c    /* Advanced Interrupt Controller IRQ6 */
    6767
    6868/* from AIC_CTL_BASE */
    69 #define AIC_IVR                 0x00    // IRQ Vector Register
    70 #define AIC_FVR                 0x04    // FIQ Vector Register
    71 #define AIC_ISR                 0x08    // Interrupt Status Register
    72 #define AIC_IPR                 0x0C    // Interrupt Pending Register
    73 #define AIC_IMR                 0x10    // Interrupt Mask Register
    74 #define AIC_CISR                0x14    // Core Interrupt Status Register
    75 #define AIC_IECR                0x20    // Interrupt Enable Command Register
    76 #define AIC_IDCR                0x24    // Interrupt Disable Command Register
    77 #define AIC_ICCR                0x28    // Interrupt Clear Command Register
    78 #define AIC_ISCR                0x2C    // Interrupt Set Command Register
    79 #define AIC_EOICR               0x30    // End of Interrupt Command Register
    80 #define AIC_SPU                 0x34    // Spurious Vector Register
    81 #define AIC_DCR                 0x38    // Debug Control Register (Protect)
    82 #define AIC_FFER                0x40    // Fast Forcing Enable Register
    83 #define AIC_FFDR                0x44    // Fast Forcing Disable Register
    84 #define AIC_FFSR                0x48    // Fast Forcing Status Register
     69#define AIC_IVR                 0x00    /* IRQ Vector Register */
     70#define AIC_FVR                 0x04    /* FIQ Vector Register */
     71#define AIC_ISR                 0x08    /* Interrupt Status Register */
     72#define AIC_IPR                 0x0C    /* Interrupt Pending Register */
     73#define AIC_IMR                 0x10    /* Interrupt Mask Register */
     74#define AIC_CISR                0x14    /* Core Interrupt Status Register */
     75#define AIC_IECR                0x20    /* Interrupt Enable Command Register */
     76#define AIC_IDCR                0x24    /* Interrupt Disable Command Register */
     77#define AIC_ICCR                0x28    /* Interrupt Clear Command Register */
     78#define AIC_ISCR                0x2C    /* Interrupt Set Command Register */
     79#define AIC_EOICR               0x30    /* End of Interrupt Command Register */
     80#define AIC_SPU                 0x34    /* Spurious Vector Register */
     81#define AIC_DCR                 0x38    /* Debug Control Register (Protect) */
     82#define AIC_FFER                0x40    /* Fast Forcing Enable Register */
     83#define AIC_FFDR                0x44    /* Fast Forcing Disable Register */
     84#define AIC_FFSR                0x48    /* Fast Forcing Status Register */
    8585
    8686/* Bit Defines */
    8787/* AIC_ISR - Interrupt Status Register */
    88 #define AIC_ISR_IRQID_MASK      0x1f    // current interrupt ID         
    89 
    90 // AIC_CISR - Core Interrupt Status Register
    91 #define AIC_CISR_IRQ            BIT1    // 1 = Core IRQ is active
    92 #define AIC_CISR_FIQ            BIT0    // 1 = Core FIQ is active
    93 
    94 // AIC_DCR - Debug Control Register (Protect)
    95 #define AIC_DCR_GMSK            BIT1    // 0 = AIC controls IRQ and FIQ
    96 #define AIC_DCR_PROT            BIT0    // 1 = enable protection mode
    97 
    98 // AIC_SMR
     88#define AIC_ISR_IRQID_MASK      0x1f    /* current interrupt ID          */
     89
     90/* AIC_CISR - Core Interrupt Status Register */
     91#define AIC_CISR_IRQ            BIT1    /* 1 = Core IRQ is active */
     92#define AIC_CISR_FIQ            BIT0    /* 1 = Core FIQ is active */
     93
     94/* AIC_DCR - Debug Control Register (Protect) */
     95#define AIC_DCR_GMSK            BIT1    /* 0 = AIC controls IRQ and FIQ */
     96#define AIC_DCR_PROT            BIT0    /* 1 = enable protection mode */
     97
     98/* AIC_SMR */
    9999#define AIC_SMR_PRIOR(_x_)      ((_x_ & 0x07) << 0)
    100 #define AIC_SMR_SRC_LVL_LOW     (0 << 5)        // Are these right? docs don't say which is high/low   
     100#define AIC_SMR_SRC_LVL_LOW     (0 << 5)        /* Are these right? docs don't say which is high/low     */
    101101#define AIC_SMR_SRC_EDGE_LOW    (1 << 5)       
    102102#define AIC_SMR_SRC_LVL_HI      (2 << 5)       
     
    109109#define DBGU_REG(_x_)   *(vulong *)(DBGU_BASE + _x_)
    110110
    111 // Register Offsets
    112 #define DBGU_CR                 0x00    // Control Register
    113 #define DBGU_MR                 0x04    // Mode Register
    114 #define DBGU_IER                0x08    // Interrupt Enable Register
    115 #define DBGU_IDR                0x0C    // Interrupt Disable Register
    116 #define DBGU_IMR                0x10    // Interrupt Mask Register
    117 #define DBGU_CSR                0x14    // Channel Status Register
    118 #define DBGU_RHR                0x18    // Receiver Holding Register
    119 #define DBGU_THR                0x1C    // Transmitter Holding Register
    120 #define DBGU_BRGR               0x20    // Baud Rate Generator Register
    121 #define DBGU_C1R                0x40    // Chip ID1 Register
    122 #define DBGU_C2R                0x44    // Chip ID2 Register
    123 #define DBGU_FNTR               0x48    // Force NTRST Register
     111/* Register Offsets */
     112#define DBGU_CR                 0x00    /* Control Register */
     113#define DBGU_MR                 0x04    /* Mode Register */
     114#define DBGU_IER                0x08    /* Interrupt Enable Register */
     115#define DBGU_IDR                0x0C    /* Interrupt Disable Register */
     116#define DBGU_IMR                0x10    /* Interrupt Mask Register */
     117#define DBGU_CSR                0x14    /* Channel Status Register */
     118#define DBGU_RHR                0x18    /* Receiver Holding Register */
     119#define DBGU_THR                0x1C    /* Transmitter Holding Register */
     120#define DBGU_BRGR               0x20    /* Baud Rate Generator Register */
     121#define DBGU_C1R                0x40    /* Chip ID1 Register */
     122#define DBGU_C2R                0x44    /* Chip ID2 Register */
     123#define DBGU_FNTR               0x48    /* Force NTRST Register */
    124124
    125125/****************/
     
    129129#define ST_REG(_x_)             *(vulong *)(ST_BASE + _x_)
    130130
    131 // Register Offsets
    132 #define ST_CR                   0x00    // Control Register
    133 #define ST_PIMR                 0x04    // Period Interval Mode Register
    134 #define ST_WDMR                 0x08    // Watchdog Mode Register
    135 #define ST_RTMR                 0x0C    // Real-time Mode Register
    136 #define ST_SR                   0x10    // Status Register
    137 #define ST_IER                  0x14    // Interrupt Enable Register
    138 #define ST_IDR                  0x18    // Interrupt Disable Register
    139 #define ST_IMR                  0x1C    // Interrupt Mask Register
    140 #define ST_RTAR                 0x20    // Real-time Alarm Register
    141 #define ST_CRTR                 0x24    // Current Real-time Register
    142 
    143 // Bit Defines
    144 // ST_CR - Control Register
    145 #define ST_CR_WDRST                     BIT0    // write 1 to reload WD counter
    146 
    147 // ST_PIMR - Period Interval Mode Register
     131/* Register Offsets */
     132#define ST_CR                   0x00    /* Control Register */
     133#define ST_PIMR                 0x04    /* Period Interval Mode Register */
     134#define ST_WDMR                 0x08    /* Watchdog Mode Register */
     135#define ST_RTMR                 0x0C    /* Real-time Mode Register */
     136#define ST_SR                   0x10    /* Status Register */
     137#define ST_IER                  0x14    /* Interrupt Enable Register */
     138#define ST_IDR                  0x18    /* Interrupt Disable Register */
     139#define ST_IMR                  0x1C    /* Interrupt Mask Register */
     140#define ST_RTAR                 0x20    /* Real-time Alarm Register */
     141#define ST_CRTR                 0x24    /* Current Real-time Register */
     142
     143/* Bit Defines */
     144/* ST_CR - Control Register */
     145#define ST_CR_WDRST                     BIT0    /* write 1 to reload WD counter  */
     146
     147/* ST_PIMR - Period Interval Mode Register */
    148148#define ST_PIMR_PIV_MASK        0x0000ffff
    149149
    150 // ST_WDMR - Watchdog Mode Register
    151 #define ST_WDMR_EXTEN           BIT17   // WDOVF is not implemented on AT91RM9200
    152 #define ST_WDMR_RSTEN           BIT16   // 1 = reset the AT91RM9200 when WD overflows
    153 #define ST_WDMR_WDV_MASK        0x0000ffff      // WD counter is in the lower 16-bits
    154 
    155 // ST_RTMR - Real-time Mode Register
    156 #define ST_RTMR_RTPRES_MASK     0x0000ffff      // Real-Time Prescaler
    157 
    158 // ST_SR - Status Register - Read Only
    159 // ST_IER - Interrupt Enable Register - Write Only
    160 // ST_IDR - Interrupt Disable Register - Write Only
    161 // ST_IMR - Interrupt Mask Register - Read Only
     150/* ST_WDMR - Watchdog Mode Register */
     151#define ST_WDMR_EXTEN           BIT17   /* WDOVF is not implemented on AT91RM9200 */
     152#define ST_WDMR_RSTEN           BIT16   /* 1 = reset the AT91RM9200 when WD overflows */
     153#define ST_WDMR_WDV_MASK        0x0000ffff      /* WD counter is in the lower 16-bits */
     154
     155/* ST_RTMR - Real-time Mode Register */
     156#define ST_RTMR_RTPRES_MASK     0x0000ffff      /* Real-Time Prescaler */
     157
     158/* ST_SR - Status Register - Read Only */
     159/* ST_IER - Interrupt Enable Register - Write Only */
     160/* ST_IDR - Interrupt Disable Register - Write Only */
     161/* ST_IMR - Interrupt Mask Register - Read Only */
    162162#define ST_SR_ALMS                      BIT3
    163163#define ST_SR_RTTINC            BIT2
     
    165165#define ST_SR_PITS                      BIT0
    166166
    167 // ST_RTAR - Real-time Alarm Register
     167/* ST_RTAR - Real-time Alarm Register */
    168168#define ST_RTAR_ALMV_MASK       0x000fffff
    169169
    170 // ST_CRTR - Current Real-time Register
     170/* ST_CRTR - Current Real-time Register */
    171171#define ST_CRTR_CRTV_MASK       0x000fffff
    172172
     
    180180 * peripheral but with these register offsets
    181181 **************************************************************************/
    182 // Register Offsets
    183 #define PDC_RPR         0x100   // Receive Pointer Register
    184 #define PDC_RCR         0x104   // Receive Counter Register
    185 #define PDC_TPR         0x108   // Transmit Pointer Register
    186 #define PDC_TCR         0x10c   // Transmit Counter Register
    187 #define PDC_RNPR        0x110   // Receive Next Pointer Register
    188 #define PDC_RNCR        0x114   // Receive Next Counter Register
    189 #define PDC_TNPR        0x118   // Transmit Next Pointer Register
    190 #define PDC_TNCR        0x11c   // Transmit Next Counter Register
    191 #define PDC_PTCR        0x120   // PDC Transfer Control Register
    192 #define PDC_PTSR        0x124   // PDC Transfer Status Register
     182/* Register Offsets */
     183#define PDC_RPR         0x100   /* Receive Pointer Register */
     184#define PDC_RCR         0x104   /* Receive Counter Register */
     185#define PDC_TPR         0x108   /* Transmit Pointer Register */
     186#define PDC_TCR         0x10c   /* Transmit Counter Register */
     187#define PDC_RNPR        0x110   /* Receive Next Pointer Register */
     188#define PDC_RNCR        0x114   /* Receive Next Counter Register */
     189#define PDC_TNPR        0x118   /* Transmit Next Pointer Register */
     190#define PDC_TNCR        0x11c   /* Transmit Next Counter Register */
     191#define PDC_PTCR        0x120   /* PDC Transfer Control Register */
     192#define PDC_PTSR        0x124   /* PDC Transfer Status Register */
    193193
    194194/**************************************************************************
     
    197197 * same register set, but different base addresses
    198198 **************************************************************************/
    199 // Port A
     199/* Port A */
    200200#define PIOA_BASE               0xFFFFF400
    201201#define PIOA_REG(_x_)   *(vulong *)(PIOA_BASE + _x_)
    202202
    203 // Port B
     203/* Port B */
    204204#define PIOB_BASE               0xFFFFF600
    205205#define PIOB_REG(_x_)   *(vulong *)(PIOB_BASE + _x_)
    206206
    207 // Port C
     207/* Port C */
    208208#define PIOC_BASE               0xFFFFF800
    209209#define PIOC_REG(_x_)   *(vulong *)(PIOC_BASE + _x_)
    210210
    211 // Port D
     211/* Port D */
    212212#define PIOD_BASE               0xFFFFFA00
    213213#define PIOD_REG(_x_)   *(vulong *)(PIOD_BASE + _x_)
     
    234234#define TC_TC2_REG(_x_) *(vulong *)(TC_BASE + 0x80 + _x_)
    235235
    236 // Offsets from TC_TC?_REG
    237 #define TC_CCR      0x00    // Channel Control Register
    238 #define TC_CMR      0x04    // Channel Mode Register
    239 #define TC_CV       0x10    // Counter Value
    240 #define TC_RA       0x14    // Register A
    241 #define TC_RB       0x18    // Register B
    242 #define TC_RC       0x1C    // Register C
    243 #define TC_SR       0x20    // Status Register
    244 #define TC_IER      0x24    // Interrupt Enable Register
    245 #define TC_IDR      0x28    // Interrupt Disable Register
    246 #define TC_IMR      0x2C    // Interrupt Mask Register
    247 
    248 // Offsets from TC_BASE
    249 #define TC_BCR      0xc0    // Channel Control Register
    250 #define TC_BMR      0xc4    // Channel Control Register
    251 
    252 // Block control register
    253 #define TC_BCR_SYNC    BIT1       // Set to syncronize channels
    254 
    255 // Block mode register
    256 #define TC_BMR_TC0(_x_)    ((_x_ & 0x3) << 0)   // TC0 clock source
    257 #define TC_BMR_TC1(_x_)    ((_x_ & 0x3) << 2)   // TC1 clock source
    258 #define TC_BMR_TC2(_x_)    ((_x_ & 0x3) << 4)   // TC2 clock source
    259 
    260 // Channel Control register
    261 #define TC_CCR_CLKEN     BIT0       // Enable clock
    262 #define TC_CCR_CLKDIS    BIT1       // Disable clock
    263 #define TC_CCR_SWTRG     BIT2       // Software trigger command
    264 
    265 // Channel mode register
    266 #define TC_CMR_TCCLKS(_x_)   ((_x_ & 0x7) << 0)  // Clock source
    267 #define TC_CMR_CLKI          BIT3                // Clock invert
    268 #define TC_BURST(_x_)        ((_x_ & 0x3 << 4)   // Burst signal selection
    269 #define TC_WAVE              BIT15               // 0 for catpure, 1 for wave
    270 
    271 // Channel mode register - capture mode (TC_WAVE = 0)
    272 #define TC_CMR_LDBSTOP       BIT6                // Set to stop clock when RB loads
    273 #define TC_CMR_LDBDIS        BIT7                // Set to disable clock when RB loads
    274 #define TC_CMR_ETRGEDG(_x_)  ((_x_ & 0x3) << 8)  // Select edge triggering mode
    275 #define TC_CMR_ABETRG        BIT10               // Select ext trigger source
    276 #define TC_CMR_CPCTRG        BIT14               // RC Compare trigger enable
    277 #define TC_CMR_LDRA(_x_)     ((_x_ & 0x3) << 16) // RA loading selection
    278 #define TC_CMR_LDRB(_x_)     ((_x_ & 0x3) << 18) // RB loading selection
    279 
    280 // Channel mode register - wave mode (TC_WAVE = 1)
    281 #define TC_CMR_CPCSTOP       BIT6                 // Clock stopped w/ RC compare
    282 #define TC_CMR_CPCDIS        BIT7                 // Clock disabled w/ RC compare
    283 #define TC_CMR_EEVTEDG(_x_)  ((_x_ & 0x3) << 8)   // Ext event edge selection
    284 #define TC_CMR_EEVT(_x_)     ((_x_ & 0x3) << 10)  // Ext event selection
    285 #define TC_CMR_ENETRG        BIT12                // Ext event trigger enable
    286 #define TC_CMR_WAVESEL(_x_)  ((_x_ & 0x3) << 13)  // Waveform selection
    287 #define TC_CMR_ACPA(_x_)     ((_x_ & 0x3) << 16)  // RA compare effect on TIOA
    288 #define TC_CMR_ACPC(_x_)     ((_x_ & 0x3) << 18)  // RC compare effect on TIOA
    289 #define TC_CMR_AEEVT(_x_)    ((_x_ & 0x3) << 20)  // Ext event effect on TIOA
    290 #define TC_CMR_ASWTRG(_x_)   ((_x_ & 0x3) << 22)  // SW trigger effect on TIOA
    291 #define TC_CMR_BCPB(_x_)     ((_x_ & 0x3) << 24)  // RB compare effect on TIOB
    292 #define TC_CMR_BCPC(_x_)     ((_x_ & 0x3) << 26)  // RC compare effect on TIOB
    293 #define TC_CMR_BEEVT(_x_)    ((_x_ & 0x3) << 28)  // Ext event effect on TIOB
    294 #define TC_CMR_BSWTRG(_x_)   ((_x_ & 0x3) << 30)  // SW trigger effect on TIOB
    295 
    296 // Counter value
    297 #define TC_CV_MASK            0xffff              // Timer counter mask
    298 
    299 // Status, Interrupt enable, Interrupt disable, and Interrupt mask registers
    300 #define TC_SR_COVFS     BIT0        // Counter overflow status
    301 #define TC_SR_LOVRS     BIT1        // Load overrun status
    302 #define TC_SR_CPAS      BIT2        // RA compare status
    303 #define TC_SR_CPBS      BIT3        // RB compare status
    304 #define TC_SR_CPCS      BIT4        // RC compare status
    305 #define TC_SR_LDRAS     BIT5        // RA loading status
    306 #define TC_SR_LDRBS     BIT6        // RB loading  status
    307 #define TC_SR_ETRGS     BIT7        // External trigger status
    308 #define TC_SR_CLKSTA    BIT16       // Clock enabling status
    309 #define TC_SR_MTIOA     BIT17       // TIOA Mirror
    310 #define TC_SR_MTIOB     BIT18       // TIOB Mirror
    311 
    312 
    313 
     236/* Offsets from TC_TC?_REG  */
     237#define TC_CCR      0x00    /* Channel Control Register  */
     238#define TC_CMR      0x04    /* Channel Mode Register  */
     239#define TC_CV       0x10    /* Counter Value  */
     240#define TC_RA       0x14    /* Register A  */
     241#define TC_RB       0x18    /* Register B  */
     242#define TC_RC       0x1C    /* Register C  */
     243#define TC_SR       0x20    /* Status Register  */
     244#define TC_IER      0x24    /* Interrupt Enable Register  */
     245#define TC_IDR      0x28    /* Interrupt Disable Register  */
     246#define TC_IMR      0x2C    /* Interrupt Mask Register  */
     247
     248/* Offsets from TC_BASE */
     249#define TC_BCR      0xc0    /* Channel Control Register  */
     250#define TC_BMR      0xc4    /* Channel Control Register  */
     251
     252/* Block control register */
     253#define TC_BCR_SYNC    BIT1       /* Set to syncronize channels */
     254
     255/* Block mode register */
     256#define TC_BMR_TC0(_x_)    ((_x_ & 0x3) << 0)   /* TC0 clock source */
     257#define TC_BMR_TC1(_x_)    ((_x_ & 0x3) << 2)   /* TC1 clock source */
     258#define TC_BMR_TC2(_x_)    ((_x_ & 0x3) << 4)   /* TC2 clock source */
     259
     260/* Channel Control register */
     261#define TC_CCR_CLKEN     BIT0       /* Enable clock */
     262#define TC_CCR_CLKDIS    BIT1       /* Disable clock */
     263#define TC_CCR_SWTRG     BIT2       /* Software trigger command */
     264
     265/* Channel mode register */
     266#define TC_CMR_TCCLKS(_x_)   ((_x_ & 0x7) << 0)  /* Clock source */
     267#define TC_CMR_CLKI          BIT3                /* Clock invert */
     268#define TC_BURST(_x_)        ((_x_ & 0x3 << 4)   /* Burst signal selection */
     269#define TC_WAVE              BIT15               /* 0 for catpure, 1 for wave */
     270
     271/* Channel mode register - capture mode (TC_WAVE = 0) */
     272#define TC_CMR_LDBSTOP       BIT6                /* Set to stop clock when RB loads */
     273#define TC_CMR_LDBDIS        BIT7                /* Set to disable clock when RB loads */
     274#define TC_CMR_ETRGEDG(_x_)  ((_x_ & 0x3) << 8)  /* Select edge triggering mode */
     275#define TC_CMR_ABETRG        BIT10               /* Select ext trigger source */
     276#define TC_CMR_CPCTRG        BIT14               /* RC Compare trigger enable */
     277#define TC_CMR_LDRA(_x_)     ((_x_ & 0x3) << 16) /* RA loading selection */
     278#define TC_CMR_LDRB(_x_)     ((_x_ & 0x3) << 18) /* RB loading selection */
     279
     280/* Channel mode register - wave mode (TC_WAVE = 1) */
     281#define TC_CMR_CPCSTOP       BIT6                 /* Clock stopped w/ RC compare */
     282#define TC_CMR_CPCDIS        BIT7                 /* Clock disabled w/ RC compare */
     283#define TC_CMR_EEVTEDG(_x_)  ((_x_ & 0x3) << 8)   /* Ext event edge selection */
     284#define TC_CMR_EEVT(_x_)     ((_x_ & 0x3) << 10)  /* Ext event selection */
     285#define TC_CMR_ENETRG        BIT12                /* Ext event trigger enable */
     286#define TC_CMR_WAVESEL(_x_)  ((_x_ & 0x3) << 13)  /* Waveform selection */
     287#define TC_CMR_ACPA(_x_)     ((_x_ & 0x3) << 16)  /* RA compare effect on TIOA */
     288#define TC_CMR_ACPC(_x_)     ((_x_ & 0x3) << 18)  /* RC compare effect on TIOA */
     289#define TC_CMR_AEEVT(_x_)    ((_x_ & 0x3) << 20)  /* Ext event effect on TIOA */
     290#define TC_CMR_ASWTRG(_x_)   ((_x_ & 0x3) << 22)  /* SW trigger effect on TIOA */
     291#define TC_CMR_BCPB(_x_)     ((_x_ & 0x3) << 24)  /* RB compare effect on TIOB */
     292#define TC_CMR_BCPC(_x_)     ((_x_ & 0x3) << 26)  /* RC compare effect on TIOB */
     293#define TC_CMR_BEEVT(_x_)    ((_x_ & 0x3) << 28)  /* Ext event effect on TIOB */
     294#define TC_CMR_BSWTRG(_x_)   ((_x_ & 0x3) << 30)  /* SW trigger effect on TIOB */
     295
     296/* Counter value */
     297#define TC_CV_MASK            0xffff              /* Timer counter mask */
     298
     299/* Status, Interrupt enable, Interrupt disable, and Interrupt mask registers */
     300#define TC_SR_COVFS     BIT0        /* Counter overflow status */
     301#define TC_SR_LOVRS     BIT1        /* Load overrun status */
     302#define TC_SR_CPAS      BIT2        /* RA compare status */
     303#define TC_SR_CPBS      BIT3        /* RB compare status */
     304#define TC_SR_CPCS      BIT4        /* RC compare status */
     305#define TC_SR_LDRAS     BIT5        /* RA loading status */
     306#define TC_SR_LDRBS     BIT6        /* RB loading  status */
     307#define TC_SR_ETRGS     BIT7        /* External trigger status */
     308#define TC_SR_CLKSTA    BIT16       /* Clock enabling status */
     309#define TC_SR_MTIOA     BIT17       /* TIOA Mirror */
     310#define TC_SR_MTIOB     BIT18       /* TIOB Mirror */
    314311
    315312/***************************************************************************
  • c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_dbgu.h

    rea1d598 r5e14d89  
    1717#include "bits.h"
    1818
    19 // Register Offsets
    20 #define DBGU_CR         0x00            // Control Register
    21 #define DBGU_MR         0x04            // Mode Register
    22 #define DBGU_IER        0x08            // Interrupt Enable Register
    23 #define DBGU_IDR        0x0C            // Interrupt Disable Register
    24 #define DBGU_IMR        0x10            // Interrupt Mask Register
    25 #define DBGU_SR         0x14            // Channel Status Register
    26 #define DBGU_RHR        0x18            // Receiver Holding Register
    27 #define DBGU_THR        0x1C            // Transmitter Holding Register
    28 #define DBGU_BRGR       0x20            // Baud Rate Generator Register
    29 #define DBGU_C1R        0x40            // Chip ID1 Register
    30 #define DBGU_C2R        0x44            // Chip ID2 Register
    31 #define DBGU_FNTR       0x48            // Force NTRST Register
     19/* Register Offsets */
     20#define DBGU_CR         0x00            /* Control Register */
     21#define DBGU_MR         0x04            /* Mode Register */
     22#define DBGU_IER        0x08            /* Interrupt Enable Register */
     23#define DBGU_IDR        0x0C            /* Interrupt Disable Register */
     24#define DBGU_IMR        0x10            /* Interrupt Mask Register */
     25#define DBGU_SR         0x14            /* Channel Status Register */
     26#define DBGU_RHR        0x18            /* Receiver Holding Register */
     27#define DBGU_THR        0x1C            /* Transmitter Holding Register */
     28#define DBGU_BRGR       0x20            /* Baud Rate Generator Register */
     29#define DBGU_C1R        0x40            /* Chip ID1 Register */
     30#define DBGU_C2R        0x44            /* Chip ID2 Register */
     31#define DBGU_FNTR       0x48            /* Force NTRST Register */
    3232
    33 // Bit Defines
    34 // Control Register, DBGU_CR, Offset 0x00
    35 #define DBGU_CR_RSTRX   BIT2            // 1 = Reset and disable receiver
    36 #define DBGU_CR_RSTTX   BIT3            // 1 = Reset and disable transmitter
    37 #define DBGU_CR_RXEN    BIT4            // 1 = Receiver enable
    38 #define DBGU_CR_RXDIS   BIT5            // 1 = Receiver disable
    39 #define DBGU_CR_TXEN    BIT6            // 1 = Transmitter enable
    40 #define DBGU_CR_TXDIS   BIT7            // 1 = Transmitter disable
    41 #define DBGU_CR_RSTSTA  BIT8            // 1 = Reset PARE, FRAME and OVRE in DBGU_SR.
     33/* Bit Defines */
     34/* Control Register, DBGU_CR, Offset 0x00 */
     35#define DBGU_CR_RSTRX   BIT2            /* 1 = Reset and disable receiver */
     36#define DBGU_CR_RSTTX   BIT3            /* 1 = Reset and disable transmitter */
     37#define DBGU_CR_RXEN    BIT4            /* 1 = Receiver enable */
     38#define DBGU_CR_RXDIS   BIT5            /* 1 = Receiver disable */
     39#define DBGU_CR_TXEN    BIT6            /* 1 = Transmitter enable */
     40#define DBGU_CR_TXDIS   BIT7            /* 1 = Transmitter disable */
     41#define DBGU_CR_RSTSTA  BIT8            /* 1 = Reset PARE, FRAME and OVRE in DBGU_SR. */
    4242
    43 // Mode Register. DBGU_MR. Offset 0x04
    44 #define DBGU_MR_PAR_EVEN    (0x0 <<  9) // Even Parity
    45 #define DBGU_MR_PAR_ODD     (0x1 <<  9) // Odd Parity
    46 #define DBGU_MR_PAR_SPACE   (0x2 <<  9) // Parity forced to 0 (Space)
    47 #define DBGU_MR_PAR_MARK    (0x3 <<  9) // Parity forced to 1 (Mark)
    48 #define DBGU_MR_PAR_NONE    (0x4 <<  9) // No Parity
    49 #define DBGU_MR_PAR_MDROP   (0x6 <<  9) // Multi-drop mode
    50 #define DBGU_MR_CHMODE_NORM (0x0 << 14) // Normal Mode
    51 #define DBGU_MR_CHMODE_AUTO (0x1 << 14) // Auto Echo: RXD drives TXD
    52 #define DBGU_MR_CHMODE_LOC  (0x2 << 14) // Local Loopback: TXD drives RXD
    53 #define DBGU_MR_CHMODE_REM  (0x3 << 14) // Remote Loopback: RXD pin connected to TXD pin.
     43/* Mode Register. DBGU_MR. Offset 0x04 */
     44#define DBGU_MR_PAR_EVEN    (0x0 <<  9) /* Even Parity */
     45#define DBGU_MR_PAR_ODD     (0x1 <<  9) /* Odd Parity */
     46#define DBGU_MR_PAR_SPACE   (0x2 <<  9) /* Parity forced to 0 (Space) */
     47#define DBGU_MR_PAR_MARK    (0x3 <<  9) /* Parity forced to 1 (Mark) */
     48#define DBGU_MR_PAR_NONE    (0x4 <<  9) /* No Parity */
     49#define DBGU_MR_PAR_MDROP   (0x6 <<  9) /* Multi-drop mode */
     50#define DBGU_MR_CHMODE_NORM (0x0 << 14) /* Normal Mode */
     51#define DBGU_MR_CHMODE_AUTO (0x1 << 14) /* Auto Echo: RXD drives TXD */
     52#define DBGU_MR_CHMODE_LOC  (0x2 << 14) /* Local Loopback: TXD drives RXD */
     53#define DBGU_MR_CHMODE_REM  (0x3 << 14) /* Remote Loopback: RXD pin connected to TXD pin. */
    5454
    55 // Interrupt Enable Register, DBGU_IER, Offset 0x08
    56 // Interrupt Disable Register, DBGU_IDR, Offset 0x0C
    57 // Interrupt Mask Register, DBGU_IMR, Offset 0x10
    58 // Channel Status Register, DBGU_SR, Offset 0x14
    59 #define DBGU_INT_RXRDY      BIT0        // RXRDY Interrupt
    60 #define DBGU_INT_TXRDY      BIT1        // TXRDY Interrupt
    61 #define DBGU_INT_ENDRX      BIT3        // End of Receive Transfer Interrupt
    62 #define DBGU_INT_ENDTX      BIT4        // End of Transmit Interrupt
    63 #define DBGU_INT_OVRE       BIT5        // Overrun Interrupt
    64 #define DBGU_INT_FRAME      BIT6        // Framing Error Interrupt
    65 #define DBGU_INT_PARE       BIT7        // Parity Error Interrupt
    66 #define DBGU_INT_TXEMPTY    BIT9        // TXEMPTY Interrupt
    67 #define DBGU_INT_TXBUFE     BIT11       // TXBUFE Interrupt
    68 #define DBGU_INT_RXBUFF     BIT12       // RXBUFF Interrupt
    69 #define DBGU_INT_COMM_TX    BIT30       // COMM_TX Interrupt
    70 #define DBGU_INT_COMM_RX    BIT31       // COMM_RX Interrupt
    71 #define DBGU_INT_ALL        0xC0001AFB  // all assigned bits
     55/* Interrupt Enable Register, DBGU_IER, Offset 0x08 */
     56/* Interrupt Disable Register, DBGU_IDR, Offset 0x0C */
     57/* Interrupt Mask Register, DBGU_IMR, Offset 0x10 */
     58/* Channel Status Register, DBGU_SR, Offset 0x14 */
     59#define DBGU_INT_RXRDY      BIT0        /* RXRDY Interrupt */
     60#define DBGU_INT_TXRDY      BIT1        /* TXRDY Interrupt */
     61#define DBGU_INT_ENDRX      BIT3        /* End of Receive Transfer Interrupt */
     62/*efine DBGU_INT_ENDTX      BIT4        /* End of Transmit Interrupt */
     63#define DBGU_INT_OVRE       BIT5        /* Overrun Interrupt */
     64#define DBGU_INT_FRAME      BIT6        /* Framing Error Interrupt */
     65#define DBGU_INT_PARE       BIT7        /* Parity Error Interrupt */
     66#define DBGU_INT_TXEMPTY    BIT9        /* TXEMPTY Interrupt */
     67#define DBGU_INT_TXBUFE     BIT11       /* TXBUFE Interrupt */
     68#define DBGU_INT_RXBUFF     BIT12       /* RXBUFF Interrupt */
     69#define DBGU_INT_COMM_TX    BIT30       /* COMM_TX Interrupt */
     70#define DBGU_INT_COMM_RX    BIT31       /* COMM_RX Interrupt */
     71#define DBGU_INT_ALL        0xC0001AFB  /* all assigned bits */
    7272
    73 // FORCE_NTRST Register, DBGU_FNTR, Offset 0x48
    74 #define DBGU_FNTR_NTRST         BIT0    // 1 = Force NTRST low in JTAG
     73/* FORCE_NTRST Register, DBGU_FNTR, Offset 0x48 */
     74#define DBGU_FNTR_NTRST         BIT0    /* 1 = Force NTRST low in JTAG */
    7575
    7676typedef struct {
  • c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_emac.h

    rea1d598 r5e14d89  
    1717#include <bits.h>
    1818
    19 //Register offsets
    20 #define EMAC_CTL        0x00            // Network Control Register
    21 #define EMAC_CFG        0x04            // Network Configuration Register
    22 #define EMAC_SR         0x08            // Network Status Register
    23 #define EMAC_TAR        0x0C            // Transmit Address Register
    24 #define EMAC_TCR        0x10            // Transmit Control Register
    25 #define EMAC_TSR        0x14            // Transmit Status Register
    26 #define EMAC_RBQP       0x18            // Receive Buffer Queue Pointer
    27 #define EMAC_RSR        0x20            // Receive Status Register
    28 #define EMAC_ISR        0x24            // Interrupt Enable Register
    29 #define EMAC_IER        0x28            // Interrupt Enable Register
    30 #define EMAC_IDR        0x2C            // Interrupt Disable Register
    31 #define EMAC_IMR        0x30            // Interrupt Mask Register
    32 #define EMAC_MAN        0x34            // PHY Maintenance Register
    33 #define EMAC_FRA        0x40            // Frames Transmitted OK Register
    34 #define EMAC_SCOL       0x44            // Single Collision Frame Register
    35 #define EMAC_MCOL       0x48            // Multiple Collision Frame Register
    36 #define EMAC_OK         0x4C            // Frames Received OK Register
    37 #define EMAC_SEQE       0x50            // Frame Check Sequence Error Register
    38 #define EMAC_ALE        0x54            // Alignment Error Register
    39 #define EMAC_DTE        0x58            // Deferred Transmission Frame Register
    40 #define EMAC_LCOL       0x5C            // Late Collision Register
    41 #define EMAC_ECOL       0x60            // Excessive Collision Register
    42 #define EMAC_CSE        0x64            // Carrier Sense Error Register
    43 #define EMAC_TUE        0x68            // Transmit Underrun Error Register
    44 #define EMAC_CDE        0x6C            // Code Error Register
    45 #define EMAC_ELR        0x70            // Excessive Length Error Register
    46 #define EMAC_RJB        0x74            // Receive Jabber Register
    47 #define EMAC_USF        0x78            // Undersize Frame Register
    48 #define EMAC_SQEE       0x7C            // SQE Test Error Register
    49 #define EMAC_DRFC       0x80            // Discarded RX Frame Register
    50 #define EMAC_HSH        0x90            // Hash Address High[63:32]
    51 #define EMAC_HSL        0x94            // Hash Address Low[31:0]
    52 #define EMAC_SA1L       0x98            // Specific Addr 1 Low, First 4 bytes
    53 #define EMAC_SA1H       0x9C            // Specific Addr 1 High, Last 2 bytes
    54 #define EMAC_SA2L       0xA0            // Specific Addr 2 Low, First 4 bytes
    55 #define EMAC_SA2H       0xA4            // Specific Addr 2 High, Last 2 bytes
    56 #define EMAC_SA3L       0xA8            // Specific Addr 3 Low, First 4 bytes
    57 #define EMAC_SA3H       0xAC            // Specific Addr 3 High, Last 2 bytes
    58 #define EMAC_SA4L       0xB0            // Specific Addr 4 Low, First 4 bytes
    59 #define EMAC_SA4H       0xB4            // Specific Addr 4 High, Last 2 bytesr
     19/*Register offsets */
     20#define EMAC_CTL        0x00          /* Network Control Register */
     21#define EMAC_CFG        0x04          /* Network Configuration Register */
     22#define EMAC_SR         0x08          /* Network Status Register */
     23#define EMAC_TAR        0x0C          /* Transmit Address Register */
     24#define EMAC_TCR        0x10          /* Transmit Control Register */
     25#define EMAC_TSR        0x14          /* Transmit Status Register */
     26#define EMAC_RBQP       0x18          /* Receive Buffer Queue Pointer */
     27#define EMAC_RSR        0x20          /* Receive Status Register */
     28#define EMAC_ISR        0x24          /* Interrupt Enable Register */
     29#define EMAC_IER        0x28          /* Interrupt Enable Register */
     30#define EMAC_IDR        0x2C          /* Interrupt Disable Register */
     31#define EMAC_IMR        0x30          /* Interrupt Mask Register */
     32#define EMAC_MAN        0x34          /* PHY Maintenance Register */
     33#define EMAC_FRA        0x40          /* Frames Transmitted OK Register */
     34#define EMAC_SCOL       0x44          /* Single Collision Frame Register */
     35#define EMAC_MCOL       0x48          /* Multiple Collision Frame Register */
     36#define EMAC_OK         0x4C          /* Frames Received OK Register */
     37#define EMAC_SEQE       0x50          /* Frame Check Sequence Error Register */
     38#define EMAC_ALE        0x54          /* Alignment Error Register */
     39#define EMAC_DTE        0x58          /* Deferred Transmission Frame Register */
     40#define EMAC_LCOL       0x5C          /* Late Collision Register */
     41#define EMAC_ECOL       0x60          /* Excessive Collision Register */
     42#define EMAC_CSE        0x64          /* Carrier Sense Error Register */
     43#define EMAC_TUE        0x68          /* Transmit Underrun Error Register */
     44#define EMAC_CDE        0x6C          /* Code Error Register */
     45#define EMAC_ELR        0x70          /* Excessive Length Error Register */
     46#define EMAC_RJB        0x74          /* Receive Jabber Register */
     47#define EMAC_USF        0x78          /* Undersize Frame Register */
     48#define EMAC_SQEE       0x7C          /* SQE Test Error Register */
     49#define EMAC_DRFC       0x80          /* Discarded RX Frame Register */
     50#define EMAC_HSH        0x90          /* Hash Address High[63:32] */
     51#define EMAC_HSL        0x94          /* Hash Address Low[31:0] */
     52#define EMAC_SA1L       0x98          /* Specific Addr 1 Low, First 4 bytes */
     53#define EMAC_SA1H       0x9C          /* Specific Addr 1 High, Last 2 bytes */
     54#define EMAC_SA2L       0xA0          /* Specific Addr 2 Low, First 4 bytes */
     55#define EMAC_SA2H       0xA4          /* Specific Addr 2 High, Last 2 bytes */
     56#define EMAC_SA3L       0xA8          /* Specific Addr 3 Low, First 4 bytes */
     57#define EMAC_SA3H       0xAC          /* Specific Addr 3 High, Last 2 bytes */
     58#define EMAC_SA4L       0xB0          /* Specific Addr 4 Low, First 4 bytes */
     59#define EMAC_SA4H       0xB4          /* Specific Addr 4 High, Last 2 bytesr */
    6060
    61 // Control Register, EMAC_CTL, Offset 0x0
    62 #define EMAC_CTL_LB     BIT0            // 1 = Set Loopback output signal
    63 #define EMAC_CTL_LBL    BIT1            // 1 = Loopback local.
    64 #define EMAC_CTL_RE     BIT2            // 1 = Receive enable.
    65 #define EMAC_CTL_TE     BIT3            // 1 = Transmit enable.
    66 #define EMAC_CTL_MPE    BIT4            // 1 = Management port enable.
    67 #define EMAC_CTL_CSR    BIT5            // Write 1 to clear stats registers.
    68 #define EMAC_CTL_ISR    BIT6            // Write to increment stats registers
    69 #define EMAC_CTL_WES    BIT7            // 1 = Enable writing to stats regs
    70 #define EMAC_CTL_BP     BIT8            // 1 = Force collision on all RX frames
     61/* Control Register, EMAC_CTL, Offset 0x0 */
     62#define EMAC_CTL_LB     BIT0          /* 1 = Set Loopback output signal */
     63#define EMAC_CTL_LBL    BIT1          /* 1 = Loopback local.  */
     64#define EMAC_CTL_RE     BIT2          /* 1 = Receive enable.  */
     65#define EMAC_CTL_TE     BIT3          /* 1 = Transmit enable.  */
     66#define EMAC_CTL_MPE    BIT4          /* 1 = Management port enable.  */
     67#define EMAC_CTL_CSR    BIT5          /* Write 1 to clear stats registers.  */
     68#define EMAC_CTL_ISR    BIT6          /* Write to increment stats registers */
     69#define EMAC_CTL_WES    BIT7          /* 1 = Enable writing to stats regs */
     70#define EMAC_CTL_BP     BIT8          /* 1 = Force collision on all RX frames */
    7171
    72 // Configuration Register, EMAC_CFG, Offset 0x4
    73 #define EMAC_CFG_SPD    BIT0            // 1 = 10/100 Speed (not functional?)
    74 #define EMAC_CFG_FD     BIT1            // 1 = Full duplex.
    75 #define EMAC_CFG_BR     BIT2            // write 0
    76 #define EMAC_CFG_CAF    BIT4            // 1 = accept all frames
    77 #define EMAC_CFG_NBC    BIT5            // 1 = disable reception of bcast frms
    78 #define EMAC_CFG_MTI    BIT6            // 1 = Multicast hash enable
    79 #define EMAC_CFG_UNI    BIT7            // 1 = Unicast hash enable.
    80 #define EMAC_CFG_BIG    BIT8            // 1 = enable reception 1522 byte frms
    81 #define EMAC_CFG_EAE    BIT9            // write 0
    82 #define EMAC_CFG_CLK_8  (0 << 10)       // MII Clock = HCLK divided by 8
    83 #define EMAC_CFG_CLK_16 (1 << 10)       // MII Clock = HCLK divided by 16
    84 #define EMAC_CFG_CLK_32 (2 << 10)       // MII Clock = HCLK divided by 32
    85 #define EMAC_CFG_CLK_64 (3 << 10)       // MII Clock = HCLK divided by 64
    86 #define EMAC_CFG_CLK_MASK (3 << 10)       // MII Clock mask
    87 #define EMAC_CFG_RTY    BIT12           // Retry Test Mode - Must be 0
    88 #define EMAC_CFG_RMII   BIT13           // Reduced MII Mode Enable
     72/* Configuration Register, EMAC_CFG, Offset 0x4 */
     73#define EMAC_CFG_SPD    BIT0          /* 1 = 10/100 Speed (not functional?) */
     74#define EMAC_CFG_FD     BIT1          /* 1 = Full duplex.  */
     75#define EMAC_CFG_BR     BIT2          /* write 0  */
     76#define EMAC_CFG_CAF    BIT4          /* 1 = accept all frames */
     77#define EMAC_CFG_NBC    BIT5          /* 1 = disable reception of bcast frms */
     78#define EMAC_CFG_MTI    BIT6          /* 1 = Multicast hash enable */
     79#define EMAC_CFG_UNI    BIT7          /* 1 = Unicast hash enable.  */
     80#define EMAC_CFG_BIG    BIT8          /* 1 = enable reception 1522 byte frms */
     81#define EMAC_CFG_EAE    BIT9          /* write 0 */
     82#define EMAC_CFG_CLK_8  (0 << 10)     /* MII Clock = HCLK divided by 8 */
     83#define EMAC_CFG_CLK_16 (1 << 10)     /* MII Clock = HCLK divided by 16 */
     84#define EMAC_CFG_CLK_32 (2 << 10)     /* MII Clock = HCLK divided by 32 */
     85#define EMAC_CFG_CLK_64 (3 << 10)     /* MII Clock = HCLK divided by 64 */
     86#define EMAC_CFG_CLK_MASK (3 << 10)   /* MII Clock mask */
     87#define EMAC_CFG_RTY    BIT12         /* Retry Test Mode - Must be 0  */
     88#define EMAC_CFG_RMII   BIT13         /* Reduced MII Mode Enable */
    8989
    90 // Status Register, EMAC_SR, Offset 0x8
    91 #define EMAC_LINK       BIT0            // Link pin
    92 #define EMAC_MDIO       BIT1            // Real Time state of MDIO pin
    93 #define EMAC_IDLE       BIT2            // 0 = PHY Logic is idle
     90/* Status Register, EMAC_SR, Offset 0x8 */
     91#define EMAC_LINK       BIT0          /* Link pin  */
     92#define EMAC_MDIO       BIT1          /* Real Time state of MDIO pin */
     93#define EMAC_IDLE       BIT2          /* 0 = PHY Logic is idle */
    9494
    95 // Transmit Control Register, EMAC_TCR, Offset 0x10
    96 #define EMAC_TCR_LEN(_x_)  ((_x_ & 0x7FF) <<  0)   // Tx frame len minus CRC
    97 #define EMAC_TCR_NCRC   BIT15                      // Do'nt append CRC on Tx
     95/* Transmit Control Register, EMAC_TCR, Offset 0x10 */
     96#define EMAC_TCR_LEN(_x_)  ((_x_ & 0x7FF) <<  0) /* Tx frame len minus CRC */
     97#define EMAC_TCR_NCRC   BIT15                    /* Do'nt append CRC on Tx */
    9898
    99 // Transmit Status Register, EMAC_TSR, Offset 0x14
    100 #define EMAC_TSR_OVR    BIT0            // 1 = Transmit buffer overrun
    101 #define EMAC_TSR_COL    BIT1            // 1 = Collision occured
    102 #define EMAC_TSR_RLE    BIT2            // 1 = Retry lmimt exceeded
    103 #define EMAC_TSR_TXIDLE BIT3            // 1 = Transmitter is idle
    104 #define EMAC_TSR_BNQ    BIT4            // 1 = Transmit buffer not queued
    105 #define EMAC_TSR_COMP   BIT5            // 1 = Transmit complete
    106 #define EMAC_TSR_UND    BIT6            // 1 = Transmit underrun
     99/* Transmit Status Register, EMAC_TSR, Offset 0x14 */
     100#define EMAC_TSR_OVR    BIT0          /* 1 = Transmit buffer overrun */
     101#define EMAC_TSR_COL    BIT1          /* 1 = Collision occured */
     102#define EMAC_TSR_RLE    BIT2          /* 1 = Retry lmimt exceeded */
     103#define EMAC_TSR_TXIDLE BIT3          /* 1 = Transmitter is idle */
     104#define EMAC_TSR_BNQ    BIT4          /* 1 = Transmit buffer not queued */
     105#define EMAC_TSR_COMP   BIT5          /* 1 = Transmit complete */
     106#define EMAC_TSR_UND    BIT6          /* 1 = Transmit underrun */
    107107 
    108 // Receive Status Register, EMAC_RSR, Offset 0x20
    109 #define EMAC_RSR_BNA    BIT0            // 1 = Buffer not available
    110 #define EMAC_RSR_REC    BIT1            // 1 = Frame received
    111 #define EMAC_RSR_OVR    BIT2            // 1 = Receive overrun
     108/* Receive Status Register, EMAC_RSR, Offset 0x20 */
     109#define EMAC_RSR_BNA    BIT0          /* 1 = Buffer not available */
     110#define EMAC_RSR_REC    BIT1          /* 1 = Frame received */
     111#define EMAC_RSR_OVR    BIT2          /* 1 = Receive overrun */
    112112
    113 // Interrupt Status Register, EMAC_ISR, Offsen 0x24
    114 // Interrupt Enable Register, EMAC_IER, Offset 0x28
    115 // Interrupt Disable Register, EMAC_IDR, Offset 0x2c
    116 // Interrupt Mask Register, EMAC_IMR, Offset 0x30
    117 #define EMAC_INT_DONE   BIT0            // Phy management done
    118 #define EMAC_INT_RCOM   BIT1            // Receive complete
    119 #define EMAC_INT_RBNA   BIT2            // Receive buffer not available
    120 #define EMAC_INT_TOVR   BIT3            // Transmit buffer overrun
    121 #define EMAC_INT_TUND   BIT4            // Transmit buffer underrun
    122 #define EMAC_INT_RTRY   BIT5            // Transmit Retry limt
    123 #define EMAC_INT_TBRE   BIT6            // Transmit buffer register empty
    124 #define EMAC_INT_TCOM   BIT7            // Transmit complete
    125 #define EMAC_INT_TIDLE  BIT8            // Transmit idle
    126 #define EMAC_INT_LINK   BIT9            // Link pin changed value
    127 #define EMAC_INT_ROVR   BIT10           // Receive overrun
    128 #define EMAC_INT_ABT    BIT11           // Abort on DMA transfer
     113/*
     114 * Interrupt Status Register, EMAC_ISR, Offsen 0x24
     115 * Interrupt Enable Register, EMAC_IER, Offset 0x28
     116 * Interrupt Disable Register, EMAC_IDR, Offset 0x2c
     117 * Interrupt Mask Register, EMAC_IMR, Offset 0x30
     118 */
     119#define EMAC_INT_DONE   BIT0          /* Phy management done  */
     120#define EMAC_INT_RCOM   BIT1          /* Receive complete */
     121#define EMAC_INT_RBNA   BIT2          /* Receive buffer not available */
     122#define EMAC_INT_TOVR   BIT3          /* Transmit buffer overrun */
     123#define EMAC_INT_TUND   BIT4          /* Transmit buffer underrun */
     124#define EMAC_INT_RTRY   BIT5          /* Transmit Retry limt */
     125#define EMAC_INT_TBRE   BIT6          /* Transmit buffer register empty */
     126#define EMAC_INT_TCOM   BIT7          /* Transmit complete */
     127#define EMAC_INT_TIDLE  BIT8          /* Transmit idle */
     128#define EMAC_INT_LINK   BIT9          /* Link pin changed value */
     129#define EMAC_INT_ROVR   BIT10         /* Receive overrun */
     130#define EMAC_INT_ABT    BIT11         /* Abort on DMA transfer */
    129131
    130 // PHY Maintenance Register, EMAC_MAN, Offset 0x34
    131 #define EMAC_MAN_DATA(_x_)      ((_x_ & 0xFFFF) <<  0)  // PHY data register
    132 #define EMAC_MAN_CODE           (0x2 << 16)             // IEEE Code
    133 #define EMAC_MAN_REGA(_x_)      ((_x_ & 0x1F) << 18)    // PHY register address
    134 #define EMAC_MAN_PHYA(_x_)      ((_x_ & 0x1F) << 23)    // PHY address
    135 #define EMAC_MAN_WRITE          (0x1 << 28)             // Transfer is a write
    136 #define EMAC_MAN_READ           (0x2 << 28)             // Transfer is a read
    137 #define EMAC_MAN_HIGH           BIT30                   // Must be set
     132/* PHY Maintenance Register, EMAC_MAN, Offset 0x34 */
     133#define EMAC_MAN_DATA(_x_)      ((_x_ & 0xFFFF) <<  0)/* PHY data register */
     134#define EMAC_MAN_CODE           (0x2 << 16)           /* IEEE Code */
     135#define EMAC_MAN_REGA(_x_)      ((_x_ & 0x1F) << 18)  /* PHY register address */
     136#define EMAC_MAN_PHYA(_x_)      ((_x_ & 0x1F) << 23)  /* PHY address */
     137#define EMAC_MAN_WRITE          (0x1 << 28)           /* Transfer is a write */
     138#define EMAC_MAN_READ           (0x2 << 28)           /* Transfer is a read */
     139#define EMAC_MAN_HIGH           BIT30                 /* Must be set */
    138140#define EMAC_MAN_LOW            BIT31
    139141
    140 // Bit assignments for Receive Buffer Descriptor
    141 // Address - Word 0
    142 #define RXBUF_ADD_BASE_MASK     0xfffffffc      // Base addr of the rx buf
    143 #define RXBUF_ADD_WRAP          BIT1            // set indicates last buf
    144 #define RXBUF_ADD_OWNED         BIT0            // 1 = SW owns the pointer
     142/*
     143 * Bit assignments for Receive Buffer Descriptor
     144 * Address - Word 0
     145 */
     146#define RXBUF_ADD_BASE_MASK     0xfffffffc    /* Base addr of the rx buf */
     147#define RXBUF_ADD_WRAP          BIT1          /* set indicates last buf  */
     148#define RXBUF_ADD_OWNED         BIT0          /* 1 = SW owns the pointer */
    145149
    146 // Status - Word 1
    147 #define RXBUF_STAT_BCAST        BIT31           // Global bcast addr detected
    148 #define RXBUF_STAT_MULTI        BIT30           // Multicast hash match
    149 #define RXBUF_STAT_UNI          BIT29           // Unicast hash match
    150 #define RXBUF_STAT_EXT          BIT28           // External address (optional)
    151 #define RXBUF_STAT_UNK          BIT27           // Unknown source address
    152 #define RXBUF_STAT_LOC1         BIT26           // Local address 1 match
    153 #define RXBUF_STAT_LOC2         BIT25           // Local address 2 match
    154 #define RXBUF_STAT_LOC3         BIT24           // Local address 3 match
    155 #define RXBUF_STAT_LOC4         BIT23           // Local address 4 match
    156 #define RXBUF_STAT_LEN_MASK     0x7ff           // Len of frame including FCS
     150/* Status - Word 1 */
     151#define RXBUF_STAT_BCAST        BIT31         /* Global bcast addr detected */
     152#define RXBUF_STAT_MULTI        BIT30         /* Multicast hash match */
     153#define RXBUF_STAT_UNI          BIT29         /* Unicast hash match */
     154#define RXBUF_STAT_EXT          BIT28         /* External address (optional) */
     155#define RXBUF_STAT_UNK          BIT27         /* Unknown source address  */
     156#define RXBUF_STAT_LOC1         BIT26         /* Local address 1 match */
     157#define RXBUF_STAT_LOC2         BIT25         /* Local address 2 match */
     158#define RXBUF_STAT_LOC3         BIT24         /* Local address 3 match */
     159#define RXBUF_STAT_LOC4         BIT23         /* Local address 4 match  */
     160#define RXBUF_STAT_LEN_MASK     0x7ff         /* Len of frame including FCS */
    157161
    158162#endif /* __AT91RM9200_EMAC_H__ */
  • c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_gpio.h

    rea1d598 r5e14d89  
    1717#include <bits.h>
    1818
    19 // Register Offsets
    20 #define PIO_PER         0x00    // PIO Enable Register
    21 #define PIO_PDR         0x04    // PIO Disable Register
    22 #define PIO_PSR         0x08    // PIO Status Register
    23 #define PIO_OER         0x10    // Output Enable Register
    24 #define PIO_ODR         0x14    // Output Disable Registerr
    25 #define PIO_OSR         0x18    // Output Status Register
    26 #define PIO_IFER        0x20    // Input Filter Enable Register
    27 #define PIO_IFDR        0x24    // Input Filter Disable Register
    28 #define PIO_IFSR        0x28    // Input Filter Status Register
    29 #define PIO_SODR        0x30    // Set Output Data Register
    30 #define PIO_CODR        0x34    // Clear Output Data Register
    31 #define PIO_ODSR        0x38    // Output Data Status Register
    32 #define PIO_PDSR        0x3c    // Pin Data Status Register
    33 #define PIO_IER         0x40    // Interrupt Enable Register
    34 #define PIO_IDR         0x44    // Interrupt Disable Register
    35 #define PIO_IMR         0x48    // Interrupt Mask Register
    36 #define PIO_ISR         0x4c    // Interrupt Status Register
    37 #define PIO_MDER        0x50    // Multi-driver Enable Register
    38 #define PIO_MDDR        0x54    // Multi-driver Disable Register
    39 #define PIO_MDSR        0x58    // Multi-driver Status Register
    40 #define PIO_PUDR        0x60    // Pull-up Disable Register
    41 #define PIO_PUER        0x64    // Pull-up Enable Register
    42 #define PIO_PUSR        0x68    // Pad Pull-up Status Register
    43 #define PIO_ASR         0x70    // Select A Register
    44 #define PIO_BSR         0x74    // Select B Register
    45 #define PIO_ABSR        0x78    // AB Select Status Register
    46 #define PIO_OWER        0xA0    // Output Write Enable Register
    47 #define PIO_OWDR        0xA4    // Output Write Disable Register
    48 #define PIO_OWSR        0xA8    // Output Write Status Register
    49 
    50 
    51 // The AT91RM9200 GPIO's are spread across four 32-bit ports A-D.
    52 // To make it easier to interface with them and to eliminate the need
    53 // to track which GPIO is in which port, we     convert the Port x, Bit y
    54 // into a single GPIO number 0 - 127.
    55 //
    56 // Board specific defines will assign the board level signal to a
    57 // virutal GPIO.
    58 //
    59 // PORT A
     19/* Register Offsets */
     20#define PIO_PER         0x00    /* PIO Enable Register */
     21#define PIO_PDR         0x04    /* PIO Disable Register */
     22#define PIO_PSR         0x08    /* PIO Status Register */
     23#define PIO_OER         0x10    /* Output Enable Register */
     24#define PIO_ODR         0x14    /* Output Disable Registerr */
     25#define PIO_OSR         0x18    /* Output Status Register */
     26#define PIO_IFER        0x20    /* Input Filter Enable Register */
     27#define PIO_IFDR        0x24    /* Input Filter Disable Register */
     28#define PIO_IFSR        0x28    /* Input Filter Status Register */
     29#define PIO_SODR        0x30    /* Set Output Data Register */
     30#define PIO_CODR        0x34    /* Clear Output Data Register */
     31#define PIO_ODSR        0x38    /* Output Data Status Register */
     32#define PIO_PDSR        0x3c    /* Pin Data Status Register */
     33#define PIO_IER         0x40    /* Interrupt Enable Register */
     34#define PIO_IDR         0x44    /* Interrupt Disable Register */
     35#define PIO_IMR         0x48    /* Interrupt Mask Register */
     36#define PIO_ISR         0x4c    /* Interrupt Status Register */
     37#define PIO_MDER        0x50    /* Multi-driver Enable Register */
     38#define PIO_MDDR        0x54    /* Multi-driver Disable Register */
     39#define PIO_MDSR        0x58    /* Multi-driver Status Register */
     40#define PIO_PUDR        0x60    /* Pull-up Disable Register */
     41#define PIO_PUER        0x64    /* Pull-up Enable Register */
     42#define PIO_PUSR        0x68    /* Pad Pull-up Status Register */
     43#define PIO_ASR         0x70    /* Select A Register */
     44#define PIO_BSR         0x74    /* Select B Register */
     45#define PIO_ABSR        0x78    /* AB Select Status Register */
     46#define PIO_OWER        0xA0    /* Output Write Enable Register */
     47#define PIO_OWDR        0xA4    /* Output Write Disable Register */
     48#define PIO_OWSR        0xA8    /* Output Write Status Register */
     49
     50
     51/*
     52 * The AT91RM9200 GPIO's are spread across four 32-bit ports A-D.
     53 * To make it easier to interface with them and to eliminate the need
     54 * to track which GPIO is in which port, we     convert the Port x, Bit y
     55 * into a single GPIO number 0 - 127.
     56 *
     57 * Board specific defines will assign the board level signal to a
     58 * virutal GPIO.
     59 *
     60 * PORT A
     61 */
    6062#define GPIO_0          BIT0   
    6163#define GPIO_1          BIT1   
     
    9092#define GPIO_30         BIT30
    9193#define GPIO_31         BIT31
    92 // PORT B
     94/* PORT B */
    9395#define GPIO_32         BIT0   
    9496#define GPIO_33         BIT1   
     
    123125#define GPIO_62         BIT30
    124126#define GPIO_63         BIT31
    125 // PORT C
     127/* PORT C */
    126128#define GPIO_64         BIT0   
    127129#define GPIO_65         BIT1   
     
    156158#define GPIO_94         BIT30
    157159#define GPIO_95         BIT31
    158 // PORT D
     160/* PORT D */
    159161#define GPIO_96         BIT0   
    160162#define GPIO_97         BIT1   
     
    190192#define GPIO_127        BIT31
    191193
    192 // Most of the GPIO pins can have one of two alternate functions
    193 // in addition to being GPIO
    194 
    195 // Port A, Alternate Function A
    196 #define PIOA_ASR_MISO   BIT0    // SPI Master In (RX), Slave out
    197 #define PIOA_ASR_MOSI   BIT1    // SPI Master Out (TX), Slave In
    198 #define PIOA_ASR_SPCK   BIT2    // SPI Clock
    199 #define PIOA_ASR_NPCS0  BIT3    // SPI Chip Select 0
    200 #define PIOA_ASR_NPCS1  BIT4    // SPI Chip Select 1
    201 #define PIOA_ASR_NPCS2  BIT5    // SPI Chip Select 2
    202 #define PIOA_ASR_NPCS3  BIT6    // SPI Chip Select 3
    203 #define PIOA_ASR_ETXCK  BIT7    // EMAC TX Clock
    204 #define PIOA_ASR_ETXEN  BIT8    // EMAC TXEN
    205 #define PIOA_ASR_ETX0   BIT9    // EMAC TXD0
    206 #define PIOA_ASR_ETX1   BIT10   // EMAC TXD1
    207 #define PIOA_ASR_ECRS   BIT11   // EMAC CRS
    208 #define PIOA_ASR_ERX0   BIT12   // EMAC RXD0
    209 #define PIOA_ASR_ERX1   BIT13   // EMAC RXD1
    210 #define PIOA_ASR_ERXER  BIT14   // EMAC RXER
    211 #define PIOA_ASR_EMDC   BIT15   // EMAC MDC
    212 #define PIOA_ASR_EMDIO  BIT16   // EMAC MDIO
    213 #define PIOA_ASR_TXD0   BIT17   // USART 0 Receive
    214 #define PIOA_ASR_RXD0   BIT18   // USART 0 Transmit
    215 #define PIOA_ASR_SCK0   BIT19   // USART 0 Clock
    216 #define PIOA_ASR_CTS0   BIT20   // USART 0 CTS
    217 #define PIOA_ASR_RTS0   BIT21   // USART 0 RTS
    218 #define PIOA_ASR_RXD2   BIT22   // USART 2 Receive
    219 #define PIOA_ASR_TXD2   BIT23   // USART 2 Transmit
    220 #define PIOA_ASR_SCK2   BIT24   // USART 2 Clock
    221 #define PIOA_ASR_TWD    BIT25   // Two-Wire (I2C) Data
    222 #define PIOA_ASR_TWCK   BIT26   // Two-Wire (I2C) Clock
    223 #define PIOA_ASR_MCCK   BIT27   // MMC/SD Card Clock
    224 #define PIOA_ASR_MCCDA  BIT28   // MMC/SD Card A Command
    225 #define PIOA_ASR_MCDA0  BIT29   // MMC/SD Card A Data 0
    226 #define PIOA_ASR_DRXD   BIT30   // Debug Uart Receive
    227 #define PIOA_ASR_DTXD   BIT31   // Debug Uart Transmit
    228 
    229 // Port A, Alternate Function B
    230 #define PIOA_BSR_PCK3   BIT0    // Peripheral Clock 3
    231 #define PIOA_BSR_PCK0   BIT1    // Peripheral Clock 0
    232 #define PIOA_BSR_IRQ4   BIT2    // IRQ4
    233 #define PIOA_BSR_IRQ5   BIT3    // IRQ5
    234 //#define PIOA_BSR_PCK1 BIT4    // Peripheral Clock 1 ***DUPLICATED at BIT24 ???
    235 #define PIOA_BSR_TXD3   BIT5    // USART 3 Transmit
    236 #define PIOA_BSR_RXD3   BIT6    // USART 3 Receive
    237 #define PIOA_BSR_PCK2   BIT7    // Peripheral Clock 2
    238 #define PIOA_BSR_MCCDB  BIT8    // MMC/SD Card B Command
    239 #define PIOA_BSR_MCDB0  BIT9    // MMC/SD Card B Data 0
    240 #define PIOA_BSR_MCDB1  BIT10   // MMC/SD Card B Data 1
    241 #define PIOA_BSR_MCDB2  BIT11   // MMC/SD Card B Data 2
    242 #define PIOA_BSR_MCDB3  BIT12   // MMC/SD C ard B Data 3
    243 #define PIOA_BSR_TCLK0  BIT13   // Timer 0 Clock
    244 #define PIOA_BSR_TCLK1  BIT14   // Timer 1 Clck
    245 #define PIOA_BSR_TCLK2  BIT15   // Timer 2 Clock
    246 #define PIOA_BSR_IRQ6   BIT16   // IRQ6
    247 #define PIOA_BSR_TIOA0  BIT17   // Timer 0 I/O A
    248 #define PIOA_BSR_TIOB0  BIT18   // Timer 0 I/O B
    249 #define PIOA_BSR_TIOA1  BIT19   // Timer 1 I/O A
    250 #define PIOA_BSR_TIOB1  BIT20   // Timer 1 I/O B
    251 #define PIOA_BSR_TIOA2  BIT21   // Timer 2 I/O A
    252 #define PIOA_BSR_TIOB2  BIT22   // Timer 2 I/O B
    253 #define PIOA_BSR_IRQ3   BIT23   // IRQ3
    254 #define PIOA_BSR_PCK1   BIT24   // Peripheral Clock 1   
    255 #define PIOA_BSR_IRQ2   BIT25   // IRQ2
    256 #define PIOA_BSR_IRQ1   BIT26   // IRQ1
    257 #define PIOA_BSR_TCLK3  BIT27   // Timer Block Clock 3 (docs only show 0-2?)
    258 #define PIOA_BSR_TCLK4  BIT28   // Timer Block Clock 4
    259 #define PIOA_BSR_TCLK5  BIT29   // Timer Block Clock 5
    260 #define PIOA_BSR_CTS2   BIT30   // USART 2 CTS
    261 #define PIOA_BSR_RTS2   BIT31   // USART 2 RTS
    262 
    263 // Port B, Function A
    264 #define PIOB_ASR_TF0    BIT0    // AC'97/I2S 0 Transmit Frame
    265 #define PIOB_ASR_TK0    BIT1    // AC'97/I2S 0 Transmit Clock
    266 #define PIOB_ASR_TD0    BIT2    // AC'97/I2S 0 Transmit Data
    267 #define PIOB_ASR_RD0    BIT3    // AC'97/I2S 0 Receive Data
    268 #define PIOB_ASR_RK0    BIT4    // AC'97/I2S 0 Receive Clock
    269 #define PIOB_ASR_RF0    BIT5    // AC'97/I2S 0 Receive Frame
    270 #define PIOB_ASR_TF1    BIT6    // AC'97/I2S 1 Transmit Frame
    271 #define PIOB_ASR_TK1    BIT7    // AC'97/I2S 1 Transmit Clock
    272 #define PIOB_ASR_TD1    BIT8    // AC'97/I2S 1 Transmit Data
    273 #define PIOB_ASR_RD1    BIT9    // AC'97/I2S 1 Receive Data
    274 #define PIOB_ASR_RK1    BIT10   // AC'97/I2S 1 Receive Clock
    275 #define PIOB_ASR_RF1    BIT11   // AC'97/I2S 1 Receive Frame
    276 #define PIOB_ASR_TF2    BIT12   // AC'97/I2S 1 Transmit Frame
    277 #define PIOB_ASR_TK2    BIT13   // AC'97/I2S 1 Transmit Clock
    278 #define PIOB_ASR_TD2    BIT14   // AC'97/I2S 1 Transmit Data 
    279 #define PIOB_ASR_RD2    BIT15   // AC'97/I2S 1 Receive Data 
    280 #define PIOB_ASR_RK2    BIT16   // AC'97/I2S 1 Receive Clock 
    281 #define PIOB_ASR_RF2    BIT17   // AC'97/I2S 1 Receive Frame 
    282 #define PIOB_ASR_RI1    BIT18   // USART 1 RI
    283 #define PIOB_ASR_DTR1   BIT19   // USART 1 DTR
    284 #define PIOB_ASR_TXD1   BIT20   // USART 1 TXD
    285 #define PIOB_ASR_RXD1   BIT21   // USART 1 RXD
    286 #define PIOB_ASR_SCK1   BIT22   // USART 1 SCK
    287 #define PIOB_ASR_DCD1   BIT23   // USART 1 DCD
    288 #define PIOB_ASR_CTS1   BIT24   // USART 1 CTS
    289 #define PIOB_ASR_DSR1   BIT25   // USART 1 DSR
    290 #define PIOB_ASR_RTS1   BIT26   // USART 1 RTS
    291 #define PIOB_ASR_PCK0   BIT27   // Peripheral Clock 0
    292 #define PIOB_ASR_FIQ    BIT28   // FIQ
    293 #define PIOB_ASR_IRQ0   BIT29   // IRQ0
    294 
    295 // Port B, Function B
    296 #define PIOB_BSR_RTS3   BIT0    // USART 3
    297 #define PIOB_BSR_CTS3   BIT1    // USART 3
    298 #define PIOB_BSR_SCK3   BIT2    // USART 3
    299 #define PIOB_BSR_MCDA1  BIT3    // MMC/SD Card A, Data 1
    300 #define PIOB_BSR_MCDA2  BIT4    // MMC/SD Card A, Data 2
    301 #define PIOB_BSR_MCDA3  BIT5    // MMC/SD Card A, Data 3
    302 #define PIOB_BSR_TIOA3  BIT6    // Timer 3 IO A
    303 #define PIOB_BSR_TIOB3  BIT7    // Timer 3 IO B
    304 #define PIOB_BSR_TIOA4  BIT8    // Timer 4 IO A
    305 #define PIOB_BSR_TIOB4  BIT9    // Timer 4 IO B
    306 #define PIOB_BSR_TIOA5  BIT10   // Timer 5 IO A
    307 #define PIOB_BSR_TIOB5  BIT11   // Timer 5 IO B
    308 #define PIOB_BSR_ETX2   BIT12   // EMAC TXD2
    309 #define PIOB_BSR_ETX3   BIT13   // EMAC TXD3
    310 #define PIOB_BSR_ETXER  BIT14   // EMAC TXER
    311 #define PIOB_BSR_ERX2   BIT15   // EMAC RXD2
    312 #define PIOB_BSR_ERX3   BIT16   // EMAC RXD3
    313 #define PIOB_BSR_ERXDV  BIT17   // EMAC RXDV
    314 #define PIOB_BSR_ECOL   BIT18   // EMAC COL
    315 #define PIOB_BSR_ERXCK  BIT19   // EMAC RX Clock
    316 #define PIOB_BSR_EF100  BIT25   // EMAC Speed 100 (RMII Only)
    317 
    318 // Port C, Alternate Function A
    319 #define PIOC_ASR_BFCK   BIT0    // Burst Flash Clock
    320 #define PIOC_ASR_BFRDY  BIT1    // Burst Flash Ready or SMC Card OE
    321 #define PIOC_ASR_BFAVD  BIT2    // Burst Flash Address Valid
    322 #define PIOC_ASR_BFBAA  BIT3    // Burst Flash Address Advance or SMC Card WE
    323 #define PIOC_ASR_BFOE   BIT4    // Burst Flash OE
    324 #define PIOC_ASR_BFWE   BIT5    // Burst Flash WE
    325 #define PIOC_ASR_NWAIT  BIT6    // WAIT Input
    326 #define PIOC_ASR_A23    BIT7    // A23
    327 #define PIOC_ASR_A24    BIT8    // A24
    328 #define PIOC_ASR_A25    BIT9    // A25 or Compact Flash R/W
    329 #define PIOC_ASR_NCS4   BIT10   // CS4 or Compact Flash CS
    330 #define PIOC_ASR_NCS5   BIT11   // CS5 or Compact Flash CE1
    331 #define PIOC_ASR_NCS6   BIT12   // CS6 or Compact Flash CE2
    332 #define PIOC_ASR_NCS7   BIT13   // CS7
    333 #define PIOC_ASR_D16    BIT16   // Databus Bit 16
    334 #define PIOC_ASR_D17    BIT17   // Databus Bit 17
    335 #define PIOC_ASR_D18    BIT18   // Databus Bit 18
    336 #define PIOC_ASR_D19    BIT19   // Databus Bit 19
    337 #define PIOC_ASR_D20    BIT20   // Databus Bit 20
    338 #define PIOC_ASR_D21    BIT21   // Databus Bit 21
    339 #define PIOC_ASR_D22    BIT22   // Databus Bit 22
    340 #define PIOC_ASR_D23    BIT23   // Databus Bit 23
    341 #define PIOC_ASR_D24    BIT24   // Databus Bit 24
    342 #define PIOC_ASR_D25    BIT25   // Databus Bit 25
    343 #define PIOC_ASR_D26    BIT26   // Databus Bit 26
    344 #define PIOC_ASR_D27    BIT27   // Databus Bit 27
    345 #define PIOC_ASR_D28    BIT28   // Databus Bit 28
    346 #define PIOC_ASR_D29    BIT29   // Databus Bit 29
    347 #define PIOC_ASR_D30    BIT30   // Databus Bit 30
    348 #define PIOC_ASR_D31    BIT31   // Databus Bit 31
    349 
    350 // Port C, Alternate Function B - None
    351 
    352 // Port D, Alternate Function A
    353 #define PIOD_ASR_ETX0   BIT0    // EMAC TXD0
    354 #define PIOD_ASR_ETX1   BIT1    // EMAC TXD1
    355 #define PIOD_ASR_ETX2   BIT2    // EMAC TXD2
    356 #define PIOD_ASR_ETX3   BIT3    // EMAC TXD3
    357 #define PIOD_ASR_ETXEN  BIT4    // EMAC TXEN
    358 #define PIOD_ASR_ETXER  BIT5    // EMAC TXER
    359 #define PIOD_ASR_DTXD   BIT6    // Debug UART Transmit
    360 #define PIOD_ASR_PCK0   BIT7    // Peripheral Clock 0
    361 #define PIOD_ASR_PCK1   BIT8    // Peripheral Clock 1
    362 #define PIOD_ASR_PCK2   BIT9    // Peripheral Clock 2
    363 #define PIOD_ASR_PCK3   BIT10   // Peripheral Clock 3
    364 #define PIOD_ASR_TD0    BIT15   // AC'97/I2S 0 Transmit Data
    365 #define PIOD_ASR_TD1    BIT16   // AC'97/I2S 1 Transmit Data
    366 #define PIOD_ASR_TD2    BIT17   // AC'97/I2S 2 Transmit Data
    367 #define PIOD_ASR_NPCS1  BIT18   // SPI Chip Select 1
    368 #define PIOD_ASR_NPCS2  BIT19   // SPI Chip Select 2
    369 #define PIOD_ASR_NPCS3  BIT20   // SPI Chip Select 3
    370 #define PIOD_ASR_RTS0   BIT21   // USART 0 RTS
    371 #define PIOD_ASR_RTS1   BIT22   // USART 1 RTS
    372 #define PIOD_ASR_RTS2   BIT23   // USART 2 RTS
    373 #define PIOD_ASR_RTS3   BIT24   // USART 3 RTS
    374 #define PIOD_ASR_DTR1   BIT25   // USART 1 DTR
     194/*
     195 * Most of the GPIO pins can have one of two alternate functions
     196 * in addition to being GPIO
     197 *
     198 * Port A, Alternate Function A
     199 */
     200#define PIOA_ASR_MISO   BIT0    /* SPI Master In (RX), Slave out */
     201#define PIOA_ASR_MOSI   BIT1    /* SPI Master Out (TX), Slave In */
     202#define PIOA_ASR_SPCK   BIT2    /* SPI Clock */
     203#define PIOA_ASR_NPCS0  BIT3    /* SPI Chip Select 0 */
     204#define PIOA_ASR_NPCS1  BIT4    /* SPI Chip Select 1 */
     205#define PIOA_ASR_NPCS2  BIT5    /* SPI Chip Select 2 */
     206#define PIOA_ASR_NPCS3  BIT6    /* SPI Chip Select 3 */
     207#define PIOA_ASR_ETXCK  BIT7    /* EMAC TX Clock */
     208#define PIOA_ASR_ETXEN  BIT8    /* EMAC TXEN */
     209#define PIOA_ASR_ETX0   BIT9    /* EMAC TXD0 */
     210#define PIOA_ASR_ETX1   BIT10   /* EMAC TXD1  */
     211#define PIOA_ASR_ECRS   BIT11   /* EMAC CRS */
     212#define PIOA_ASR_ERX0   BIT12   /* EMAC RXD0 */
     213#define PIOA_ASR_ERX1   BIT13   /* EMAC RXD1 */
     214#define PIOA_ASR_ERXER  BIT14   /* EMAC RXER */
     215#define PIOA_ASR_EMDC   BIT15   /* EMAC MDC */
     216#define PIOA_ASR_EMDIO  BIT16   /* EMAC MDIO */
     217#define PIOA_ASR_TXD0   BIT17   /* USART 0 Receive */
     218#define PIOA_ASR_RXD0   BIT18   /* USART 0 Transmit */
     219#define PIOA_ASR_SCK0   BIT19   /* USART 0 Clock */
     220#define PIOA_ASR_CTS0   BIT20   /* USART 0 CTS */
     221#define PIOA_ASR_RTS0   BIT21   /* USART 0 RTS */
     222#define PIOA_ASR_RXD2   BIT22   /* USART 2 Receive */
     223#define PIOA_ASR_TXD2   BIT23   /* USART 2 Transmit */
     224#define PIOA_ASR_SCK2   BIT24   /* USART 2 Clock */
     225#define PIOA_ASR_TWD    BIT25   /* Two-Wire (I2C) Data */
     226#define PIOA_ASR_TWCK   BIT26   /* Two-Wire (I2C) Clock */
     227#define PIOA_ASR_MCCK   BIT27   /* MMC/SD Card Clock */
     228#define PIOA_ASR_MCCDA  BIT28   /* MMC/SD Card A Command */
     229#define PIOA_ASR_MCDA0  BIT29   /* MMC/SD Card A Data 0 */
     230#define PIOA_ASR_DRXD   BIT30   /* Debug Uart Receive */
     231#define PIOA_ASR_DTXD   BIT31   /* Debug Uart Transmit */
     232
     233/* Port A, Alternate Function B */
     234#define PIOA_BSR_PCK3   BIT0    /* Peripheral Clock 3 */
     235#define PIOA_BSR_PCK0   BIT1    /* Peripheral Clock 0 */
     236#define PIOA_BSR_IRQ4   BIT2    /* IRQ4 */
     237#define PIOA_BSR_IRQ5   BIT3    /* IRQ5 */
     238/*#define PIOA_BSR_PCK1 BIT4     Peripheral Clock 1 ***DUPLICATED at BIT24 ??? */
     239#define PIOA_BSR_TXD3   BIT5    /* USART 3 Transmit */
     240#define PIOA_BSR_RXD3   BIT6    /* USART 3 Receive */
     241#define PIOA_BSR_PCK2   BIT7    /* Peripheral Clock 2 */
     242#define PIOA_BSR_MCCDB  BIT8    /* MMC/SD Card B Command */
     243#define PIOA_BSR_MCDB0  BIT9    /* MMC/SD Card B Data 0 */
     244#define PIOA_BSR_MCDB1  BIT10   /* MMC/SD Card B Data 1 */
     245#define PIOA_BSR_MCDB2  BIT11   /* MMC/SD Card B Data 2 */
     246#define PIOA_BSR_MCDB3  BIT12   /* MMC/SD C ard B Data 3 */
     247#define PIOA_BSR_TCLK0  BIT13   /* Timer 0 Clock */
     248#define PIOA_BSR_TCLK1  BIT14   /* Timer 1 Clck */
     249#define PIOA_BSR_TCLK2  BIT15   /* Timer 2 Clock */
     250#define PIOA_BSR_IRQ6   BIT16   /* IRQ6 */
     251#define PIOA_BSR_TIOA0  BIT17   /* Timer 0 I/O A */
     252#define PIOA_BSR_TIOB0  BIT18   /* Timer 0 I/O B */
     253#define PIOA_BSR_TIOA1  BIT19   /* Timer 1 I/O A */
     254#define PIOA_BSR_TIOB1  BIT20   /* Timer 1 I/O B */
     255#define PIOA_BSR_TIOA2  BIT21   /* Timer 2 I/O A */
     256#define PIOA_BSR_TIOB2  BIT22   /* Timer 2 I/O B */
     257#define PIOA_BSR_IRQ3   BIT23   /* IRQ3 */
     258#define PIOA_BSR_PCK1   BIT24   /* Peripheral Clock 1    */
     259#define PIOA_BSR_IRQ2   BIT25   /* IRQ2 */
     260#define PIOA_BSR_IRQ1   BIT26   /* IRQ1 */
     261#define PIOA_BSR_TCLK3  BIT27   /* Timer Block Clock 3 (docs only show 0-2?) */
     262#define PIOA_BSR_TCLK4  BIT28   /* Timer Block Clock 4 */
     263#define PIOA_BSR_TCLK5  BIT29   /* Timer Block Clock 5 */
     264#define PIOA_BSR_CTS2   BIT30   /* USART 2 CTS */
     265#define PIOA_BSR_RTS2   BIT31   /* USART 2 RTS */
     266
     267/* Port B, Function A */
     268#define PIOB_ASR_TF0    BIT0    /* AC'97/I2S 0 Transmit Frame  */
     269#define PIOB_ASR_TK0    BIT1    /* AC'97/I2S 0 Transmit Clock  */
     270#define PIOB_ASR_TD0    BIT2    /* AC'97/I2S 0 Transmit Data */
     271#define PIOB_ASR_RD0    BIT3    /* AC'97/I2S 0 Receive Data */
     272#define PIOB_ASR_RK0    BIT4    /* AC'97/I2S 0 Receive Clock */
     273#define PIOB_ASR_RF0    BIT5    /* AC'97/I2S 0 Receive Frame */
     274#define PIOB_ASR_TF1    BIT6    /* AC'97/I2S 1 Transmit Frame  */
     275#define PIOB_ASR_TK1    BIT7    /* AC'97/I2S 1 Transmit Clock  */
     276#define PIOB_ASR_TD1    BIT8    /* AC'97/I2S 1 Transmit Data  */
     277#define PIOB_ASR_RD1    BIT9    /* AC'97/I2S 1 Receive Data  */
     278#define PIOB_ASR_RK1    BIT10   /* AC'97/I2S 1 Receive Clock  */
     279#define PIOB_ASR_RF1    BIT11   /* AC'97/I2S 1 Receive Frame  */
     280#define PIOB_ASR_TF2    BIT12   /* AC'97/I2S 1 Transmit Frame  */
     281#define PIOB_ASR_TK2    BIT13   /* AC'97/I2S 1 Transmit Clock  */
     282#define PIOB_ASR_TD2    BIT14   /* AC'97/I2S 1 Transmit Data   */
     283#define PIOB_ASR_RD2    BIT15   /* AC'97/I2S 1 Receive Data   */
     284#define PIOB_ASR_RK2    BIT16   /* AC'97/I2S 1 Receive Clock   */
     285#define PIOB_ASR_RF2    BIT17   /* AC'97/I2S 1 Receive Frame   */
     286#define PIOB_ASR_RI1    BIT18   /* USART 1 RI  */
     287#define PIOB_ASR_DTR1   BIT19   /* USART 1 DTR */
     288#define PIOB_ASR_TXD1   BIT20   /* USART 1 TXD */
     289#define PIOB_ASR_RXD1   BIT21   /* USART 1 RXD */
     290#define PIOB_ASR_SCK1   BIT22   /* USART 1 SCK */
     291#define PIOB_ASR_DCD1   BIT23   /* USART 1 DCD */
     292#define PIOB_ASR_CTS1   BIT24   /* USART 1 CTS */
     293#define PIOB_ASR_DSR1   BIT25   /* USART 1 DSR */
     294#define PIOB_ASR_RTS1   BIT26   /* USART 1 RTS */
     295#define PIOB_ASR_PCK0   BIT27   /* Peripheral Clock 0  */
     296#define PIOB_ASR_FIQ    BIT28   /* FIQ */
     297#define PIOB_ASR_IRQ0   BIT29   /* IRQ0 */
     298
     299/* Port B, Function B */
     300#define PIOB_BSR_RTS3   BIT0    /* USART 3 */
     301#define PIOB_BSR_CTS3   BIT1    /* USART 3 */
     302#define PIOB_BSR_SCK3   BIT2    /* USART 3 */
     303#define PIOB_BSR_MCDA1  BIT3    /* MMC/SD Card A, Data 1 */
     304#define PIOB_BSR_MCDA2  BIT4    /* MMC/SD Card A, Data 2 */
     305#define PIOB_BSR_MCDA3  BIT5    /* MMC/SD Card A, Data 3 */
     306#define PIOB_BSR_TIOA3  BIT6    /* Timer 3 IO A */
     307#define PIOB_BSR_TIOB3  BIT7    /* Timer 3 IO B */
     308#define PIOB_BSR_TIOA4  BIT8    /* Timer 4 IO A */
     309#define PIOB_BSR_TIOB4  BIT9    /* Timer 4 IO B */
     310#define PIOB_BSR_TIOA5  BIT10   /* Timer 5 IO A */
     311#define PIOB_BSR_TIOB5  BIT11   /* Timer 5 IO B */
     312#define PIOB_BSR_ETX2   BIT12   /* EMAC TXD2 */
     313#define PIOB_BSR_ETX3   BIT13   /* EMAC TXD3 */
     314#define PIOB_BSR_ETXER  BIT14   /* EMAC TXER */
     315#define PIOB_BSR_ERX2   BIT15   /* EMAC RXD2 */
     316#define PIOB_BSR_ERX3   BIT16   /* EMAC RXD3 */
     317#define PIOB_BSR_ERXDV  BIT17   /* EMAC RXDV */
     318#define PIOB_BSR_ECOL   BIT18   /* EMAC COL */
     319#define PIOB_BSR_ERXCK  BIT19   /* EMAC RX Clock */
     320#define PIOB_BSR_EF100  BIT25   /* EMAC Speed 100 (RMII Only) */
     321
     322/* Port C, Alternate Function A */
     323#define PIOC_ASR_BFCK   BIT0    /* Burst Flash Clock */
     324#define PIOC_ASR_BFRDY  BIT1    /* Burst Flash Ready or SMC Card OE */
     325#define PIOC_ASR_BFAVD  BIT2    /* Burst Flash Address Valid */
     326#define PIOC_ASR_BFBAA  BIT3    /* Burst Flash Address Advance or SMC Card WE */
     327#define PIOC_ASR_BFOE   BIT4    /* Burst Flash OE */
     328#define PIOC_ASR_BFWE   BIT5    /* Burst Flash WE */
     329#define PIOC_ASR_NWAIT  BIT6    /* WAIT Input */
     330#define PIOC_ASR_A23    BIT7    /* A23 */
     331#define PIOC_ASR_A24    BIT8    /* A24 */
     332#define PIOC_ASR_A25    BIT9    /* A25 or Compact Flash R/W */
     333#define PIOC_ASR_NCS4   BIT10   /* CS4 or Compact Flash CS */
     334#define PIOC_ASR_NCS5   BIT11   /* CS5 or Compact Flash CE1 */
     335#define PIOC_ASR_NCS6   BIT12   /* CS6 or Compact Flash CE2 */
     336#define PIOC_ASR_NCS7   BIT13   /* CS7 */
     337#define PIOC_ASR_D16    BIT16   /* Databus Bit 16 */
     338#define PIOC_ASR_D17    BIT17   /* Databus Bit 17 */
     339#define PIOC_ASR_D18    BIT18   /* Databus Bit 18 */
     340#define PIOC_ASR_D19    BIT19   /* Databus Bit 19 */
     341#define PIOC_ASR_D20    BIT20   /* Databus Bit 20 */
     342#define PIOC_ASR_D21    BIT21   /* Databus Bit 21 */
     343#define PIOC_ASR_D22    BIT22   /* Databus Bit 22 */
     344#define PIOC_ASR_D23    BIT23   /* Databus Bit 23 */
     345#define PIOC_ASR_D24    BIT24   /* Databus Bit 24 */
     346#define PIOC_ASR_D25    BIT25   /* Databus Bit 25 */
     347#define PIOC_ASR_D26    BIT26   /* Databus Bit 26 */
     348#define PIOC_ASR_D27    BIT27   /* Databus Bit 27 */
     349#define PIOC_ASR_D28    BIT28   /* Databus Bit 28 */
     350#define PIOC_ASR_D29    BIT29   /* Databus Bit 29 */
     351#define PIOC_ASR_D30    BIT30   /* Databus Bit 30 */
     352#define PIOC_ASR_D31    BIT31   /* Databus Bit 31 */
     353
     354/* Port C, Alternate Function B - None */
     355
     356/* Port D, Alternate Function A */
     357#define PIOD_ASR_ETX0   BIT0    /* EMAC TXD0 */
     358#define PIOD_ASR_ETX1   BIT1    /* EMAC TXD1 */
     359#define PIOD_ASR_ETX2   BIT2    /* EMAC TXD2 */
     360#define PIOD_ASR_ETX3   BIT3    /* EMAC TXD3 */
     361#define PIOD_ASR_ETXEN  BIT4    /* EMAC TXEN */
     362#define PIOD_ASR_ETXER  BIT5    /* EMAC TXER */
     363#define PIOD_ASR_DTXD   BIT6    /* Debug UART Transmit */
     364#define PIOD_ASR_PCK0   BIT7    /* Peripheral Clock 0 */
     365#define PIOD_ASR_PCK1   BIT8    /* Peripheral Clock 1 */
     366#define PIOD_ASR_PCK2   BIT9    /* Peripheral Clock 2 */
     367#define PIOD_ASR_PCK3   BIT10   /* Peripheral Clock 3 */
     368#define PIOD_ASR_TD0    BIT15   /* AC'97/I2S 0 Transmit Data */
     369#define PIOD_ASR_TD1    BIT16   /* AC'97/I2S 1 Transmit Data */
     370#define PIOD_ASR_TD2    BIT17   /* AC'97/I2S 2 Transmit Data */
     371#define PIOD_ASR_NPCS1  BIT18   /* SPI Chip Select 1 */
     372#define PIOD_ASR_NPCS2  BIT19   /* SPI Chip Select 2 */
     373#define PIOD_ASR_NPCS3  BIT20   /* SPI Chip Select 3 */
     374#define PIOD_ASR_RTS0   BIT21   /* USART 0 RTS */
     375#define PIOD_ASR_RTS1   BIT22   /* USART 1 RTS */
     376#define PIOD_ASR_RTS2   BIT23   /* USART 2 RTS */
     377#define PIOD_ASR_RTS3   BIT24   /* USART 3 RTS */
     378#define PIOD_ASR_DTR1   BIT25   /* USART 1 DTR */
    375379                   
    376 // Port D, Alternate Function B
     380/* Port D, Alternate Function B */
    377381               
    378 #define PIOC_ASR_TSYNC  BIT7    // ETM Sync     
    379 #define PIOC_ASR_TCLK   BIT8    // ETM Clock
    380 #define PIOC_ASR_TPS0   BIT9    // ETM Processor Status 0
    381 #define PIOC_ASR_TPS1   BIT10   // ETM Processor Status 1
    382 #define PIOC_ASR_TPS2   BIT11   // ETM Processor Status 2
    383 #define PIOC_ASR_TPK0   BIT12   // ETM Packet Data 0
    384 #define PIOC_ASR_TPK1   BIT13   // ETM Packet Data 1
    385 #define PIOC_ASR_TPK2   BIT14   // ETM Packet Data 2
    386 #define PIOC_ASR_TPK3   BIT15   // ETM Packet Data 3
    387 #define PIOC_ASR_TPK4   BIT16   // ETM Packet Data 4
    388 #define PIOC_ASR_TPK5   BIT17   // ETM Packet Data 5
    389 #define PIOC_ASR_TPK6   BIT18   // ETM Packet Data 6
    390 #define PIOC_ASR_TPK7   BIT19   // ETM Packet Data 7
    391 #define PIOC_ASR_TPK8   BIT20   // ETM Packet Data 8
    392 #define PIOC_ASR_TPK9   BIT21   // ETM Packet Data 9
    393 #define PIOC_ASR_TPK10  BIT22   // ETM Packet Data 10
    394 #define PIOC_ASR_TPK11  BIT23   // ETM Packet Data 11
    395 #define PIOC_ASR_TPK12  BIT24   // ETM Packet Data 12
    396 #define PIOC_ASR_TPK13  BIT25   // ETM Packet Data 13
    397 #define PIOC_ASR_TPK14  BIT26   // ETM Packet Data 14
    398 #define PIOC_ASR_TPK15  BIT27   // ETM Packet Data 15
     382#define PIOC_ASR_TSYNC  BIT7    /* ETM Sync      */
     383#define PIOC_ASR_TCLK   BIT8    /* ETM Clock */
     384#define PIOC_ASR_TPS0   BIT9    /* ETM Processor Status 0 */
     385#define PIOC_ASR_TPS1   BIT10   /* ETM Processor Status 1 */
     386#define PIOC_ASR_TPS2   BIT11   /* ETM Processor Status 2 */
     387#define PIOC_ASR_TPK0   BIT12   /* ETM Packet Data 0 */
     388#define PIOC_ASR_TPK1   BIT13   /* ETM Packet Data 1 */
     389#define PIOC_ASR_TPK2   BIT14   /* ETM Packet Data 2 */
     390#define PIOC_ASR_TPK3   BIT15   /* ETM Packet Data 3 */
     391#define PIOC_ASR_TPK4   BIT16   /* ETM Packet Data 4 */
     392#define PIOC_ASR_TPK5   BIT17   /* ETM Packet Data 5 */
     393#define PIOC_ASR_TPK6   BIT18   /* ETM Packet Data 6 */
     394#define PIOC_ASR_TPK7   BIT19   /* ETM Packet Data 7 */
     395#define PIOC_ASR_TPK8   BIT20   /* ETM Packet Data 8 */
     396#define PIOC_ASR_TPK9   BIT21   /* ETM Packet Data 9 */
     397#define PIOC_ASR_TPK10  BIT22   /* ETM Packet Data 10 */
     398#define PIOC_ASR_TPK11  BIT23   /* ETM Packet Data 11 */
     399#define PIOC_ASR_TPK12  BIT24   /* ETM Packet Data 12 */
     400#define PIOC_ASR_TPK13  BIT25   /* ETM Packet Data 13 */
     401#define PIOC_ASR_TPK14  BIT26   /* ETM Packet Data 14 */
     402#define PIOC_ASR_TPK15  BIT27   /* ETM Packet Data 15 */
    399403
    400404#endif
  • c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_mem.h

    rea1d598 r5e14d89  
    1515#define AT91RM9200_MEM_H
    1616
    17 // *****************************************************************************
    18 // External Bus Interface Unit
    19 // *****************************************************************************
    20 #define EBI_CSA                                 0x00    // Chip Select Assignment Register
    21 #define EBI_CFGR                                0x04    // Configuration Register
     17/**********************************************************************
     18 *      External Bus Interface Unit
     19 **********************************************************************/
     20#define EBI_CSA             0x00    /* Chip Select Assignment Register */
     21#define EBI_CFGR            0x04    /* Configuration Register */
    2222
    23 // Bit Defines
    24 // EBI_CSA - Chip Select Assignment Register
    25 #define EBI_CSA_CS4_CF                  BIT4    // 1 = CS4-6 are assigned to Compact Flash, 0 = Chip Selects
    26 #define EBI_CSA_CS3_SMM                 BIT3    // 1 = CS3 is assigned to SmartMedia, 0 = Chip Select
    27 #define EBI_CSA_CS1_SDRAM               BIT1    // 1 = CS1 is assigned to SDRAM, 0 = Chip Select
    28 #define EBI_CSA_CS0_BF                  BIT0    // 1 = CS0 is assigned to Burst Flash, 0 = Chip Select
     23/* Bit Defines */
     24/* EBI_CSA - Chip Select Assignment Register */
     25#define EBI_CSA_CS4_CF        BIT4    /* 1 = CS4-6 are assigned to Compact Flash, 0 = Chip Selects */
     26#define EBI_CSA_CS3_SMM       BIT3    /* 1 = CS3 is assigned to SmartMedia, 0 = Chip Select */
     27#define EBI_CSA_CS1_SDRAM     BIT1    /* 1 = CS1 is assigned to SDRAM, 0 = Chip Select */
     28#define EBI_CSA_CS0_BF        BIT0    /* 1 = CS0 is assigned to Burst Flash, 0 = Chip Select */
    2929
    30 // EBI_CFGR     - Configuration Register
    31 #define EBI_CFGR_DBPU                   BIT0    // 1 = Disable D0-15 pullups                           
     30/* EBI_CFGR     - Configuration Register */
     31#define EBI_CFGR_DBPU         BIT0    /* 1 = Disable D0-15 pullups         */
    3232
    33 // *****************************************************************************
    34 // Static Memory Interface Unit
    35 // *****************************************************************************
    36 #define SMC_CSR0                                0x00    // Chip Select Register 0
    37 #define SMC_CSR1                                0x04    // Chip Select Register 1
    38 #define SMC_CSR2                                0x08    // Chip Select Register 2
    39 #define SMC_CSR3                                0x0C    // Chip Select Register 3
    40 #define SMC_CSR4                                0x10    // Chip Select Register 4
    41 #define SMC_CSR5                                0x14    // Chip Select Register 5
    42 #define SMC_CSR6                                0x18    // Chip Select Register 6
    43 #define SMC_CSR7                                0x1C    // Chip Select Register 7
     33/***************************************************************************
     34 * Static Memory Interface Unit
     35 ***************************************************************************/
     36#define SMC_CSR0            0x00    /* Chip Select Register 0  */
     37#define SMC_CSR1            0x04    /* Chip Select Register 1  */
     38#define SMC_CSR2            0x08    /* Chip Select Register 2  */
     39#define SMC_CSR3            0x0C    /* Chip Select Register 3  */
     40#define SMC_CSR4            0x10    /* Chip Select Register 4  */
     41#define SMC_CSR5            0x14    /* Chip Select Register 5  */
     42#define SMC_CSR6            0x18    /* Chip Select Register 6  */
     43#define SMC_CSR7            0x1C    /* Chip Select Register 7  */
    4444
    45 // Bit Defines
    46 // SMC_CSR0 -7 - Chip Selects 0 - 7 Register
    47 #define SMC_CSR_RWHOLD(_x_)             ((_x_ & 0x3) << 28)     // Hold CS after R/W strobes
    48 #define SMC_CSR_RWSETUP(_x_)    ((_x_ & 0x3) << 24)     // Setup CS before R/W strobes
    49 #define SMC_CSR_ACSS_0                  (0 << 16)                               // Setup/Hold Address 0 clocks before/after CS
    50 #define SMC_CSR_ACSS_1                  (1 << 16)                               // Setup/Hold Address 1 clock before/after CS
    51 #define SMC_CSR_ACSS_2                  (2 << 16)                               // Setup/Hold Address 2 clocks before/after CS
    52 #define SMC_CSR_ACSS_3                  (3 << 16)                               // Setup/Hold Address 3 clocks before/after CS
    53 #define SMC_CSR_DRP_NORMAL              0                                               // 0 = normal read protocol
    54 #define SMC_CSR_DRP_EARLY               BIT15                                   // 1 = early read protocol
    55 #define SMC_CSR_DBW_16                  (1 << 13)                               // CS DataBus Width = 16-Bits
    56 #define SMC_CSR_DBW_8                   (2 << 13)                               // CS DataBus Width = 8 Bits
    57 #define SMC_CSR_BAT_16_1                0                                               // Single 16-Bit device (when DBW is 16)
    58 #define SMC_CSR_BAT_16_2                BIT12                                   // Dual 8-Bit devices (when DBW is 16)
    59 #define SMC_CSR_TDF(_x_)                ((_x_ & 0xf) << 8)              // Intercycle Data Float Time
    60 #define SMC_CSR_WSEN                    BIT7                                    // 1 = wait states are enabled
    61 #define SMC_CSR_NWS(_x_)                ((_x_ & 0x7f) << 0)     // Wait States + 1
     45/* Bit Defines */
     46/* SMC_CSR0 -7 - Chip Selects 0 - 7 Register */
     47#define SMC_CSR_RWHOLD(_x_)        ((_x_ & 0x3) << 28)     /* Hold CS after R/W strobes */
     48#define SMC_CSR_RWSETUP(_x_)    ((_x_ & 0x3) << 24)     /* Setup CS before R/W strobes */
     49#define SMC_CSR_ACSS_0        (0 << 16)           /* Setup/Hold Address 0 clocks before/after CS */
     50#define SMC_CSR_ACSS_1        (1 << 16)           /* Setup/Hold Address 1 clock before/after CS */
     51#define SMC_CSR_ACSS_2        (2 << 16)           /* Setup/Hold Address 2 clocks before/after CS */
     52#define SMC_CSR_ACSS_3        (3 << 16)           /* Setup/Hold Address 3 clocks before/after CS */
     53#define SMC_CSR_DRP_NORMAL    0                 /* 0 = normal read protocol */
     54#define SMC_CSR_DRP_EARLY     BIT15          /* 1 = early read protocol */
     55#define SMC_CSR_DBW_16        (1 << 13)           /* CS DataBus Width = 16-Bits */
     56#define SMC_CSR_DBW_8         (2 << 13)           /* CS DataBus Width = 8 Bits */
     57#define SMC_CSR_BAT_16_1      0                 /* Single 16-Bit device (when DBW is 16) */
     58#define SMC_CSR_BAT_16_2      BIT12          /* Dual 8-Bit devices (when DBW is 16) */
     59#define SMC_CSR_TDF(_x_)      ((_x_ & 0xf) << 8)    /* Intercycle Data Float Time */
     60#define SMC_CSR_WSEN          BIT7           /* 1 = wait states are enabled */
     61#define SMC_CSR_NWS(_x_)      ((_x_ & 0x7f) << 0)     /* Wait States + 1 */
    6262
    63 // *****************************************************************************
    64 // SDRAM Memory Interface Unit
    65 // *****************************************************************************
    66 #define SDRC_MR                                 0x00            // Mode Register
    67 #define SDRC_TR                                 0x04            // Refresh Timer Register
    68 #define SDRC_CR                                 0x08            // Configuration Register
    69 #define SDRC_SRR                                0x0C            // Self Refresh Register
    70 #define SDRC_LPR                                0x10            // Low Power Register
    71 #define SDRC_IER                                0x14            // Interrupt Enable Register
    72 #define SDRC_IDR                                0x18            // Interrupt Disable Register
    73 #define SDRC_IMR                                0x1C            // Interrupt Mask Register
    74 #define SDRC_ISR                                0x20            // Interrupt Status Register
     63/* ***************************************************************************** */
     64/* SDRAM Memory Interface Unit */
     65/* ***************************************************************************** */
     66#define SDRC_MR             0x00       /* Mode Register */
     67#define SDRC_TR             0x04       /* Refresh Timer Register */
     68#define SDRC_CR             0x08       /* Configuration Register */
     69#define SDRC_SRR            0x0C       /* Self Refresh Register */
     70#define SDRC_LPR            0x10       /* Low Power Register */
     71#define SDRC_IER            0x14       /* Interrupt Enable Register */
     72#define SDRC_IDR            0x18       /* Interrupt Disable Register */
     73#define SDRC_IMR            0x1C       /* Interrupt Mask Register */
     74#define SDRC_ISR            0x20       /* Interrupt Status Register */
    7575
    76 // Bit Defines
    77 // SDRC_MR - Mode Register
    78 #define SDRC_MR_DBW_16                  BIT4            // 1 = SDRAM is 16-bits wide, 0 = 32-bits
    79 #define SDRC_MR_NORM                    (0 << 0)        // Normal Mode - All accesses to SDRAM are decoded normally
    80 #define SDRC_MR_NOP                             (1 << 0)        // NOP Command is sent to SDRAM
    81 #define SDRC_MR_PRE                             (2 << 0)        // Precharge All Command is sent to SDRAM
    82 #define SDRC_MR_MRS                             (3 << 0)        // Mode Register Set Command is sent to SDRAM
    83 #define SDRC_MR_REF                             (4 << 0)        // Refresh Command is sent to SDRAM
     76/* Bit Defines */
     77/* SDRC_MR - Mode Register */
     78#define SDRC_MR_DBW_16        BIT4       /* 1 = SDRAM is 16-bits wide, 0 = 32-bits */
     79#define SDRC_MR_NORM          (0 << 0)   /* Normal Mode - All accesses to SDRAM are decoded normally */
     80#define SDRC_MR_NOP         (1 << 0)   /* NOP Command is sent to SDRAM */
     81#define SDRC_MR_PRE         (2 << 0)   /* Precharge All Command is sent to SDRAM */
     82#define SDRC_MR_MRS         (3 << 0)   /* Mode Register Set Command is sent to SDRAM */
     83#define SDRC_MR_REF         (4 << 0)   /* Refresh Command is sent to SDRAM */
    8484
    85 // SDRC_TR - Refresh Timer Register
    86 #define SDRC_TR_COUNT(_x_)              ((_x_ & 0xfff) << 0)
     85/* SDRC_TR - Refresh Timer Register */
     86#define SDRC_TR_COUNT(_x_)    ((_x_ & 0xfff) << 0)
    8787
    88 // SDRC_CR - Configuration Register
    89 #define SDRC_CR_TXSR(_x_)               ((_x_ & 0xf) << 27)     // CKE to ACT Time
    90 #define SDRC_CR_TRAS(_x_)               ((_x_ & 0xf) << 23)     // ACT to PRE Time
    91 #define SDRC_CR_TRCD(_x_)               ((_x_ & 0xf) << 19)     // RAS to CAS Time
    92 #define SDRC_CR_TRP(_x_)                ((_x_ & 0xf) << 15)     // PRE to ACT Time
    93 #define SDRC_CR_TRC(_x_)                ((_x_ & 0xf) << 11)     // REF to ACT Time
    94 #define SDRC_CR_TWR(_x_)                ((_x_ & 0xf) << 7)      // Write Recovery Time
    95 #define SDRC_CR_CAS_2                   (2 << 5)        // Cas Delay = 2, this is the only supported value
    96 #define SDRC_CR_NB_2                    0                       // 2 Banks per device
    97 #define SDRC_CR_NB_4                    BIT4            // 4 Banks per device
    98 #define SDRC_CR_NR_11                   (0 << 2)        // Number of rows = 11
    99 #define SDRC_CR_NR_12                   (1 << 2)        // Number of rows = 12
    100 #define SDRC_CR_NR_13                   (2 << 2)        // Number of rows = 13
    101 #define SDRC_CR_NC_8                    (0 << 0)        // Number of columns = 8
    102 #define SDRC_CR_NC_9                    (1 << 0)        // Number of columns = 9
    103 #define SDRC_CR_NC_10                   (2 << 0)        // Number of columns = 10
    104 #define SDRC_CR_NC_11                   (3 << 0)        // Number of columns = 11
     88/* SDRC_CR - Configuration Register */
     89#define SDRC_CR_TXSR(_x_)     ((_x_ & 0xf) << 27)     /* CKE to ACT Time */
     90#define SDRC_CR_TRAS(_x_)     ((_x_ & 0xf) << 23)     /* ACT to PRE Time */
     91#define SDRC_CR_TRCD(_x_)     ((_x_ & 0xf) << 19)     /* RAS to CAS Time */
     92#define SDRC_CR_TRP(_x_)      ((_x_ & 0xf) << 15)     /* PRE to ACT Time */
     93#define SDRC_CR_TRC(_x_)      ((_x_ & 0xf) << 11)     /* REF to ACT Time */
     94#define SDRC_CR_TWR(_x_)      ((_x_ & 0xf) << 7)      /* Write Recovery Time */
     95#define SDRC_CR_CAS_2         (2 << 5)   /* Cas Delay = 2, this is the only supported value */
     96#define SDRC_CR_NB_2          0        /* 2 Banks per device */
     97#define SDRC_CR_NB_4          BIT4       /* 4 Banks per device */
     98#define SDRC_CR_NR_11         (0 << 2)   /* Number of rows = 11 */
     99#define SDRC_CR_NR_12         (1 << 2)   /* Number of rows = 12 */
     100#define SDRC_CR_NR_13         (2 << 2)   /* Number of rows = 13 */
     101#define SDRC_CR_NC_8          (0 << 0)   /* Number of columns = 8 */
     102#define SDRC_CR_NC_9          (1 << 0)   /* Number of columns = 9 */
     103#define SDRC_CR_NC_10         (2 << 0)   /* Number of columns = 10 */
     104#define SDRC_CR_NC_11         (3 << 0)   /* Number of columns = 11 */
    105105
    106 // SDRC_SRR - Self Refresh Register
    107 #define SDRC_SRR_SRCB                   BIT0            // 1 = Enter Self Refresh
     106/* SDRC_SRR - Self Refresh Register */
     107#define SDRC_SRR_SRCB         BIT0       /* 1 = Enter Self Refresh */
    108108
    109 // SDRC_LPR - Low Power Register
    110 #define SDRC_LPR_LPCB                   BIT0            // 1 = De-assert CKE between accesses
     109/* SDRC_LPR - Low Power Register */
     110#define SDRC_LPR_LPCB         BIT0       /* 1 = De-assert CKE between accesses */
    111111
    112 // SDRC_IER - Interrupt Enable Register
    113 // SDRC_IDR - Interrupt Disable Register
    114 // SDRC_ISR - Interrupt Mask Register
    115 // SDRC_IMR - Interrupt Mask Register
    116 #define SDRC_INT_RES                    BIT0            // Refresh Error Status
     112/* SDRC_IER - Interrupt Enable Register */
     113/* SDRC_IDR - Interrupt Disable Register */
     114/* SDRC_ISR - Interrupt Mask Register */
     115/* SDRC_IMR - Interrupt Mask Register */
     116#define SDRC_INT_RES          BIT0       /* Refresh Error Status */
    117117
    118118#endif
  • c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_pmc.h

    rea1d598 r5e14d89  
    1717#include <bits.h>
    1818
    19 // *****************************************************************************
    20 // Power Management and Clock Control Register Offsets
    21 // *****************************************************************************
     19/***********************************************************************
     20 *      Power Management and Clock Control Register Offsets
     21 ***********************************************************************/
    2222int at91rm9200_get_mainclk(void);
    2323int at91rm9200_get_slck(void);
     
    2525
    2626
    27 #define PMC_SCER        0x00    // System Clock Enable Register
    28 #define PMC_SCDR        0x04    // System Clock Disable Register
    29 #define PMC_SCSR        0x08    // System Clock Status Register
    30 #define PMC_PCER        0x10    // Peripheral Clock Enable Register
    31 #define PMC_PCDR        0x14    // Peripheral Clock Disable Register
    32 #define PMC_PCSR        0x18    // Peripheral Clock Status Register
    33 #define PMC_MOR         0x20    // Main Oscillator Register
    34 #define PMC_MCFR        0x24    // Main Clock  Frequency Register
    35 #define PMC_PLLAR       0x28    // PLL A Register
    36 #define PMC_PLLBR       0x2C    // PLL B Register
    37 #define PMC_MCKR        0x30    // Master Clock Register
    38 #define PMC_PCKR0       0x40    // Programmable Clock Register 0
    39 #define PMC_PCKR1       0x44    // Programmable Clock Register 1
    40 #define PMC_PCKR2       0x48    // Programmable Clock Register 2
    41 #define PMC_PCKR3       0x4C    // Programmable Clock Register 3
    42 #define PMC_PCKR4       0x50    // Programmable Clock Register 4
    43 #define PMC_PCKR5       0x54    // Programmable Clock Register 5
    44 #define PMC_PCKR6       0x58    // Programmable Clock Register 6
    45 #define PMC_PCKR7       0x5C    // Programmable Clock Register 7
    46 #define PMC_IER         0x60    // Interrupt Enable Register
    47 #define PMC_IDR         0x64    // Interrupt Disable Register
    48 #define PMC_SR          0x68    // Status Register
    49 #define PMC_IMR         0x6C    // Interrupt Mask Register
     27#define PMC_SCER  0x00    /* System Clock Enable Register */
     28#define PMC_SCDR  0x04    /* System Clock Disable Register */
     29#define PMC_SCSR  0x08    /* System Clock Status Register */
     30#define PMC_PCER  0x10    /* Peripheral Clock Enable Register */
     31#define PMC_PCDR  0x14    /* Peripheral Clock Disable Register */
     32#define PMC_PCSR  0x18    /* Peripheral Clock Status Register */
     33#define PMC_MOR   0x20    /* Main Oscillator Register */
     34#define PMC_MCFR  0x24    /* Main Clock  Frequency Register */
     35#define PMC_PLLAR       0x28    /* PLL A Register */
     36#define PMC_PLLBR       0x2C    /* PLL B Register */
     37#define PMC_MCKR  0x30    /* Master Clock Register */
     38#define PMC_PCKR0       0x40    /* Programmable Clock Register 0 */
     39#define PMC_PCKR1       0x44    /* Programmable Clock Register 1 */
     40#define PMC_PCKR2       0x48    /* Programmable Clock Register 2 */
     41#define PMC_PCKR3       0x4C    /* Programmable Clock Register 3 */
     42#define PMC_PCKR4       0x50    /* Programmable Clock Register 4 */
     43#define PMC_PCKR5       0x54    /* Programmable Clock Register 5 */
     44#define PMC_PCKR6       0x58    /* Programmable Clock Register 6 */
     45#define PMC_PCKR7       0x5C    /* Programmable Clock Register 7 */
     46#define PMC_IER   0x60    /* Interrupt Enable Register */
     47#define PMC_IDR   0x64    /* Interrupt Disable Register */
     48#define PMC_SR    0x68    /* Status Register */
     49#define PMC_IMR   0x6C    /* Interrupt Mask Register */
    5050
    51 // Bit Defines
     51/* Bit Defines */
    5252
    53 // PMC_SCDR - System Clock Disable Register
    54 // PMC_SCSR - System Clock Status Register
    55 // PMC_SCER - System Clock Enable Register
    56 #define PMC_SCR_PCK7                    BIT15
    57 #define PMC_SCR_PCK6                    BIT14
    58 #define PMC_SCR_PCK5                    BIT13
    59 #define PMC_SCR_PCK4                    BIT12
    60 #define PMC_SCR_PCK3                    BIT11
    61 #define PMC_SCR_PCK2                    BIT10
    62 #define PMC_SCR_PCK1                    BIT9
    63 #define PMC_SCR_PCK0                    BIT8
    64 #define PMC_SCR_UHP                             BIT4
    65 #define PMC_SCR_MCKUDP                  BIT2
    66 #define PMC_SCR_UDP                     BIT1
    67 #define PMC_SCR_PCK                     BIT0
     53/* PMC_SCDR - System Clock Disable Register */
     54/* PMC_SCSR - System Clock Status Register */
     55/* PMC_SCER - System Clock Enable Register */
     56#define PMC_SCR_PCK7        BIT15
     57#define PMC_SCR_PCK6        BIT14
     58#define PMC_SCR_PCK5        BIT13
     59#define PMC_SCR_PCK4        BIT12
     60#define PMC_SCR_PCK3        BIT11
     61#define PMC_SCR_PCK2        BIT10
     62#define PMC_SCR_PCK1        BIT9
     63#define PMC_SCR_PCK0        BIT8
     64#define PMC_SCR_UHP           BIT4
     65#define PMC_SCR_MCKUDP      BIT2
     66#define PMC_SCR_UDP         BIT1
     67#define PMC_SCR_PCK         BIT0
    6868
    69 // PMC_PCER - Peripheral Clock Enable Register
    70 // PMC_PCDR - Peripheral Clock Disable Register
    71 // PMC_PCSR - Peripheral Clock Status Register
    72 #define PMC_PCR_PID_EMAC                BIT24           // Ethernet Peripheral Clock
    73 #define PMC_PCR_PID_UHP                 BIT23           // USB Host Ports Peripheral Clock
    74 #define PMC_PCR_PID_TC5                 BIT22           // Timer/Counter 5 Peripheral Clock
    75 #define PMC_PCR_PID_TC4                 BIT21           // Timer/Counter 4 Peripheral Clock
    76 #define PMC_PCR_PID_TC3                 BIT20           // Timer/Counter 3 Peripheral Clock
    77 #define PMC_PCR_PID_TC2                 BIT19           // Timer/Counter 2 Peripheral Clock
    78 #define PMC_PCR_PID_TC1                 BIT18           // Timer/Counter 1 Peripheral Clock
    79 #define PMC_PCR_PID_TC0                 BIT17           // Timer/Counter 0 Peripheral Clock
    80 #define PMC_PCR_PID_SSC2                BIT16           // Synchronous Serial 2 Peripheral Clock
    81 #define PMC_PCR_PID_SSC1                BIT15           // Synchronous Serial 1 Peripheral Clock
    82 #define PMC_PCR_PID_SSC0                BIT14           // Synchronous Serial 0 Peripheral Clock
    83 #define PMC_PCR_PID_SPI                 BIT13           // Serial Peripheral Interface Peripheral Clock
    84 #define PMC_PCR_PID_TWI                 BIT12           // Two-Wire Interface Peripheral Clock
    85 #define PMC_PCR_PID_UDP                 BIT11           // USB Device Port Peripheral Clock
    86 #define PMC_PCR_PID_MCI                 BIT10           // MMC/SD Card Peripheral Clock
    87 #define PMC_PCR_PID_US3                 BIT9            // USART 3 Peripheral Clock
    88 #define PMC_PCR_PID_US2                 BIT8            // USART 2 Peripheral Clock
    89 #define PMC_PCR_PID_US1                 BIT7            // USART 1 Peripheral Clock
    90 #define PMC_PCR_PID_US0                 BIT6            // USART 0 Peripheral Clock
    91 #define PMC_PCR_PID_PIOD                BIT5            // Parallel I/O D Peripheral Clock
    92 #define PMC_PCR_PID_PIOC                BIT4            // Parallel I/O C Peripheral Clock
    93 #define PMC_PCR_PID_PIOB                BIT3            // Parallel I/O B Peripheral Clock
    94 #define PMC_PCR_PID_PIOA                BIT2            // Parallel I/O A Peripheral Clock
     69/* PMC_PCER - Peripheral Clock Enable Register */
     70/* PMC_PCDR - Peripheral Clock Disable Register */
     71/* PMC_PCSR - Peripheral Clock Status Register */
     72#define PMC_PCR_PID_EMAC    BIT24     /* Ethernet Peripheral Clock */
     73#define PMC_PCR_PID_UHP     BIT23     /* USB Host Ports Peripheral Clock */
     74#define PMC_PCR_PID_TC5     BIT22     /* Timer/Counter 5 Peripheral Clock */
     75#define PMC_PCR_PID_TC4     BIT21     /* Timer/Counter 4 Peripheral Clock */
     76#define PMC_PCR_PID_TC3     BIT20     /* Timer/Counter 3 Peripheral Clock */
     77#define PMC_PCR_PID_TC2     BIT19     /* Timer/Counter 2 Peripheral Clock */
     78#define PMC_PCR_PID_TC1     BIT18     /* Timer/Counter 1 Peripheral Clock */
     79#define PMC_PCR_PID_TC0     BIT17     /* Timer/Counter 0 Peripheral Clock */
     80#define PMC_PCR_PID_SSC2    BIT16     /* Synchronous Serial 2 Peripheral Clock */
     81#define PMC_PCR_PID_SSC1    BIT15     /* Synchronous Serial 1 Peripheral Clock */
     82#define PMC_PCR_PID_SSC0    BIT14     /* Synchronous Serial 0 Peripheral Clock */
     83#define PMC_PCR_PID_SPI     BIT13     /* Serial Peripheral Interface Peripheral Clock */
     84#define PMC_PCR_PID_TWI     BIT12     /* Two-Wire Interface Peripheral Clock */
     85#define PMC_PCR_PID_UDP     BIT11     /* USB Device Port Peripheral Clock */
     86#define PMC_PCR_PID_MCI     BIT10     /* MMC/SD Card Peripheral Clock */
     87#define PMC_PCR_PID_US3     BIT9      /* USART 3 Peripheral Clock */
     88#define PMC_PCR_PID_US2     BIT8      /* USART 2 Peripheral Clock */
     89#define PMC_PCR_PID_US1     BIT7      /* USART 1 Peripheral Clock */
     90#define PMC_PCR_PID_US0     BIT6      /* USART 0 Peripheral Clock */
     91#define PMC_PCR_PID_PIOD    BIT5      /* Parallel I/O D Peripheral Clock */
     92#define PMC_PCR_PID_PIOC    BIT4      /* Parallel I/O C Peripheral Clock */
     93#define PMC_PCR_PID_PIOB    BIT3      /* Parallel I/O B Peripheral Clock */
     94#define PMC_PCR_PID_PIOA    BIT2      /* Parallel I/O A Peripheral Clock */
    9595
    96 // PMC_MOR - Main Oscillator Register
    97 #define PMC_MOR_MOSCEN                  BIT0
     96/* PMC_MOR - Main Oscillator Register */
     97#define PMC_MOR_MOSCEN      BIT0
    9898
    99 // PMC_MCFR - Main Clock  Frequency Register
    100 #define PMC_MCFR_MAINRDY                BIT16
     99/* PMC_MCFR - Main Clock  Frequency Register */
     100#define PMC_MCFR_MAINRDY    BIT16
    101101
    102 // PMC_PLLAR - PLL A Register
    103 #define PMC_PLLAR_MUST_SET              BIT29                                   // This bit must be set according to the docs
    104 #define PMC_PLLAR_MUL(_x_)              ((_x_ & 0x7ff) << 16)   // Multiplier   
    105 #define PMC_PLLAR_MUL_MASK              (0x7ff << 16)   // Multiplier mask
     102/* PMC_PLLAR - PLL A Register */
     103#define PMC_PLLAR_MUST_SET        BIT29           /* This bit must be set according to the docs */
     104#define PMC_PLLAR_MUL(_x_)        ((_x_ & 0x7ff) << 16)   /* Multiplier    */
     105#define PMC_PLLAR_MUL_MASK        (0x7ff << 16)   /* Multiplier mask */
    106106
    107 #define PMC_PLLAR_OUT_80_160    (0 << 14)                               // select when PLL frequency is 80-160 Mhz
    108 #define PMC_PLLAR_OUT_150_240   (2 << 14)                               // select when PLL frequency is 150-240 Mhz
    109 #define PMC_PLLAR_DIV(_x_)              ((_x_ & 0xff) << 0)             // Divider
    110 #define PMC_PLLAR_DIV_MASK              (0xff)          // Divider mask
     107#define PMC_PLLAR_OUT_80_160    (0 << 14)             /* select when PLL frequency is 80-160 Mhz */
     108#define PMC_PLLAR_OUT_150_240   (2 << 14)             /* select when PLL frequency is 150-240 Mhz */
     109#define PMC_PLLAR_DIV(_x_)        ((_x_ & 0xff) << 0)       /* Divider */
     110#define PMC_PLLAR_DIV_MASK        (0xff)    /* Divider mask */
    111111
    112 // PMC_PLLBR - PLL B Register
    113 #define PMC_PLLBR_USB_96M               BIT28                                   // Set when PLL is 96Mhz to divide it by 2 for USB
    114 #define PMC_PLLBR_MUL(_x_)              ((_x_ & 0x7ff) << 16)   // Multiplier   
    115 #define PMC_PLLBR_MUL_MASK              (0x7ff << 16)   // Multiplier mask
    116 #define PMC_PLLBR_OUT_80_160    (0 << 14)                               // select when PLL frequency is 80-160 Mhz
    117 #define PMC_PLLBR_OUT_150_240   (2 << 14)                               // select when PLL frequency is 150-240 Mhz
    118 #define PMC_PLLBR_DIV(_x_)              ((_x_ & 0xff) << 0)             // Divider
    119 #define PMC_PLLBR_DIV_MASK              (0xff)          // Divider mask
     112/* PMC_PLLBR - PLL B Register */
     113#define PMC_PLLBR_USB_96M         BIT28           /* Set when PLL is 96Mhz to divide it by 2 for USB */
     114#define PMC_PLLBR_MUL(_x_)        ((_x_ & 0x7ff) << 16)   /* Multiplier    */
     115#define PMC_PLLBR_MUL_MASK      (0x7ff << 16)   /* Multiplier mask */
     116#define PMC_PLLBR_OUT_80_160    (0 << 14)         /* select when PLL frequency is 80-160 Mhz */
     117#define PMC_PLLBR_OUT_150_240   (2 << 14)        /* select when PLL frequency is 150-240 Mhz */
     118#define PMC_PLLBR_DIV(_x_)      ((_x_ & 0xff) << 0)       /* Divider */
     119#define PMC_PLLBR_DIV_MASK      (0xff)    /* Divider mask */
    120120
    121 // PMC_MCKR - Master Clock Register
    122 #define PMC_MCKR_MDIV_MASK              (3 << 8)                                // for masking out the MDIV field
    123 #define PMC_MCKR_MDIV_1                 (0 << 8)                                // MCK = Core/1
    124 #define PMC_MCKR_MDIV_2                 (1 << 8)                                // MCK = Core/2
    125 #define PMC_MCKR_MDIV_3                 (2 << 8)                                // MCK = Core/3
    126 #define PMC_MCKR_MDIV_4                 (3 << 8)                                // MCK = Core/4
    127 #define PMC_MCKR_PRES_MASK              (7 << 2)                                // for masking out the PRES field
    128 #define PMC_MCKR_PRES_1                 (0 << 2)                                // Core = CSS/1
    129 #define PMC_MCKR_PRES_2                 (1 << 2)                                // Core = CSS/2
    130 #define PMC_MCKR_PRES_4                 (2 << 2)                                // Core = CSS/4
    131 #define PMC_MCKR_PRES_8                 (3 << 2)                                // Core = CSS/8
    132 #define PMC_MCKR_PRES_16                (4 << 2)                                // Core = CSS/16
    133 #define PMC_MCKR_PRES_32                (5 << 2)                                // Core = CSS/32
    134 #define PMC_MCKR_PRES_64                (6 << 2)                                // Core = CSS/64
    135 #define PMC_MCKR_CSS_MASK               (3 << 0)                                // for masking out the CSS field
    136 #define PMC_MCKR_CSS_SLOW               (0 << 0)                                // Core Source = Slow Clock
    137 #define PMC_MCKR_CSS_MAIN               (1 << 0)                                // Core Source = Main Oscillator
    138 #define PMC_MCKR_CSS_PLLA               (2 << 0)                                // Core Source = PLL A
    139 #define PMC_MCKR_CSS_PLLB               (3 << 0)                                // Core Source = PLL B
     121/* PMC_MCKR - Master Clock Register */
     122#define PMC_MCKR_MDIV_MASK      (3 << 8)        /* for masking out the MDIV field */
     123#define PMC_MCKR_MDIV_1     (0 << 8)        /* MCK = Core/1 */
     124#define PMC_MCKR_MDIV_2     (1 << 8)        /* MCK = Core/2 */
     125#define PMC_MCKR_MDIV_3     (2 << 8)        /* MCK = Core/3 */
     126#define PMC_MCKR_MDIV_4     (3 << 8)        /* MCK = Core/4 */
     127#define PMC_MCKR_PRES_MASK        (7 << 2)        /* for masking out the PRES field */
     128#define PMC_MCKR_PRES_1     (0 << 2)        /* Core = CSS/1 */
     129#define PMC_MCKR_PRES_2     (1 << 2)        /* Core = CSS/2 */
     130#define PMC_MCKR_PRES_4     (2 << 2)        /* Core = CSS/4 */
     131#define PMC_MCKR_PRES_8     (3 << 2)        /* Core = CSS/8 */
     132#define PMC_MCKR_PRES_16    (4 << 2)        /* Core = CSS/16 */
     133#define PMC_MCKR_PRES_32    (5 << 2)        /* Core = CSS/32 */
     134#define PMC_MCKR_PRES_64    (6 << 2)        /* Core = CSS/64 */
     135#define PMC_MCKR_CSS_MASK         (3 << 0)        /* for masking out the CSS field */
     136#define PMC_MCKR_CSS_SLOW         (0 << 0)        /* Core Source = Slow Clock */
     137#define PMC_MCKR_CSS_MAIN         (1 << 0)        /* Core Source = Main Oscillator */
     138#define PMC_MCKR_CSS_PLLA         (2 << 0)        /* Core Source = PLL A */
     139#define PMC_MCKR_CSS_PLLB         (3 << 0)        /* Core Source = PLL B */
    140140
    141 // PMC_PCKR0 - 7 - Programmable Clock Register 0
    142 #define PMC_PCKR_PRES_1                 (0 << 2)                                // Peripheral Clock = CSS/1
    143 #define PMC_PCKR_PRES_2                 (1 << 2)                                // Peripheral Clock = CSS/2
    144 #define PMC_PCKR_PRES_4                 (2 << 2)                                // Peripheral Clock = CSS/4
    145 #define PMC_PCKR_PRES_8                 (3 << 2)                                // Peripheral Clock = CSS/8
    146 #define PMC_PCKR_PRES_16                (4 << 2)                                // Peripheral Clock = CSS/16
    147 #define PMC_PCKR_PRES_32                (5 << 2)                                // Peripheral Clock = CSS/32
    148 #define PMC_PCKR_PRES_64                (6 << 2)                                // Peripheral Clock = CSS/64
    149 #define PMC_PCKR_CSS_SLOW               (0 << 0)                                // Peripheral Clock Source = Slow Clock
    150 #define PMC_PCKR_CSS_MAIN               (1 << 0)                                // Peripheral Clock Source = Main Oscillator
    151 #define PMC_PCKR_CSS_PLLA               (2 << 0)                                // Peripheral Clock Source = PLL A
    152 #define PMC_PCKR_CSS_PLLB               (3 << 0)                                // Peripheral Clock Source = PLL B
     141/* PMC_PCKR0 - 7 - Programmable Clock Register 0 */
     142#define PMC_PCKR_PRES_1     (0 << 2)        /* Peripheral Clock = CSS/1 */
     143#define PMC_PCKR_PRES_2     (1 << 2)        /* Peripheral Clock = CSS/2 */
     144#define PMC_PCKR_PRES_4     (2 << 2)        /* Peripheral Clock = CSS/4 */
     145#define PMC_PCKR_PRES_8     (3 << 2)        /* Peripheral Clock = CSS/8 */
     146#define PMC_PCKR_PRES_16    (4 << 2)        /* Peripheral Clock = CSS/16 */
     147#define PMC_PCKR_PRES_32    (5 << 2)        /* Peripheral Clock = CSS/32 */
     148#define PMC_PCKR_PRES_64    (6 << 2)        /* Peripheral Clock = CSS/64 */
     149#define PMC_PCKR_CSS_SLOW         (0 << 0)        /* Peripheral Clock Source = Slow Clock */
     150#define PMC_PCKR_CSS_MAIN         (1 << 0)        /* Peripheral Clock Source = Main Oscillator */
     151#define PMC_PCKR_CSS_PLLA         (2 << 0)        /* Peripheral Clock Source = PLL A */
     152#define PMC_PCKR_CSS_PLLB         (3 << 0)        /* Peripheral Clock Source = PLL B */
    153153
    154 // PMC_IER - Interrupt Enable Register
    155 // PMC_IDR - Interrupt Disable Register
    156 // PMC_SR - Status Register
    157 // PMC_IMR - Interrupt Mask Register
    158 #define PMC_INT_PCK7_RDY                BIT15
    159 #define PMC_INT_PCK6_RDY                BIT14
    160 #define PMC_INT_PCK5_RDY                BIT13
    161 #define PMC_INT_PCK4_RDY                BIT12
    162 #define PMC_INT_PCK3_RDY                BIT11
    163 #define PMC_INT_PCK2_RDY                BIT10
    164 #define PMC_INT_PCK1_RDY                BIT9
    165 #define PMC_INT_PCK0_RDY                BIT8
    166 #define PMC_INT_MCK_RDY                 BIT3
    167 #define PMC_INT_LOCKB                   BIT2
    168 #define PMC_INT_LCKA                    BIT1
    169 #define PMC_INT_MOSCS                   BIT0
     154/* PMC_IER - Interrupt Enable Register */
     155/* PMC_IDR - Interrupt Disable Register */
     156/* PMC_SR - Status Register */
     157/* PMC_IMR - Interrupt Mask Register */
     158#define PMC_INT_PCK7_RDY    BIT15
     159#define PMC_INT_PCK6_RDY    BIT14
     160#define PMC_INT_PCK5_RDY    BIT13
     161#define PMC_INT_PCK4_RDY    BIT12
     162#define PMC_INT_PCK3_RDY    BIT11
     163#define PMC_INT_PCK2_RDY    BIT10
     164#define PMC_INT_PCK1_RDY    BIT9
     165#define PMC_INT_PCK0_RDY    BIT8
     166#define PMC_INT_MCK_RDY     BIT3
     167#define PMC_INT_LOCKB       BIT2
     168#define PMC_INT_LCKA        BIT1
     169#define PMC_INT_MOSCS       BIT0
    170170
    171171
  • c/src/lib/libcpu/arm/s3c2400/include/s3c2400.h

    rea1d598 r5e14d89  
    428428/* Wait until rINTPND is changed for the case that the ISR is very short. */
    429429
    430 //////////////////////////////////////////////////////////////////////////////
    431 // Typedefs                                                                 //
    432 //////////////////////////////////////////////////////////////////////////////
    433 typedef union {
    434         struct _reg {
    435                 unsigned STOP_BIT:1;    // Enters STOP mode. This bit isn't be cleared automatically.
    436                 unsigned SL_IDLE:1;             // SL_IDLE mode option. This bit isn't be cleared automatically. To enter SL_IDLE mode, CLKCON register has to be 0xe.
    437                 unsigned IDLE_BIT:1;    // Enters IDLE mode. This bit isn't be cleared automatically.
    438                 unsigned LCDC:1;                // Controls HCLK into LCDC block
    439                 unsigned USB_host:1;    // Controls HCLK into USB host block
    440                 unsigned USB_device:1;  // Controls PCLK into USB device block
    441                 unsigned PWMTIMER:1;    // Controls PCLK into PWMTIMER block
    442                 unsigned MMC:1;                 // Controls PCLK into MMC interface block
    443                 unsigned UART0:1;               // Controls PCLK into UART0 block
    444                 unsigned UART1:1;               // Controls PCLK into UART1 block
    445                 unsigned GPIO:1;                // Controls PCLK into GPIO block
    446                 unsigned RTC:1;                 // Controls PCLK into RTC control block. Even if this bit is cleared to 0, RTC timer is alive.
    447                 unsigned ADC:1;                 // Controls PCLK into ADC block
    448                 unsigned IIC:1;                 // Controls PCLK into IIC block
    449                 unsigned IIS:1;                 // Controls PCLK into IIS block
    450                 unsigned SPI:1;                 // Controls PCLK into SPI block
    451         } reg;
    452         unsigned long all;
     430/* Typedefs */
     431typedef union {
     432  struct _reg {
     433    unsigned STOP_BIT:1;   /* Enters STOP mode. This bit isn't be */
     434                           /*    cleared automatically. */
     435    unsigned SL_IDLE:1;    /* SL_IDLE mode option. This bit isn't cleared */
     436                           /*    automatically. To enter SL_IDLE mode, */
     437                           /* CLKCON register has to be 0xe. */
     438    unsigned IDLE_BIT:1;   /* Enters IDLE mode. This bit isn't be cleared */
     439                           /*    automatically. */
     440    unsigned LCDC:1;       /* Controls HCLK into LCDC block */
     441    unsigned USB_host:1;   /* Controls HCLK into USB host block */
     442    unsigned USB_device:1; /* Controls PCLK into USB device block */
     443    unsigned PWMTIMER:1;   /* Controls PCLK into PWMTIMER block */
     444    unsigned MMC:1;        /* Controls PCLK into MMC interface block */
     445    unsigned UART0:1;      /* Controls PCLK into UART0 block */
     446    unsigned UART1:1;      /* Controls PCLK into UART1 block */
     447    unsigned GPIO:1;       /* Controls PCLK into GPIO block */
     448    unsigned RTC:1;        /* Controls PCLK into RTC control block. Even if */
     449                           /*   this bit is cleared to 0, RTC timer is alive. */
     450    unsigned ADC:1;        /* Controls PCLK into ADC block */
     451    unsigned IIC:1;        /* Controls PCLK into IIC block */
     452    unsigned IIS:1;        /* Controls PCLK into IIS block */
     453    unsigned SPI:1;        /* Controls PCLK into SPI block */
     454  } reg;
     455  unsigned long all;
    453456} CLKCON;
    454457
    455458typedef union
    456459{
    457         struct {
    458                 unsigned ENVID:1;               // LCD video output and the logic 1=enable/0=disable.
    459                 unsigned BPPMODE:4;             // 1011 = 8 bpp for TFT, 1100 = 16 bpp for TFT, 1110 = 16 bpp TFT skipmode
    460                 unsigned PNRMODE:2;             // TFT: 3
    461                 unsigned MMODE:1;               // This bit determines the toggle rate of the VM. 0 = Each Frame, 1 = The rate defined by the MVAL
    462                 unsigned CLKVAL:10;             // TFT: VCLK = HCLK / [(CLKVAL+1) x 2] (CLKVAL >= 1)
    463                 unsigned LINECNT:10;    // (read only) These bits provide the status of the line counter. Down count from LINEVAL to 0
    464         } reg;
    465         unsigned long all;
     460  struct {
     461    unsigned ENVID:1;    /* LCD video output and the logic 1=enable/0=disable. */
     462    unsigned BPPMODE:4;  /* 1011 = 8 bpp for TFT, 1100 = 16 bpp for TFT, */
     463                         /*   1110 = 16 bpp TFT skipmode */
     464    unsigned PNRMODE:2;  /* TFT: 3 */
     465    unsigned MMODE:1;    /* This bit determines the toggle rate of the VM. */
     466                         /*   0 = Each Frame, 1 = The rate defined by the MVAL */
     467    unsigned CLKVAL:10;  /* TFT: VCLK = HCLK / [(CLKVAL+1) x 2] (CLKVAL >= 1) */
     468    unsigned LINECNT:10; /* (read only) These bits provide the status of the */
     469                         /*   line counter. Down count from LINEVAL to 0 */
     470  } reg;
     471  unsigned long all;
    466472} LCDCON1;
    467473
    468474typedef union {
    469         struct {
    470                 unsigned VSPW:6;                // TFT: Vertical sync pulse width determines the VSYNC pulse's high level width by counting the number of inactive lines.
    471                 unsigned VFPD:8;                // TFT: Vertical front porch is the number of inactive lines at the end of a frame, before vertical synchronization period.
    472                 unsigned LINEVAL:10;    // TFT/STN: These bits determine the vertical size of LCD panel.
    473                 unsigned VBPD:8;                // TFT: Vertical back porch is the number of inactive lines at the start of a frame, after vertical synchronization period.
    474         } reg;
    475         unsigned long all;
     475  struct {
     476    unsigned VSPW:6;    /* TFT: Vertical sync pulse width determines the */
     477                        /*   VSYNC pulse's high level width by counting the */
     478                        /*   number of inactive lines. */
     479    unsigned VFPD:8;    /* TFT: Vertical front porch is the number of */
     480                        /*   inactive lines at the end of a frame, before */
     481                        /*   vertical synchronization period. */
     482    unsigned LINEVAL:10;  /* TFT/STN: These bits determine the vertical size */
     483                        /*   of LCD panel. */
     484    unsigned VBPD:8;    /* TFT: Vertical back porch is the number of inactive */
     485                        /*   lines at the start of a frame, after */
     486                        /*   vertical synchronization period. */
     487  } reg;
     488  unsigned long all;
    476489} LCDCON2;
    477490
    478491typedef union {
    479         struct {
    480                 unsigned HFPD:8;                // TFT: Horizontal front porch is the number of VCLK periods between the end of active data and the rising edge of HSYNC.
    481                 unsigned HOZVAL:11;             // TFT/STN: These bits determine the horizontal size of LCD panel. 2n bytes.
    482                 unsigned HBPD:7;                // TFT: Horizontal back porch is the number of VCLK periods between the falling edge of HSYNC and the start of active data.
    483         } reg;
    484         unsigned long all;
     492  struct {
     493    unsigned HFPD:8;    /* TFT: Horizontal front porch is the number of */
     494                        /*   VCLK periods between the end of active data */
     495                        /*   and the rising edge of HSYNC. */
     496    unsigned HOZVAL:11; /* TFT/STN: These bits determine the horizontal */
     497                        /*   size of LCD panel. 2n bytes. */
     498    unsigned HBPD:7;    /* TFT: Horizontal back porch is the number of VCLK */
     499                        /*   periods between the falling edge of HSYNC and */
     500                        /*   the start of active data. */
     501  } reg;
     502  unsigned long all;
    485503} LCDCON3;
    486504
    487505typedef union {
    488         struct {
    489                 unsigned HSPW:8;                // TFT: Horizontal sync pulse width determines the HSYNC pulse's high level width by counting the number of the VCLK.
    490                 unsigned MVAL:8;                // STN:
    491                 unsigned ADDVAL:8;              // TFT: Palette Index offset value
    492                 unsigned PALADDEN:1;    // TFT: Palette Index offset enable. 0 = Disable 1 = Enable
    493         } reg;
    494         unsigned long all;
     506  struct {
     507    unsigned HSPW:8;     /* TFT: Horizontal sync pulse width determines the */
     508                         /*   HSYNC pulse's high level width by counting the */
     509                         /*   number of the VCLK. */
     510    unsigned MVAL:8;     /* STN: */
     511    unsigned ADDVAL:8;   /* TFT: Palette Index offset value */
     512    unsigned PALADDEN:1; /* TFT: Palette Index offset enable. */
     513                         /*   0 = Disable 1 = Enable */
     514  } reg;
     515  unsigned long all;
    495516} LCDCON4;
    496517
    497518typedef union {
    498         struct {
    499                 unsigned HWSWP:1;               // STN/TFT: Half-Word swap control bit. 0 = Swap Disable 1 = Swap Enable
    500                 unsigned BSWP:1;                // STN/TFT: Byte swap control bit. 0 = Swap Disable 1 = Swap Enable
    501                 unsigned ENLEND:1;              // TFT: LEND output signal enable/disable. 0 = Disable LEND signal. 1 = Enable LEND signal
    502                 unsigned RESERVED1:1;
    503                 unsigned INVENDLINE:1;  // TFT: This bit indicates the LEND signal polarity. 0 = normal 1 = inverted
    504                 unsigned RESERVED2:1;
    505                 unsigned INVVDEN:1;             // TFT: This bit indicates the VDEN signal polarity. 0 = normal 1 = inverted
    506                 unsigned INVVD:1;               // STN/TFT: This bit indicates the VD (video data) pulse polarity. 0 = Normal. 1 = VD is inverted.
    507                 unsigned INVVFRAME:1;   // STN/TFT: This bit indicates the VFRAME/VSYNC pulse polarity. 0 = normal 1 = inverted
    508                 unsigned INVVLINE:1;    // STN/TFT: This bit indicates the VLINE/HSYNC pulse polarity. 0 = normal 1 = inverted
    509                 unsigned INVVCLK:1;             // STN/TFT: This bit controls the polarity of the VCLK active edge. 0 = The video data is fetched at VCLK falling edge. 1 = The video data is fetched at VCLK rising edge
    510                 unsigned RESERVED3:2;
    511                 unsigned SELFREF:1;             // STN:
    512                 unsigned SLOWCLKSYNC:1; // STN:
    513                 unsigned RESERVED4:2;   // must be 0
    514                 unsigned HSTATUS:2;             // TFT: Horizontal Status (Read only) 00 = HSYNC 01 = BACK Porch. 10 = ACTIVE 11 = FRONT Porch
    515                 unsigned VSTATUS:2;             // TFT: Vertical Status (Read only). 00 = VSYNC 01 = BACK Porch. 10 = ACTIVE 11 = FRONT Porch
    516         } reg;
    517         unsigned long all;
     519  struct {
     520    unsigned HWSWP:1;     /* STN/TFT: Half-Word swap control bit. */
     521                          /*    0 = Swap Disable 1 = Swap Enable */
     522    unsigned BSWP:1;      /* STN/TFT: Byte swap control bit. */
     523                          /*    0 = Swap Disable 1 = Swap Enable */
     524    unsigned ENLEND:1;    /* TFT: LEND output signal enable/disable. */
     525                          /*    0 = Disable LEND signal. */
     526                          /*    1 = Enable LEND signal */
     527    unsigned RESERVED1:1;
     528    unsigned INVENDLINE:1;/* TFT: This bit indicates the LEND signal */
     529                          /*    polarity. 0 = normal 1 = inverted */
     530    unsigned RESERVED2:1;
     531    unsigned INVVDEN:1;   /* TFT: This bit indicates the VDEN signal */
     532                          /*    polarity. */
     533                          /*    0 = normal 1 = inverted */
     534    unsigned INVVD:1;     /* STN/TFT: This bit indicates the VD (video data) */
     535                          /*    pulse polarity. 0 = Normal. */
     536                          /*    1 = VD is inverted. */
     537    unsigned INVVFRAME:1; /* STN/TFT: This bit indicates the VFRAME/VSYNC */
     538                          /*    pulse polarity. 0 = normal 1 = inverted */
     539    unsigned INVVLINE:1;  /* STN/TFT: This bit indicates the VLINE/HSYNC */
     540                          /*    pulse polarity. 0 = normal 1 = inverted */
     541    unsigned INVVCLK:1;   /* STN/TFT: This bit controls the polarity of the */
     542                          /*    VCLK active edge. 0 = The video data is */
     543                          /*    fetched at VCLK falling edge. 1 = The video */
     544                          /*    data is fetched at VCLK rising edge */
     545    unsigned RESERVED3:2;
     546    unsigned SELFREF:1;   /* STN: */
     547    unsigned SLOWCLKSYNC:1; /* STN: */
     548    unsigned RESERVED4:2; /* must be 0 */
     549    unsigned HSTATUS:2;   /* TFT: Horizontal Status (Read only) */
     550                          /*    00 = HSYNC */
     551                          /*    01 = BACK Porch. */
     552                          /*    10 = ACTIVE */
     553                          /*    11 = FRONT Porch */
     554    unsigned VSTATUS:2;   /* TFT: Vertical Status (Read only). */
     555                          /*    00 = VSYNC */
     556                          /*    01 = BACK Porch. */
     557                          /*    10 = ACTIVE */
     558                          /*    11 = FRONT Porch */
     559  } reg;
     560  unsigned long all;
    518561} LCDCON5;
    519562
    520563typedef union {
    521         struct {
    522                 unsigned LCDBASEU:21;   // For single-scan LCD: These bits indicate A[21:1] of the start address of the LCD frame buffer.
    523                 unsigned LCDBANK:7;             // A[28:22]
    524         } reg;
    525         unsigned long all;
     564  struct {
     565    unsigned LCDBASEU:21; /* For single-scan LCD: These bits indicate */
     566                          /*    A[21:1] of the start address of the LCD */
     567                          /*    frame buffer. */
     568    unsigned LCDBANK:7;   /* A[28:22] */
     569  } reg;
     570  unsigned long all;
    526571} LCDSADDR1;
    527572
    528573typedef union {
    529         struct {
    530                 unsigned LCDBASEL:21;   // For single scan LCD: These bits indicate A[21:1] of the end address of the LCD frame buffer. LCDBASEL = ((the fame end address) >>1) + 1 = LCDBASEU + (PAGEWIDTH+OFFSIZE)x(LINEVAL+1)
    531         } reg;
    532         unsigned long all;
     574  struct {
     575    unsigned LCDBASEL:21; /* For single scan LCD: These bits indicate A[21:1]*/
     576                          /*    of the end address of the LCD frame buffer. */
     577                          /*    LCDBASEL = ((the fame end address) >>1) + 1 */
     578                          /*    = LCDBASEU + (PAGEWIDTH+OFFSIZE)x(LINEVAL+1) */
     579  } reg;
     580  unsigned long all;
    533581} LCDSADDR2;
    534582
    535583typedef union {
    536         struct {
    537                 unsigned PAGEWIDTH:11;  // Virtual screen page width(the number of half words) This value defines the width of the view port in the frame
    538                 unsigned OFFSIZE:11;    // Virtual screen offset size(the number of half words) This value defines the difference between the address of the last half word displayed on the previous LCD line and the address of the first half word to be displayed in the new LCD line.
    539         } reg;
    540         unsigned long all;
     584  struct {
     585    unsigned PAGEWIDTH:11; /* Virtual screen page width(the number of half */
     586                          /*    words) This value defines the width of the */
     587                          /*    view port in the frame */
     588    unsigned OFFSIZE:11;  /* Virtual screen offset size(the number of half */
     589                          /*    words) This value defines the difference */
     590                          /*    between the address of the last half word */
     591                          /*    displayed on the previous LCD line and the */
     592                          /*    address of the first half word to be */
     593                          /*    displayed in the new LCD line. */
     594  } reg;
     595  unsigned long all;
    541596} LCDSADDR3;
    542597
    543 //
    544 //
    545 //
    546 
    547 typedef union {
    548         struct {
    549                 unsigned IISIFENA:1;    // IIS interface enable (start)
    550                 unsigned IISPSENA:1;    // IIS prescaler enable
    551                 unsigned RXCHIDLE:1;    // Receive channel idle command
    552                 unsigned TXCHIDLE:1;    // Transmit channel idle command
    553                 unsigned RXDMAENA:1;    // Receive DMA service request enable
    554                 unsigned TXDMAENA:1;    // Transmit DMA service request enable
    555                 unsigned RXFIFORDY:1;   // Receive FIFO ready flag (read only)
    556                 unsigned TXFIFORDY:1;   // Transmit FIFO ready flag (read only)
    557                 unsigned LRINDEX:1;             // Left/right channel index (read only)
    558         } reg;
    559         unsigned long all;
     598/*
     599 *
     600 */
     601
     602typedef union {
     603  struct {
     604    unsigned IISIFENA:1;  /* IIS interface enable (start) */
     605    unsigned IISPSENA:1;  /* IIS prescaler enable */
     606    unsigned RXCHIDLE:1;  /* Receive channel idle command */
     607    unsigned TXCHIDLE:1;  /* Transmit channel idle command */
     608    unsigned RXDMAENA:1;  /* Receive DMA service request enable */
     609    unsigned TXDMAENA:1;  /* Transmit DMA service request enable */
     610    unsigned RXFIFORDY:1; /* Receive FIFO ready flag (read only) */
     611    unsigned TXFIFORDY:1; /* Transmit FIFO ready flag (read only) */
     612    unsigned LRINDEX:1;   /* Left/right channel index (read only) */
     613  } reg;
     614  unsigned long all;
    560615} IISCON;
    561616
    562617typedef union {
    563         struct {
    564                 unsigned SBCLKFS:2;             // Serial bit clock frequency select
    565                 unsigned MCLKFS:1;              // Master clock frequency select
    566                 unsigned SDBITS:1;              // Serial data bit per channel
    567                 unsigned SIFMT:1;               // Serial interface format
    568                 unsigned ACTLEVCH:1;    // Active level pf left/right channel
    569                 unsigned TXRXMODE:2;    // Transmit/receive mode select
    570                 unsigned MODE:1;                // Master/slave mode select
    571         } reg;
    572         unsigned long all;
     618  struct {
     619    unsigned SBCLKFS:2;  /* Serial bit clock frequency select */
     620    unsigned MCLKFS:1;   /* Master clock frequency select */
     621    unsigned SDBITS:1;   /* Serial data bit per channel */
     622    unsigned SIFMT:1;    /* Serial interface format */
     623    unsigned ACTLEVCH:1; /* Active level pf left/right channel */
     624    unsigned TXRXMODE:2; /* Transmit/receive mode select */
     625    unsigned MODE:1;     /* Master/slave mode select */
     626  } reg;
     627  unsigned long all;
    573628} IISMOD;
    574629
    575630typedef union {
    576         struct {
    577                 unsigned PSB:5;                 // Prescaler control B
    578                 unsigned PSA:5;                 // Prescaler control A
    579         } reg;
    580         unsigned long all;
     631  struct {
     632    unsigned PSB:5;      /* Prescaler control B */
     633    unsigned PSA:5;      /* Prescaler control A */
     634  } reg;
     635  unsigned long all;
    581636} IISPSR;
    582637
    583638typedef union {
    584         struct {
    585                 unsigned RXFIFOCNT:4;   // (read only)
    586                 unsigned TXFIFOCNT:4;   // (read only)
    587                 unsigned RXFIFOENA:1;   //
    588                 unsigned TXFIFOENA:1;   //
    589                 unsigned RXFIFOMODE:1;  //
    590                 unsigned TXFIFOMODE:1;  //
    591         } reg;
    592         unsigned long all;
     639  struct {
     640    unsigned RXFIFOCNT:4;  /* (read only) */
     641    unsigned TXFIFOCNT:4;  /* (read only) */
     642    /*signed RXFIFOENA:1;  /* */
     643    unsigned TXFIFOENA:1;  /* */
     644    unsigned RXFIFOMODE:1; /* */
     645    unsigned TXFIFOMODE:1; /* */
     646  } reg;
     647  unsigned long all;
    593648} IISSFIFCON;
    594649
    595650typedef union {
    596         struct {
    597                 unsigned FENTRY:16;             //
    598         } reg;
    599         unsigned long all;
     651  struct {
     652    unsigned FENTRY:16;    /* */
     653  } reg;
     654  unsigned long all;
    600655} IISSFIF;
    601656
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