Changeset 5e0ab02 in rtems


Ignore:
Timestamp:
Dec 21, 2018, 6:46:58 AM (4 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
b0c2d48
Parents:
a6f70e1
git-author:
Sebastian Huber <sebastian.huber@…> (12/21/18 06:46:58)
git-committer:
Sebastian Huber <sebastian.huber@…> (12/21/18 09:32:37)
Message:

bsps: Update cache manager documentation

Update #3667.

File:
1 edited

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Added
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  • bsps/shared/cache/cacheimpl.h

    ra6f70e1 r5e0ab02  
    11/*
    22 *  Cache Manager
     3 *
     4 *  Copyright (C) 2014, 2018 embedded brains GmbH
    35 *
    46 *  COPYRIGHT (c) 1989-1999.
     
    810 *  found in the file LICENSE in this distribution or at
    911 *  http://www.rtems.org/license/LICENSE.
    10  *
    11  *
    12  *  The functions in this file implement the API to the RTEMS Cache Manager and
    13  *  are divided into data cache and instruction cache functions. Data cache
    14  *  functions only have bodies if a data cache is supported. Instruction
    15  *  cache functions only have bodies if an instruction cache is supported.
    16  *  Support for a particular cache exists only if CPU_x_CACHE_ALIGNMENT is
    17  *  defined, where x E {DATA, INSTRUCTION}. These definitions are found in
    18  *  the Cache Manager Wrapper header files, often
    19  *
    20  *  rtems/c/src/lib/libcpu/CPU/cache_.h
    21  *
    22  *  The cache implementation header file can define
    23  *
    24  *    #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
    25  *
    26  *  if it provides cache maintenance functions which operate on multiple lines.
    27  *  Otherwise a generic loop with single line operations will be used.  It is
    28  *  strongly recommended to provide the implementation in terms of static
    29  *  inline functions for performance reasons.
    30  *
    31  *  The functions below are implemented with CPU dependent inline routines
    32  *  found in the cache.c files for each CPU. In the event that a CPU does
    33  *  not support a specific function for a cache it has, the CPU dependent
    34  *  routine does nothing (but does exist).
    35  *
    36  *  At this point, the Cache Manager makes no considerations, and provides no
    37  *  support for BSP specific issues such as a secondary cache. In such a system,
    38  *  the CPU dependent routines would have to be modified, or a BSP layer added
    39  *  to this Manager.
     12 */
     13
     14/*
     15 * The functions in this file implement the API to the RTEMS Cache Manager.
     16 * This file is intended to be included in a cache implemention source file
     17 * provided by the architecture or BSP, e.g.
     18 *
     19 *  - bsps/${RTEMS_CPU}/shared/cache/cache.c
     20 *  - bsps/${RTEMS_CPU}/${RTEMS_BSP_FAMILY}/start/cache.c
     21 *
     22 * In this file a couple of defines and inline functions may be provided and
     23 * afterwards this file is included, e.g.
     24 *
     25 *  #define CPU_DATA_CACHE_ALIGNMENT XYZ
     26 *  ...
     27 *  #include "../../../bsps/shared/cache/cacheimpl.h"
     28 *
     29 * The cache implementation source file shall define
     30 *
     31 *  #define CPU_DATA_CACHE_ALIGNMENT <POSITIVE INTEGER>
     32 *
     33 * to enable the data cache support.
     34 *
     35 * The cache implementation source file shall define
     36 *
     37 *  #define CPU_INSTRUCTION_CACHE_ALIGNMENT <POSITIVE INTEGER>
     38 *
     39 * to enable the instruction cache support.
     40 *
     41 * The cache implementation source file shall define
     42 *
     43 *  #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
     44 *
     45 * if it provides cache maintenance functions which operate on multiple lines.
     46 * Otherwise a generic loop with single line operations will be used.  It is
     47 * strongly recommended to provide the implementation in terms of static inline
     48 * functions for performance reasons.
     49 *
     50 * The cache implementation source file shall define
     51 *
     52 *  #define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS
     53 *
     54 * if it provides functions to get the data and instruction cache sizes by
     55 * level.
     56 *
     57 * The cache implementation source file shall define
     58 *
     59 *  #define CPU_CACHE_SUPPORT_PROVIDES_INSTRUCTION_SYNC_FUNCTION
     60 *
     61 * if special instructions must be used to synchronize the instruction caches
     62 * after a code change.
     63 *
     64 * The cache implementation source file shall define
     65 *
     66 *  #define CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING
     67 *
     68 * if the hardware provides no instruction cache snooping and the instruction
     69 * cache invalidation needs software support.
     70 *
     71 * The functions below are implemented with inline routines found in the cache
     72 * implementation source file for each architecture or BSP.  In the event that
     73 * not support for a specific function for a cache is provided, the API routine
     74 * does nothing (but does exist).
    4075 */
    4176
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