Changeset 5dbc2e2 in rtems


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Timestamp:
Apr 8, 1999, 4:09:11 PM (21 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
936ae5d
Parents:
920e47f6
Message:

First attempt to build.

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1 edited

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  • doc/networking/decdriver.t

    r920e47f6 r5dbc2e2  
    1 %% This LaTeX-file was created by <raguet> Wed Apr  7 17:10:33 1999
    2 %% LyX 1.0 (C) 1995-1999 by Matthias Ettrich and the LyX Team
    3 
    4 %% Do not edit this file unless you know what you are doing.
    5 \documentclass[10pt,american]{article}
    6 \usepackage[T1]{fontenc}
    7 \usepackage{a4wide}
    8 \pagestyle{plain}
    9 \usepackage{babel}
    10 \usepackage[dvips]{graphics}
    11 
    12 \makeatletter
    13 
    14 
    15 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%% LyX specific LaTeX commands.
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    18 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%% User specified LaTeX commands.
    19 \usepackage[dvips]{epsfig}
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    21 \makeatother
    22 
    23 \begin{document}
    24 
    25 \resizebox*{1\textwidth}{!}{\includegraphics{garde.eps}}
    26 
    27 {\par\centering \newpage\par}
    28 \vspace{0.3cm}
    29 
    30 \bigskip{}
    31 {\par\centering \textbf{\Huge Ethernet Driver for PCI DEC board}\Huge \par}
    32 \bigskip{}
    33 
    34 \tableofcontents{}
    35 
    36 \listoffigures{}
    37 
    38 \newpage
    39 
    40 
    41 \section{\noindent Introduction}
     1@c
     2@c  RTEMS Remote Debugger Server Specifications
     3@c
     4@c  Written by: Emmanuel Raguet <raguet@crf.canon.fr>
     5@c
     6@c
     7@c  $Id$
     8@c
     9
     10@chatper DEC 21140 Driver
     11
     12@section Introduction
     13
     14@c XXX add back in cross reference to list of boards.
    4215
    4316One aim of our project is to port RTEMS on a standard PowerPC platform. To achieve
     
    4619have to develop the DEC21140 related ethernet driver for the PowerPC port of
    4720RTEMS. As this controller is able to support 100Mbps network and as there is
    48 a lot of PCI card using this DEC chip (cf \ref{List}), we have decided to first
     21a lot of PCI card using this DEC chip, we have decided to first
    4922implement this driver on an Intel PC386 target to provide a solution for using
    5023RTEMS on PC with the 100Mbps network and then to port this code on PowerPC in
    51 a second phase.\\
    52 
    53 
    54 \noindent The aim of this document is to give some PCI board generalities and
     24a second phase.
     25
     26
     27The aim of this document is to give some PCI board generalities and
    5528to explain the software architecture of the RTEMS driver. Finally, we will see
    5629what will be done for ChorusOs and Netboot environment .
    5730
    5831
    59 \section{Document Revision History}
    60 
    61 \underbar{Current release} :
    62 
    63 \begin{itemize}
    64 \item \noindent Current applicable release is 1.0.
    65 \end{itemize}
    66 \noindent \underbar{Existing releases} :
    67 
    68 \begin{itemize}
    69 \item \noindent 1.0 : Released the 10/02/98. First version of this document.
    70 \item 0.1 : First draft of this document
    71 \end{itemize}
    72 \noindent \underbar{Planned releases} :
    73 
    74 \begin{itemize}
    75 \item \noindent None planned today.
    76 \end{itemize}
    77 
    78 \section{DEC21140 PCI Board Generalities}
    79 
     32@section Document Revision History
     33
     34@b{Current release}:
     35
     36@itemize @bullet
     37@item Current applicable release is 1.0.
     38@end itemize
     39@b{Existing releases}:
     40
     41@itemize @bullet
     42@item 1.0 : Released the 10/02/98. First version of this document.
     43@item 0.1 : First draft of this document
     44@end itemize
     45@b{Planned releases}:
     46
     47@itemize @bullet
     48@item None planned today.
     49@end itemize
     50
     51@section DEC21140 PCI Board Generalities
     52
     53@c XXX add crossreference to PCI Register Figure
    8054This chapter describes rapidely the PCI interface of this Ethernet controller.
    8155The board we have chosen for our PC386 implementation is a D-Link DFE-500TX.
    8256This is a dual-speed 10/100Mbps Ethernet PCI adapter with a DEC21140AF chip.
    8357Like other PCI devices, this board has a PCI device's header containing some
    84 required configuration registers, as shown in figure \ref{PCI reg}. By reading
     58required configuration registers, as shown in the PCI Register Figure.
     59By reading
    8560or writing these registers, a driver can obtain information about the type of
    86 the board, the interrupt it uses, the mapping of the chip specific registers,~...
    87 \\
    88 
    89 
    90 \noindent On Intel target, the chip specific registers can be accessed via 2
     61the board, the interrupt it uses, the mapping of the chip specific registers, ...
     62
     63
     64
     65On Intel target, the chip specific registers can be accessed via 2
    9166methods : I/O port access or PCI address mapped access. We have chosen to implement
    9267the PCI address access to obtain compatible source code to the port the driver
    93 on a PowerPC target.\\
    94 
    95 
    96 \begin{figure}
    97 {\par\centering \includegraphics{PCI_reg.eps} \par}
    98 
    99 
    100 \caption{\label{PCI reg}PCI device's configuration header space format}
    101 \end{figure}
     68on a PowerPC target.
     69
     70@c
     71@c PCI Device's Configuration Header Space Format
     72@c
     73
     74@ifset use-ascii
     75@example
     76@group
     77XXXXX reference it in the previous paragraph
     78XXXXX insert PCI_reg.eps
     79XXXXX Caption PCI Device's Configuration Header Space Format
     80@end group
     81@end example
     82@end ifset
     83
     84@ifset use-tex
     85@example
     86@group
     87XXXXX reference it in the previous paragraph
     88XXXXX insert PCI_reg.eps
     89XXXXX Caption PCI Device's Configuration Header Space Format
     90@end group
     91@end example
     92@end ifset
     93
     94@c @image{PCI_reg}
     95
     96@ifset use-html
     97@c <IMG SRC="PCI_reg.jpg" WIDTH=500 HEIGHT=600 ALT="PCI Device's Configuration Header Space Format">
     98@html
     99<IMG SRC="PCI_reg.jpg" ALT="PCI Device's Configuration Header Space Format">
     100@end html
     101@end ifset
     102
     103
     104@c XXX add crossreference to PCI Register Figure
     105
    102106On RTEMS, a PCI API exists. We have used it to configure the board. After initializing
    103 this PCI module via the \textbf{\textit{pcib\_init()}} function, we try to detect
     107this PCI module via the @code{pcib_init()} function, we try to detect
    104108the DEC21140 based ethernet board. This board is characterized by its Vendor
    105 ID (0x1011) and its Device ID (0x0009). We give these arguments to the \textbf{\textit{pcib\_find\_by\_deviceid}}
     109ID (0x1011) and its Device ID (0x0009). We give these arguments to the
     110@code{pcib_find_by_deviceid}
    106111function which returns , if the device is present, a pointer to the configuration
    107 header space (cf fig \ref{PCI reg}). Once this operation performed, the driver
     112header space (see PCI Registers Fgure). Once this operation performed,
     113the driver
    108114is able to extract the information it needs to configure the board internal
    109115registers, like the interrupt line, the base address,... The board internal
    110 registers will not be detailled here. You can find them in \cite{1}.\newpage
    111 
    112 
    113 \section{\noindent RTEMS Driver Software Architecture}
     116registers will not be detailled here. You can find them in @title{DIGITAL
     117Semiconductor 21140A PCI Fast Ethernet LAN Controller
     118- Hardware Reference Manual}.
     119
     120@c fix citation
     121
     122
     123@section RTEMS Driver Software Architecture
    114124
    115125In this chapter will see the initialization phase, how the controller uses the
     
    117127
    118128
    119 \subsection{Initialization phase}
     129@subsection Initialization phase
    120130
    121131The DEC21140 Ethernet driver keeps the same software architecture than the other
    122 RTEMS ethernet drivers. The only API the programmer can use is the \textbf{\textit{``rtems\_dec21140\_driver\_attach}}\\
    123 \textbf{\textit{(struct rtems\_bsdnet\_ifconfig {*}config)''}} function which
     132RTEMS ethernet drivers. The only API the programmer can use is the @code{rtems_dec21140_driver_attach}
     133@code{(struct rtems_bsdnet_ifconfig *config)} function which
    124134detects the board and initializes the associated data structure (with registers
    125135base address, entry points to low-level initialization function,...), if the
    126136board is found.
    127137
    128 \noindent Once the attach function executed, the driver initializes the DEC
     138Once the attach function executed, the driver initializes the DEC
    129139chip. Then the driver connects an interrupt handler to the interrupt line driven
    130140by the Ethernet controller (the only interrupt which will be treated is the
     
    134144
    135145
    136 \subsection{Memory Buffer}
    137 
     146@subsection Memory Buffer
     147
     148@c XXX add cross reference to Problem
    138149This DEC chip uses the host memory to store the incoming Ethernet frames and
    139150the descriptor of these frames. We have chosen to use 7 receive buffers and
    1401511 transmit buffer to optimize memory allocation due to cache and paging problem
    141 that will be explained in paragraph \ref{Problem}).\\
    142 
    143 
    144 \noindent To reference these buffers to the DEC chip we use a buffer descriptors
    145 ring. The descriptor structure is defined in figure \ref{bdescr}. Each descriptor
     152that will be explained in the section @b{Encountered Problems.
     153
     154
     155To reference these buffers to the DEC chip we use a buffer descriptors
     156ring. The descriptor structure is defined in the Buffer Descriptor Figure.
     157Each descriptor
    146158can reference one or two memory buffers. We choose to use only one buffer of
    147 1520 bytes per descriptor.\\
    148 
    149 
    150 \noindent The difference between a receive and a transmit buffer descriptor
     1591520 bytes per descriptor.
     160
     161
     162The difference between a receive and a transmit buffer descriptor
    151163is located in the status and control bits fields. We do not give details here,
    152 please refer to \cite{1}.
    153 
    154 \begin{figure}
    155 {\par\centering \includegraphics{recv_bd.eps} \par}
    156 
    157 
    158 \caption{\label{bdescr}Buffer Descriptor}
    159 \end{figure}
    160 
    161 
    162 
    163 \subsection{Receiver Thread}
     164please refer to the [DEC21140 Hardware Manual].
     165
     166@c
     167@c Buffer Descriptor
     168@c
     169
     170@ifset use-ascii
     171@example
     172@group
     173XXXXX reference it in the previous paragraph
     174XXXXX insert recv_bd.eps
     175XXXXX Caption Buffer Descriptor
     176@end group
     177@end example
     178@end ifset
     179
     180@ifset use-tex
     181@example
     182@group
     183XXXXX reference it in the previous paragraph
     184XXXXX insert recv_bd.eps
     185XXXXX Caption Buffer Descriptor
     186@end group
     187@end example
     188@end ifset
     189
     190@c @image{recv_bd}
     191
     192@ifset use-html
     193@c <IMG SRC="recv_bd.jpg" WIDTH=500 HEIGHT=600 ALT="Buffer Descriptor">
     194@html
     195<IMG SRC="recv_bd.jpg" ALT="Buffer Descriptor">
     196@end html
     197@end ifset
     198
     199
     200
     201@subsection Receiver Thread
    164202
    165203This thread is event driven. Each time a DEC PCI board interrupt occurs, the
     
    172210
    173211
    174 \subsection{Transmitter Thread}
     212@subsection Transmitter Thread
    175213
    176214This thread is also event driven. Each time an Ethernet frame is put in the
     
    180218
    181219
    182 \section{\label{Problem}Encountered Problems}
     220@section Encountered Problems
    183221
    184222On Intel PC386 target, we were faced with a problem of memory cache management.
     
    188226ones written (or read) by the DEC21140 device in the host memory and not old
    189227data stored in the cache memory. Therefore, we had to provide a way to manage
    190 the cache. This module is described in the document \cite{2}. On Intel, the
     228the cache. This module is described in the document @b{RTEMS
     229Cache Management For Intel}. On Intel, the
    191230memory region cache management is available only if the paging unit is enabled.
    192231We have used this paging mechanism, with 4Kb page. All the buffers allocated
    193232to store the incoming or outcoming frames, buffer descriptor and also the PCI
    194 address space of the DEC board are located in a memory space with cache disable.\\
    195 
    196 
    197 \noindent Concerning the buffers and their descriptors, we have tried to optimize
     233address space of the DEC board are located in a memory space with cache disable.
     234
     235
     236Concerning the buffers and their descriptors, we have tried to optimize
    198237the memory space in term of allocated page. One buffer has 1520 bytes, one descriptor
    199238has 16 bytes. We have 7 receive buffers and 1 transmit buffer, and for each,
    200 1 descriptor : (7+1){*}(1520+16) = 12288 bytes = 12Kb = 3 entire pages. This
     2391 descriptor : (7+1)*(1520+16) = 12288 bytes = 12Kb = 3 entire pages. This
    201240allows not to lose too much memory or not to disable cache memory for a page
    202241which contains other data than buffer, which could decrease performance.
    203242
    204243
    205 \section{ChorusOs DEC Driver}
     244@section ChorusOs DEC Driver
    206245
    207246Because ChorusOs is used in several Canon CRF projects, we must provide such
     
    214253
    215254
    216 \section{Netboot DEC driver}
     255@section Netboot DEC driver
    217256
    218257We use Netboot tool to load our development from a server to the target via
    219258an ethernet network. Currently, this tool does not support the DEC board. We
    220 plan to port the DEC driver for the Netboot tool.\\
    221 
    222 
    223 \noindent But concerning the port of the DEC driver into Netboot, we are faced
     259plan to port the DEC driver for the Netboot tool.
     260
     261
     262But concerning the port of the DEC driver into Netboot, we are faced
    224263with a problem : in RTEMS environment, the DEC driver is interrupt or event
    225264driven, in Netboot environment, it must be used in polling mode. It means that
     
    227266
    228267
    229 \section{\label{List}List of Ethernet cards using the DEC chip}
     268@section List of Ethernet cards using the DEC chip
    230269
    231270Many Ethernet adapter cards use the Tulip chip. Here is a non exhaustive list
    232271of adapters which support this driver :
    233272
    234 \begin{itemize}
    235 \item Accton EtherDuo PCI.
    236 \item Accton EN1207 All three media types supported.
    237 \item Adaptec ANA6911/TX 21140-AC.
    238 \item Cogent EM110 21140-A with DP83840 N-Way MII transceiver.
    239 \item Cogent EM400 EM100 with 4 21140 100mbps-only ports + PCI Bridge.
    240 \item Danpex EN-9400P3.
    241 \item D-Link DFE500-Tx 21140-A with DP83840 transceiver.
    242 \item Kingston EtherX KNE100TX 21140AE.
    243 \item Netgear FX310 TX 10/100 21140AE.
    244 \item SMC EtherPower10/100 With DEC21140 and 68836 SYM transceiver.
    245 \item SMC EtherPower10/100 With DEC21140-AC and DP83840 MII transceiver. \\
     273@itemize @bullet
     274@item Accton EtherDuo PCI.
     275@item Accton EN1207 All three media types supported.
     276@item Adaptec ANA6911/TX 21140-AC.
     277@item Cogent EM110 21140-A with DP83840 N-Way MII transceiver.
     278@item Cogent EM400 EM100 with 4 21140 100mbps-only ports + PCI Bridge.
     279@item Danpex EN-9400P3.
     280@item D-Link DFE500-Tx 21140-A with DP83840 transceiver.
     281@item Kingston EtherX KNE100TX 21140AE.
     282@item Netgear FX310 TX 10/100 21140AE.
     283@item SMC EtherPower10/100 With DEC21140 and 68836 SYM transceiver.
     284@item SMC EtherPower10/100 With DEC21140-AC and DP83840 MII transceiver.
    246285Note: The EtherPower II uses the EPIC chip, which requires a different driver.
    247 \item Surecom EP-320X DEC 21140.
    248 \item Thomas Conrad TC5048.
    249 \item Znyx ZX345 21140-A, usually with the DP83840 N-Way MII transciever. Some ZX345
     286@item Surecom EP-320X DEC 21140.
     287@item Thomas Conrad TC5048.
     288@item Znyx ZX345 21140-A, usually with the DP83840 N-Way MII transciever. Some ZX345
    250289cards made in 1996 have an ICS 1890 transciver instead.
    251 \item ZNYX ZX348 Two 21140-A chips using ICS 1890 transcievers and either a 21052
     290@item ZNYX ZX348 Two 21140-A chips using ICS 1890 transcievers and either a 21052
    252291or 21152 bridge. Early versions used National 83840 transcievers, but later
    253292versions are depopulated ZX346 boards.
    254 \item ZNYX ZX351 21140 chip with a Broadcom 100BaseT4 transciever.
    255 \end{itemize}
     293@item ZNYX ZX351 21140 chip with a Broadcom 100BaseT4 transciever.
     294@end itemize
     295
    256296Our DEC driver has not been tested with all these cards, only with the D-Link
    257297DFE500-TX.
    258298
    259 \begin{thebibliography}{DEC21140 Hardware Manual}
    260 \bibitem[DEC21140 Hardware Manual]{1}DIGITAL, \textit{DIGITAL Semiconductor 21140A PCI Fast Ethernet LAN Controller
    261 - Hardware Reference Manual.}
    262 \bibitem[99.TA.0021.M.ER]{2}Emmanuel Raguet, \textit{RTEMS Cache Management For Intel.}
    263 \end{thebibliography}
    264 \end{document}
     299@itemize @code{ }
     300@item @cite{[DEC21140 Hardware Manual] DIGITAL, @b{DIGITAL
     301Semiconductor 21140A PCI Fast Ethernet LAN Controller - Hardware
     302Reference Manual}}.
     303
     304@item @cite{[99.TA.0021.M.ER]Emmanuel Raguet,
     305@b{RTEMS Cache Management For Intel}}.
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