Changeset 5d7bfce3 in rtems
- Timestamp:
- 12/06/00 15:32:40 (23 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 5996c48
- Parents:
- c3df4a6
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/exec/score/cpu/mips/ChangeLog
rc3df4a6 r5d7bfce3 1 2000-12-06 Joel Sherrill <joel@OARcorp.com> 2 3 * rtems/score/cpu.h: When mips ISA level is 1, registers in the 4 context should be 32 not 64 bits. 5 1 6 2000-11-30 Joel Sherrill <joel@OARcorp.com> 2 7 -
c/src/exec/score/cpu/mips/rtems/score/cpu.h
rc3df4a6 r5d7bfce3 361 361 /* WARNING: If this structure is modified, the constants in cpu.h must be updated. */ 362 362 typedef struct { 363 #if __mips == 1 364 unsigned32 s0; 365 unsigned32 s1; 366 unsigned32 s2; 367 unsigned32 s3; 368 unsigned32 s4; 369 unsigned32 s5; 370 unsigned32 s6; 371 unsigned32 s7; 372 unsigned32 sp; 373 unsigned32 fp; 374 unsigned32 ra; 375 unsigned32 c0_sr; 376 unsigned32 c0_epc; 377 #else 363 378 unsigned64 s0; 364 379 unsigned64 s1; … … 374 389 unsigned64 c0_sr; 375 390 unsigned64 c0_epc; 391 #endif 376 392 } Context_Control; 377 393 -
cpukit/score/cpu/mips/ChangeLog
rc3df4a6 r5d7bfce3 1 2000-12-06 Joel Sherrill <joel@OARcorp.com> 2 3 * rtems/score/cpu.h: When mips ISA level is 1, registers in the 4 context should be 32 not 64 bits. 5 1 6 2000-11-30 Joel Sherrill <joel@OARcorp.com> 2 7 -
cpukit/score/cpu/mips/rtems/score/cpu.h
rc3df4a6 r5d7bfce3 361 361 /* WARNING: If this structure is modified, the constants in cpu.h must be updated. */ 362 362 typedef struct { 363 #if __mips == 1 364 unsigned32 s0; 365 unsigned32 s1; 366 unsigned32 s2; 367 unsigned32 s3; 368 unsigned32 s4; 369 unsigned32 s5; 370 unsigned32 s6; 371 unsigned32 s7; 372 unsigned32 sp; 373 unsigned32 fp; 374 unsigned32 ra; 375 unsigned32 c0_sr; 376 unsigned32 c0_epc; 377 #else 363 378 unsigned64 s0; 364 379 unsigned64 s1; … … 374 389 unsigned64 c0_sr; 375 390 unsigned64 c0_epc; 391 #endif 376 392 } Context_Control; 377 393
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