Changeset 5d6e54d0 in rtems


Ignore:
Timestamp:
Oct 6, 2005, 7:36:09 PM (15 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Children:
a5222eef
Parents:
6fa5969
Message:

2005-10-06 Till Straumann <strauman@…>

PR 833/bsps

  • irq/irq_asm.S: Currently, all (new exception) BSPs explicitely enable the FPU across the user ISR but DONT save/restore the FPU context. Any use of the FPU fron the user handler (e.g., due to GCC optimizations) result in corruption. The fix results in an exception in such cases (user ISR must explicitely save/enable/restore FPU).
Location:
c/src/lib/libbsp/powerpc
Files:
8 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/eth_comm/ChangeLog

    r6fa5969 r5d6e54d0  
     12005-10-06      Till Straumann <strauman@slac.stanford.edu>
     2
     3        PR 833/bsps
     4        * irq/irq_asm.S: Currently, all (new exception) BSPs explicitely enable
     5        the FPU across the user ISR but DONT save/restore the FPU context.
     6        Any use of the FPU fron the user handler (e.g., due to GCC
     7        optimizations) result in corruption. The fix results in an exception
     8        in such cases (user ISR must explicitely save/enable/restore FPU).
     9
    1102003-12-19      Joel Sherrill <joel@OARcorp.com>
    211
  • c/src/lib/libbsp/powerpc/eth_comm/irq/irq_asm.S

    r6fa5969 r5d6e54d0  
    1313 *    - store isr nesting level in _ISR_Nest_level rather than
    1414 *      SPRG0 - RTEMS relies on that variable.
     15 *  Till Straumann <strauman@slac.stanford.edu>, 2005/4:
     16 *    - DONT enable FP across user USR since fpregs are never saved!!
    1517 *
    1618 * $Id$
     
    8991         * Enable data and instruction address translation, exception recovery
    9092     *
    91      * also, on CPUs with FP, enable FP so that FP context can be
    92      * saved and restored (using FP instructions)
    93          */
    94 #if (PPC_HAS_FPU == 0)
     93         */
    9594        ori     r3, r3, MSR_RI | MSR_IR | MSR_DR
    96 #else
    97         ori     r3, r3, MSR_RI | MSR_IR | MSR_DR | MSR_FP
    98 #endif
    9995        mtmsr   r3
    10096        SYNC
     
    299295       
    300296switch:
     297#if ( PPC_HAS_FPU != 0 )
     298#if ! defined( CPU_USE_DEFERRED_FP_SWITCH )
     299#error missing include file???
     300#endif
     301        mfmsr  r4
     302#if ( CPU_USE_DEFERRED_FP_SWITCH == TRUE )
     303        /* if the executing thread has FP enabled propagate
     304         * this now so _Thread_Dispatch can save/restore the FPREGS
     305         * NOTE: it is *crucial* to disable the FPU across the
     306         *       user ISR [independent of using the 'deferred'
     307         *       strategy or not]. We don't save FP regs across
     308         *       the user ISR and hence we prefer an exception to
     309         *       be raised rather than experiencing corruption.
     310         */
     311        lwz    r3, SRR1_FRAME_OFFSET(r1)
     312        rlwimi r4, r3, 0, 18, 18 /* MSR_FP */
     313#else
     314        ori    r4, r4, MSR_FP
     315#endif
     316        mtmsr  r4
     317#endif
    301318        bl      SYM (_Thread_Dispatch)
    302319       
  • c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog

    r6fa5969 r5d6e54d0  
     12005-10-06      Till Straumann <strauman@slac.stanford.edu>
     2
     3        PR 833/bsps
     4        * irq/irq_asm.S: Currently, all (new exception) BSPs explicitely enable
     5        the FPU across the user ISR but DONT save/restore the FPU context.
     6        Any use of the FPU fron the user handler (e.g., due to GCC
     7        optimizations) result in corruption. The fix results in an exception
     8        in such cases (user ISR must explicitely save/enable/restore FPU).
     9
    1102005-09-12      Thomas Doerfler <Thomas.Doerfler@imd-systems.de>
    211
  • c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_asm.S

    r6fa5969 r5d6e54d0  
    1313 *    - store isr nesting level in _ISR_Nest_level rather than
    1414 *      SPRG0 - RTEMS relies on that variable.
     15 *  Till Straumann <strauman@slac.stanford.edu>, 2005/4:
     16 *    - DONT enable FP across user ISR since fpregs are never saved!!
    1517 *
    1618 * $Id$
     
    128130     * saved and restored (using FP instructions)
    129131         */
    130 #if (PPC_HAS_FPU == 0)
    131132        ori     r3, r3, MSR_RI | MSR_IR | MSR_DR
    132 #else
    133         ori     r3, r3, MSR_RI | MSR_IR | MSR_DR | MSR_FP
    134 #endif
    135133        mtmsr   r3
    136134        SYNC
     
    339337       
    340338switch:
     339#if ( PPC_HAS_FPU != 0 )
     340#if ! defined( CPU_USE_DEFERRED_FP_SWITCH )
     341#error missing include file???
     342#endif
     343        mfmsr  r4
     344#if ( CPU_USE_DEFERRED_FP_SWITCH == TRUE )
     345        /* if the executing thread has FP enabled propagate
     346         * this now so _Thread_Dispatch can save/restore the FPREGS
     347         * NOTE: it is *crucial* to disable the FPU across the
     348         *       user ISR [independent of using the 'deferred'
     349         *       strategy or not]. We don't save FP regs across
     350         *       the user ISR and hence we prefer an exception to
     351         *       be raised rather than experiencing corruption.
     352         */
     353        lwz    r3, SRR1_FRAME_OFFSET(r1)
     354        rlwimi r4, r3, 0, 18, 18 /* MSR_FP */
     355#else
     356        ori    r4, r4, MSR_FP
     357#endif
     358        mtmsr  r4
     359#endif
    341360        bl      SYM (_Thread_Dispatch)
    342361       
  • c/src/lib/libbsp/powerpc/mpc8260ads/ChangeLog

    r6fa5969 r5d6e54d0  
     12005-10-06      Till Straumann <strauman@slac.stanford.edu>
     2
     3        PR 833/bsps
     4        * irq/irq_asm.S: Currently, all (new exception) BSPs explicitely enable
     5        the FPU across the user ISR but DONT save/restore the FPU context.
     6        Any use of the FPU fron the user handler (e.g., due to GCC
     7        optimizations) result in corruption. The fix results in an exception
     8        in such cases (user ISR must explicitely save/enable/restore FPU).
     9
    1102004-09-27      Joel Sherrill <joel@OARcorp.com>
    211
  • c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq_asm.S

    r6fa5969 r5d6e54d0  
    1212 *  Modifications to store nesting level in global _ISR_Nest_level
    1313 *  variable instead of SPRG0.  Andy Dachs <a.dachs@sstl.co.uk>
     14 *
     15 *  Till Straumann <strauman@slac.stanford.edu>, 2005/4:
     16 *    - DONT enable FP across user ISR since fpregs are never saved!!
    1417 *
    1518 * $Id$
     
    9497         * saved and restored (using FP instructions)
    9598         */
    96 #if (PPC_HAS_FPU == 0)
    9799        ori     r3, r3, MSR_RI /*| MSR_IR | MSR_DR*/
    98 #else
    99         ori     r3, r3, MSR_RI | /*MSR_IR | MSR_DR |*/ MSR_FP
    100 #endif
    101100        mtmsr   r3
    102101        SYNC
     
    302301       
    303302switch:
     303#if ( PPC_HAS_FPU != 0 )
     304#if ! defined( CPU_USE_DEFERRED_FP_SWITCH )
     305#error missing include file???
     306#endif
     307        mfmsr  r4
     308#if ( CPU_USE_DEFERRED_FP_SWITCH == TRUE )
     309        /* if the executing thread has FP enabled propagate
     310         * this now so _Thread_Dispatch can save/restore the FPREGS
     311         * NOTE: it is *crucial* to disable the FPU across the
     312         *       user ISR [independent of using the 'deferred'
     313         *       strategy or not]. We don't save FP regs across
     314         *       the user ISR and hence we prefer an exception to
     315         *       be raised rather than experiencing corruption.
     316         */
     317        lwz    r3, SRR1_FRAME_OFFSET(r1)
     318        rlwimi r4, r3, 0, 18, 18 /* MSR_FP */
     319#else
     320        ori    r4, r4, MSR_FP
     321#endif
     322        mtmsr  r4
     323#endif
    304324        bl              SYM (_Thread_Dispatch)
    305325       
  • c/src/lib/libbsp/powerpc/shared/ChangeLog

    r6fa5969 r5d6e54d0  
     12005-10-06      Till Straumann <strauman@slac.stanford.edu>
     2
     3        PR 833/bsps
     4        * irq/irq_asm.S: Currently, all (new exception) BSPs explicitely enable
     5        the FPU across the user ISR but DONT save/restore the FPU context.
     6        Any use of the FPU fron the user handler (e.g., due to GCC
     7        optimizations) result in corruption. The fix results in an exception
     8        in such cases (user ISR must explicitely save/enable/restore FPU).
     9
    1102005-09-01      Joel Sherrill <joel@OARcorp.com>
    211
  • c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S

    r6fa5969 r5d6e54d0  
    1313 *    - store isr nesting level in _ISR_Nest_level rather than
    1414 *      SPRG0 - RTEMS relies on that variable.
     15 *  Till Straumann <strauman@slac.stanford.edu>, 2005/4:
     16 *    - DONT enable FP across ISR since fpregs are not saved!!
     17 *      FPU is used by Thread_Dispatch however...
    1518 *
    1619 * $Id$
     
    9699     * saved and restored (using FP instructions)
    97100         */
    98 #if (PPC_HAS_FPU == 0)
    99101        ori     r3, r3, MSR_RI | MSR_IR | MSR_DR
    100 #else
    101         ori     r3, r3, MSR_RI | MSR_IR | MSR_DR | MSR_FP
    102 #endif
    103102        mtmsr   r3
    104103        SYNC
     
    303302       
    304303switch:
     304#if ( PPC_HAS_FPU != 0 )
     305#if ! defined( CPU_USE_DEFERRED_FP_SWITCH )
     306#error missing include file???
     307#endif
     308        mfmsr  r4
     309#if ( CPU_USE_DEFERRED_FP_SWITCH == TRUE )
     310        /* if the executing thread has FP enabled propagate
     311         * this now so _Thread_Dispatch can save/restore the FPREGS
     312         * NOTE: it is *crucial* to disable the FPU across the
     313         *       user ISR [independent of using the 'deferred'
     314         *       strategy or not]. We don't save FP regs across
     315         *       the user ISR and hence we prefer an exception to
     316         *       be raised rather than experiencing corruption.
     317         */
     318        lwz    r3, SRR1_FRAME_OFFSET(r1)
     319        rlwimi r4, r3, 0, 18, 18 /* MSR_FP */
     320#else
     321        ori    r4, r4, MSR_FP
     322#endif
     323        mtmsr  r4
     324#endif
    305325        bl      SYM (_Thread_Dispatch)
    306326       
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