Changeset 5d4a1edc in rtems


Ignore:
Timestamp:
May 31, 2020, 2:22:55 PM (11 months ago)
Author:
Jan Sommer <jan.sommer@…>
Branches:
5, master
Children:
c954003
Parents:
8937f12
git-author:
Jan Sommer <jan.sommer@…> (05/31/20 14:22:55)
git-committer:
Chris Johns <chrisj@…> (06/11/20 03:29:11)
Message:

bsp/pc386: Define interrupt stack frame for smp

  • Defines CPU_Interrupt_frame in cpu_impl.h
  • Updates isq_asm.S to save/restore registers in matching order to

interrupt frame

Files:
3 edited

Legend:

Unmodified
Added
Removed
  • bsps/i386/shared/irq/irq_asm.S

    r8937f12 r5d4a1edc  
    2626
    2727/* Stack frame we use for intermediate storage               */
    28 #define ARG_OFF 0
    29 #define MSK_OFF 4        /* not used any more                */
    30 #define EBX_OFF 8        /* ebx                              */
    31 #define EBP_OFF 12       /* code restoring ebp/esp relies on */
    32 #define ESP_OFF 16       /* esp being on top of ebp!         */
     28#define ARG_OFF  0
     29#define EBX_OFF  4        /* ebx                              */
     30#define EBP_OFF  8       /* code restoring ebp/esp relies on */
     31#define ESP_OFF 12       /* esp being on top of ebp!         */
    3332#ifdef __SSE__
     33#ifdef RTEMS_SMP
     34#error SMP with SSE support has not been tested. Use at your own risk.
     35#endif
    3436/* need to be on 16 byte boundary for SSE, add 12 to do that */
    3537#define FRM_SIZ (20+12+512)
    3638#define SSE_OFF 32
    3739#else
    38 #define FRM_SIZ 20
     40#define FRM_SIZ 16
    3941#endif
    4042
     
    6062         *         pushed, do not forget to adjust SAVED_REGS.
    6163         *
    62          *  NOTE:  Make sure the exit code which restores these
     64         *  NOTE:  Make sure the Lthread_dispatch_done code restores these
    6365         *         when this type of code is needed.
    6466         */
     
    7375         * Establish an aligned stack frame
    7476         *   original sp
    75          *   saved ebx
    7677         *   saved ebp
    77          *   saved irq mask
     78         *   saved ebx
    7879         *   vector arg to BSP_dispatch_isr   <- aligned SP
    7980         */
    8081        movl      esp, eax
    8182        subl      $FRM_SIZ, esp
    82         andl      $ - CPU_STACK_ALIGNMENT, esp
    83         movl      ebx, EBX_OFF(esp)
    8483        movl      eax, ESP_OFF(esp)
    8584        movl      ebp, EBP_OFF(esp)
     85        movl      ebx, EBX_OFF(esp)
    8686
    8787        /*
     
    101101         * call other C-code (besides the ISR, namely _Thread_Dispatch())
    102102         */
    103     /*  don't wait here; a possible exception condition will eventually be
    104     *  detected when the task resumes control and executes a FP instruction
     103        /*  don't wait here; a possible exception condition will eventually be
     104        *  detected when the task resumes control and executes a FP instruction
    105105        fwait
    106     */
     106        */
    107107        fxsave SSE_OFF(esp)
    108108        fninit                          /* clean-slate FPU                */
     
    119119.check_stack_switch:
    120120        movl      esp, ebp                  /* ebp = previous stack pointer */
    121 
    122 #ifdef RTEMS_SMP
    123         call      SYM(_CPU_SMP_Get_current_processor)
    124         sall      $PER_CPU_CONTROL_SIZE_LOG2, eax
    125         addl      $SYM(_Per_CPU_Information), eax
    126         movl      eax, ebx
    127 #else
    128         movl      $SYM(_Per_CPU_Information), ebx
    129 #endif
     121        andl      $ - CPU_STACK_ALIGNMENT, esp  /* Make sure esp is 16 byte aligned */
     122
     123        GET_SELF_CPU_CONTROL ebx
    130124
    131125        /* is this the outermost interrupt? */
     
    162156        movl      ebp, esp
    163157
     158        /*
     159         * Thread dispatching is necessary and allowed if and only if
     160         *   dispatch_necessary == 1 and
     161         *   isr_dispatch_disable == 0 and
     162         *   thread_dispatch_disable_level == 0.
     163         *
     164         * Otherwise, continue with .Lthread_dispatch_done
     165         */
     166        movl      PER_CPU_DISPATCH_NEEDED(ebx), eax
     167        xorl      PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(ebx), eax
     168        decl      PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(ebx)
     169        orl       PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(ebx), eax
     170        orl       PER_CPU_ISR_DISPATCH_DISABLE(ebx), eax
    164171        decl      PER_CPU_ISR_NEST_LEVEL(ebx)  /* one less ISR nest level */
    165                                             /* If interrupts are nested, */
    166                                             /*   then dispatching is disabled */
    167 
    168         decl      PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(ebx)
    169                                             /* unnest multitasking */
    170                                             /* Is dispatch disabled */
    171         jne       .exit                     /* Yes, then exit */
    172 
    173         cmpb      $0, PER_CPU_DISPATCH_NEEDED(ebx)
    174                                             /* Is task switch necessary? */
    175         jne       .schedule                 /* Yes, then call the scheduler */
    176         jmp       .exit                     /* No, exit */
    177 
    178 .schedule:
    179         /*
    180          * the scratch registers have already been saved and we are already
    181          * back on the thread system stack. So we can call _Thread_Dispatch
    182          * directly
    183          */
    184         call      _Thread_Dispatch
    185         /*
    186          * fall through exit to restore complete contex (scratch registers
    187          * eip, CS, Flags).
    188          */
    189 .exit:
     172
     173        cmpl      $0, eax
     174        jne       .Lthread_dispatch_done    /* Is task switch necessary? */
     175
     176.Ldo_thread_dispatch:
     177          /* Set ISR dispatch disable and thread dispatch disable level to one */
     178          movl    $1, PER_CPU_ISR_DISPATCH_DISABLE(ebx)
     179          movl    $1, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(ebx)
     180          /* Call Thread_Do_dispatch(), this function will enable interrupts */
     181          push    $EFLAGS_INTR_ENABLE      /* Set interrupt flag manually */
     182          push    ebx
     183          call    _Thread_Do_dispatch
     184
     185      /* Disable interrupts */
     186          cli
     187          addl    $8, esp
     188          /* Sometimes after returning from _Thread_Do_dispatch current CPU and ebx ptr are different */
     189          GET_SELF_CPU_CONTROL ebx
     190          cmpb    $0, PER_CPU_DISPATCH_NEEDED(ebx)
     191          jne     .Ldo_thread_dispatch
     192
     193          /* We are done with thread dispatching */
     194          movl    $0, PER_CPU_ISR_DISPATCH_DISABLE(ebx)
     195         /*
     196          * fall through Lthread_dispatch_done to restore complete contex (scratch registers
     197          * eip, CS, Flags).
     198          */
     199.Lthread_dispatch_done:
    190200
    191201#ifdef __SSE__
  • cpukit/score/cpu/i386/include/rtems/score/cpu.h

    r8937f12 r5d4a1edc  
    265265extern void rtems_exception_init_mngt(void);
    266266
    267 #ifdef RTEMS_SMP
    268   /* Throw compile-time error to indicate incomplete support */
    269   #error "i386 targets do not support SMP.\
    270  See: https://devel.rtems.org/ticket/3335"
    271 
    272   /*
    273    * This size must match the size of the CPU_Interrupt_frame, which must be
    274    * used in the SMP context switch code, which is incomplete at the moment.
    275    */
    276   #define CPU_INTERRUPT_FRAME_SIZE 4
    277 #endif
    278 
    279267/*
    280268 * This port does not pass any frame info to the
     
    283271
    284272typedef struct {
    285   uint32_t todo_replace_with_apt_registers;
     273/* allow for 16B alignment (worst case 12 Bytes more) and isr right after pushfl */
     274  uint32_t reserved[3];
     275/* registers saved by _ISR_Handler */
     276  uint32_t isr_vector;
     277  uint32_t ebx;
     278  uint32_t ebp;
     279  uint32_t esp;
     280/* registers saved by rtems_irq_prologue_##_vector */
     281  uint32_t edx;
     282  uint32_t ecx;
     283  uint32_t eax;
     284/* registers saved by CPU */
     285  uint32_t eip;
     286  uint32_t cs;
     287  uint32_t eflags;
    286288} CPU_Interrupt_frame;
    287289
  • cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h

    r8937f12 r5d4a1edc  
    2929
    3030#define CPU_PER_CPU_CONTROL_SIZE 0
     31
     32#define CPU_INTERRUPT_FRAME_SIZE 52
    3133
    3234#ifndef ASM
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