Changeset 5c7bfcf in rtems


Ignore:
Timestamp:
Nov 11, 2015, 10:49:45 AM (4 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
610909f
Parents:
4fee129
git-author:
Sebastian Huber <sebastian.huber@…> (11/11/15 10:49:45)
git-committer:
Sebastian Huber <sebastian.huber@…> (11/12/15 07:21:45)
Message:

Fix interrupt epilogue for ARMv7-AR and PowerPC

Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S

    r4fee129 r5c7bfcf  
    3030#define FRAME_REGISTER r14
    3131
    32 #define VECTOR_OFFSET(reg) GPR4_OFFSET(reg)
    33 #define SELF_CPU_OFFSET(reg) GPR5_OFFSET(reg)
    34 #define ISR_NEST_OFFSET(reg) GPR6_OFFSET(reg)
    35 #define DISPATCH_LEVEL_OFFSET(reg) GPR7_OFFSET(reg)
    36 #define HANDLER_OFFSET(reg) GPR8_OFFSET(reg)
    37 #define SCRATCH_0_OFFSET(reg) GPR0_OFFSET(reg)
    38 #define SCRATCH_1_OFFSET(reg) GPR3_OFFSET(reg)
    39 #define SCRATCH_2_OFFSET(reg) GPR9_OFFSET(reg)
    40 #define SCRATCH_3_OFFSET(reg) GPR10_OFFSET(reg)
    41 #define SCRATCH_4_OFFSET(reg) GPR11_OFFSET(reg)
    42 #define SCRATCH_5_OFFSET(reg) GPR12_OFFSET(reg)
     32#define VECTOR_OFFSET GPR4_OFFSET
     33#define SELF_CPU_OFFSET GPR5_OFFSET
     34#define ISR_NEST_OFFSET GPR6_OFFSET
     35#define DISPATCH_LEVEL_OFFSET GPR7_OFFSET
     36#define HANDLER_OFFSET GPR8_OFFSET
     37#define SCRATCH_0_OFFSET GPR0_OFFSET
     38#define SCRATCH_1_OFFSET GPR3_OFFSET
     39#define SCRATCH_2_OFFSET GPR9_OFFSET
     40#define SCRATCH_3_OFFSET GPR10_OFFSET
     41#define SCRATCH_4_OFFSET GPR11_OFFSET
     42#define SCRATCH_5_OFFSET GPR12_OFFSET
    4343
    4444/*
    4545 * The register 2 slot is free, since this is the read-only small data anchor.
    4646 */
    47 #define FRAME_OFFSET(reg) GPR2_OFFSET(reg)
     47#define FRAME_OFFSET GPR2_OFFSET
    4848
    4949#ifdef RTEMS_PROFILING
     
    5252 */
    5353#define ENTRY_INSTANT_REGISTER r15
    54 #define ENTRY_INSTANT_OFFSET(reg) GPR13_OFFSET(reg)
     54#define ENTRY_INSTANT_OFFSET GPR13_OFFSET
    5555
    5656.macro GET_TIME_BASE REG
     
    400400#endif
    401401
     402        /*
     403         * We must clear reservations here, since otherwise compare-and-swap
     404         * atomic operations with interrupts enabled may yield wrong results.
     405         * A compare-and-swap atomic operation is generated by the compiler
     406         * like this:
     407         *
     408         *   .L1:
     409         *     lwarx  r9, r0, r3
     410         *     cmpw   r9, r4
     411         *     bne-   .L2
     412         *     stwcx. r5, r0, r3
     413         *     bne-   .L1
     414         *   .L2:
     415         *
     416         * Consider the following scenario.  A thread is interrupted right
     417         * before the stwcx.  The interrupt updates the value using a
     418         * compare-and-swap sequence.  Everything is fine up to this point.
     419         * The interrupt performs now a compare-and-swap sequence which fails
     420         * with a branch to .L2.  The current processor has now a reservation.
     421         * The interrupt returns without further stwcx.  The thread updates the
     422         * value using the unrelated reservation of the interrupt.
     423         */
     424        li      SCRATCH_0_REGISTER, FRAME_OFFSET
     425        stwcx.  SCRATCH_0_REGISTER, r1, SCRATCH_0_REGISTER
     426
    402427        /* Load SRR0, SRR1, CR, CTR, XER, and LR */
    403428        lwz     SCRATCH_0_REGISTER, SRR0_FRAME_OFFSET(r1)
  • cpukit/score/cpu/arm/arm_exc_interrupt.S

    r4fee129 r5c7bfcf  
    210210        ldmia   sp!, {EXCHANGE_LR, EXCHANGE_SPSR}
    211211
     212#ifdef ARM_MULTILIB_HAS_LOAD_STORE_EXCLUSIVE
     213        /*
     214         * We must clear reservations here, since otherwise compare-and-swap
     215         * atomic operations with interrupts enabled may yield wrong results.
     216         * A compare-and-swap atomic operation is generated by the compiler
     217         * like this:
     218         *
     219         *   .L1:
     220         *     ldrex r1, [r0]
     221         *     cmp   r1, r3
     222         *     bne   .L2
     223         *     strex r3, r2, [r0]
     224         *     cmp   r3, #0
     225         *     bne   .L1
     226         *   .L2:
     227         *
     228         * Consider the following scenario.  A thread is interrupted right
     229         * before the strex.  The interrupt updates the value using a
     230         * compare-and-swap sequence.  Everything is fine up to this point.
     231         * The interrupt performs now a compare-and-swap sequence which fails
     232         * with a branch to .L2.  The current processor has now a reservation.
     233         * The interrupt returns without further strex.  The thread updates the
     234         * value using the unrelated reservation of the interrupt.
     235         */
     236        clrex
     237#endif
     238
    212239        /* Return from interrupt */
    213240        subs    pc, lr, #4
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