Changeset 5bb38e15 in rtems


Ignore:
Timestamp:
Dec 4, 2009, 5:25:30 AM (9 years ago)
Author:
Ralf Corsepius <ralf.corsepius@…>
Branches:
4.10, 4.11, master
Children:
10f4120
Parents:
42e243e
Message:

Whitespace removal.

Location:
cpukit/score/cpu
Files:
37 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/arm/arm_exc_handler_high.c

    r42e243e r5bb38e15  
    4545#if 0
    4646    printk(" r0  = %8x  r1  = %8x  r2  = %8x  r3  = %8x\n\r",
    47            ctx->register_r0, ctx->register_r1, 
     47           ctx->register_r0, ctx->register_r1,
    4848           ctx->register_r2, ctx->register_r3);
    4949    printk(" r4  = %8x  r5  = %8x  r6  = %8x  r7  = %8x\n\r",
    50            ctx->register_r4, ctx->register_r5, 
     50           ctx->register_r4, ctx->register_r5,
    5151           ctx->register_r6, ctx->register_r7);
    5252    printk(" r8  = %8x  r9  = %8x  r10 = %8x\n\r",
    5353           ctx->register_r8, ctx->register_r9, ctx->register_r10);
    5454    printk(" fp  = %8x  ip  = %8x  sp  = %8x  pc  = %8x\n\r",
    55            ctx->register_fp, ctx->register_ip, 
     55           ctx->register_fp, ctx->register_ip,
    5656           ctx->register_sp, ctx->register_lr - 4);
    5757    printk("----------------------------------------------------------\n\r");
    58 #endif   
     58#endif
    5959    if (_ISR_Nest_level > 0) {
    6060        /*
     
    7676cpuExcHandlerType _currentExcHandler = _defaultExcHandler;
    7777
    78 extern void _Exception_Handler_Undef_Swi(void); 
    79 extern void _Exception_Handler_Abort(void); 
    80 extern void _exc_data_abort(void); 
     78extern void _Exception_Handler_Undef_Swi(void);
     79extern void _Exception_Handler_Abort(void);
     80extern void _exc_data_abort(void);
    8181
    8282
     
    8686{
    8787        ISR_Level level;
    88      
     88
    8989      _CPU_ISR_Disable(level);
    9090      _CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF,
    9191                              _Exception_Handler_Undef_Swi,
    9292                              NULL);
    93  
     93
    9494      _CPU_ISR_install_vector(ARM_EXCEPTION_SWI,
    9595                              _Exception_Handler_Undef_Swi,
    9696                              NULL);
    97      
     97
    9898      _CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT,
    9999                              _Exception_Handler_Abort,
    100100                              NULL);
    101      
     101
    102102      _CPU_ISR_install_vector(ARM_EXCEPTION_DATA_ABORT,
    103103                              _exc_data_abort,
    104104                              NULL);
    105      
    106       _CPU_ISR_install_vector(ARM_EXCEPTION_FIQ,       
     105
     106      _CPU_ISR_install_vector(ARM_EXCEPTION_FIQ,
    107107                              _Exception_Handler_Abort,
    108108                              NULL);
    109      
    110       _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, 
     109
     110      _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ,
    111111                              _Exception_Handler_Abort,
    112112                              NULL);
    113      
     113
    114114      _CPU_ISR_Enable(level);
    115115}
  • cpukit/score/cpu/arm/arm_exc_handler_low.S

    r42e243e r5bb38e15  
    6464        ldr     lr,  [r13, #REG_LR]
    6565        add     r13,r13,#SIZE_REGS
    66         movs    pc,r14                  /* return  */ 
     66        movs    pc,r14                  /* return  */
    6767       
    6868/* FIXME:       _Exception_Handler_Abort is untested */
  • cpukit/score/cpu/arm/cpu.c

    r42e243e r5bb38e15  
    9494{
    9595  /* Redirection table starts at the end of the vector table */
    96   volatile uint32_t *table = (volatile uint32_t *) (MAX_EXCEPTIONS * 4); 
     96  volatile uint32_t *table = (volatile uint32_t *) (MAX_EXCEPTIONS * 4);
    9797
    9898  uint32_t current_handler = table [vector];
    99  
     99
    100100  /* The current handler is now the old one */
    101101  if (old_handler != NULL) {
  • cpukit/score/cpu/arm/cpu_asm.S

    r42e243e r5bb38e15  
    3838 *  Using the ldm/stm opcodes save 2-3 us on 100 MHz ARM9TDMI with
    3939 *  a 16 bit data bus.
    40  *       
     40 *
    4141 */
    42  
     42
    4343DEFINE_FUNCTION_ARM(_CPU_Context_switch)
    4444/* Start saving context */
     
    4848
    4949/* Start restoring context */
    50 _restore:       
     50_restore:
    5151        ldmia   r1,  {r2, r4, r5, r6, r7, r8, r9, r10, r11, r13, r14}
    5252        msr     cpsr, r2
  • cpukit/score/cpu/arm/rtems/asm.h

    r42e243e r5bb38e15  
    1212 *        is critical to them working as advertised.
    1313 */
    14  
     14
    1515/*
    1616 *  COPYRIGHT:
     
    9797#define NUM_IRQ_VECTOR          6       // IRQ number
    9898#define NUM_FIQ_VECTOR          7       // IRQ number
    99                                                                                 //                                                                              // 
     99                                                                                //                                                                              //
    100100#define CPSR_IRQ_DISABLE        0x80    // FIQ disabled when =1
    101101#define CPSR_FIQ_DISABLE        0x40    // FIQ disabled when =1
  • cpukit/score/cpu/arm/rtems/score/arm.h

    r42e243e r5bb38e15  
    33 */
    44
    5 /* 
     5/*
    66 *  $Id$
    77 *
  • cpukit/score/cpu/h8300/cpu.c

    r42e243e r5bb38e15  
    4242 *  This routine returns the current interrupt level.
    4343 */
    44  
     44
    4545uint32_t   _CPU_ISR_Get_level( void )
    4646{
     
    6262 *  _CPU_ISR_install_raw_handler
    6363 */
    64  
     64
    6565void _CPU_ISR_install_raw_handler(
    6666  uint32_t    vector,
  • cpukit/score/cpu/h8300/cpu_asm.S

    r42e243e r5bb38e15  
    44 *
    55 *  Based on example code and other ports with this copyright:
    6  * 
     6 *
    77 *  COPYRIGHT (c) 1989-1999.
    88 *  On-Line Applications Research Corporation (OAR).
    9  * 
     9 *
    1010 *  The license and distribution terms for this file may be
    1111 *  found in the file LICENSE in this distribution or at
    1212 *  http://www.rtems.com/license/LICENSE.
    13  * 
     13 *
    1414 *  $Id$
    1515 */
     
    1919;.equ   HEIRCONTEXT_ARG, er1
    2020       
    21 /*     
     21/*
    2222 *  Make sure we tell the assembler what type of CPU model we are
    2323 *  being compiled for.
    24  */ 
     24 */
    2525
    2626#if defined(__H8300H__)
    2727        .h8300h
    2828#endif
    29 #if defined(__H8300S__) 
     29#if defined(__H8300S__)
    3030        .h8300s
    3131#endif
    32 #if defined(__H8300SX__) 
     32#if defined(__H8300SX__)
    3333        .h8300sx
    3434#endif
     
    122122        mov.l   er6,@-er7       ; save sp so pop regardless of nest level
    123123       
    124 ;; Inc  system counters 
     124;; Inc  system counters
    125125        mov.l   @__ISR_Nest_level,er1
    126126        inc.l   #1,er1
  • cpukit/score/cpu/h8300/rtems/asm.h

    r42e243e r5bb38e15  
    2020 *  of the file is noted.  This file is:
    2121 *
    22  * 
     22 *
    2323 *  COPYRIGHT (c) 1989-1999.
    2424 *  On-Line Applications Research Corporation (OAR).
    25  * 
     25 *
    2626 *  The license and distribution terms for this file may be
    2727 *  found in the file LICENSE in this distribution or at
    2828 *  http://www.rtems.com/license/LICENSE.
    29  * 
     29 *
    3030 *  $Id$
    3131 */
  • cpukit/score/cpu/h8300/rtems/score/cpu.h

    r42e243e r5bb38e15  
    275275 *
    276276 *  XXX
    277  *  The port initially called a BSP dependent routine called 
     277 *  The port initially called a BSP dependent routine called
    278278 *  IDLE_Monitor.  The idle task body can be overridden by
    279279 *  the BSP in newer versions of RTEMS.
     
    485485 */
    486486
    487 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 
     487#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
    488488
    489489/*
     
    643643 *  H8300 Specific Information:
    644644 *
    645  *  XXX 
     645 *  XXX
    646646 */
    647647
     
    653653             : "=m" (__ccr) /* : "0" (__ccr) */ ); \
    654654    (_isr_cookie) = __ccr; \
    655   } while (0) 
     655  } while (0)
    656656#else
    657657#define _CPU_ISR_Disable( _isr_cookie ) (_isr_cookie) = 0
     
    674674    unsigned char __ccr = (unsigned char) (_isr_cookie); \
    675675    asm volatile( "ldc %0, ccr" :  : "m" (__ccr) ); \
    676   } while (0) 
     676  } while (0)
    677677#else
    678678#define _CPU_ISR_Enable( _isr_cookie )
     
    695695    unsigned char __ccr = (unsigned char) (_isr_cookie); \
    696696    asm volatile( "ldc %0, ccr ; orc #0x80,ccr " :  : "m" (__ccr) ); \
    697   } while (0) 
     697  } while (0)
    698698#else
    699699#define _CPU_ISR_Flash( _isr_cookie )
     
    853853#define _CPU_Fatal_halt( _error ) \
    854854        printk("Fatal Error %d Halted\n",_error); \
    855         for(;;) 
    856  
     855        for(;;)
     856
    857857
    858858/* end of Fatal Error manager macros */
     
    987987 *  _CPU_ISR_install_raw_handler
    988988 *
    989  *  This routine installs a "raw" interrupt handler directly into the 
     989 *  This routine installs a "raw" interrupt handler directly into the
    990990 *  processor's vector table.
    991991 *
     
    994994 *  XXX
    995995 */
    996  
     996
    997997void _CPU_ISR_install_raw_handler(
    998998  uint32_t    vector,
     
    11301130 *  This is the generic implementation.
    11311131 */
    1132  
     1132
    11331133static inline uint32_t   CPU_swap_u32(
    11341134  uint32_t   value
     
    11361136{
    11371137  uint32_t   byte1, byte2, byte3, byte4, swapped;
    1138  
     1138
    11391139  byte4 = (value >> 24) & 0xff;
    11401140  byte3 = (value >> 16) & 0xff;
    11411141  byte2 = (value >> 8)  & 0xff;
    11421142  byte1 =  value        & 0xff;
    1143  
     1143
    11441144  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
    11451145  return( swapped );
  • cpukit/score/cpu/h8300/rtems/score/h8300.h

    r42e243e r5bb38e15  
    4141#endif
    4242
    43 #endif 
     43#endif
  • cpukit/score/cpu/m32c/varvects.S

    r42e243e r5bb38e15  
    44All rights reserved.
    55
    6 Redistribution and use in source and binary forms, with or without 
    7 modification, are permitted provided that the following conditions are met: 
     6Redistribution and use in source and binary forms, with or without
     7modification, are permitted provided that the following conditions are met:
    88
    9     Redistributions of source code must retain the above copyright 
     9    Redistributions of source code must retain the above copyright
    1010    notice, this list of conditions and the following disclaimer.
    1111
     
    1414    documentation and/or other materials provided with the distribution.
    1515
    16     The name of Red Hat Incorporated may not be used to endorse 
    17     or promote products derived from this software without specific 
     16    The name of Red Hat Incorporated may not be used to endorse
     17    or promote products derived from this software without specific
    1818    prior written permission.
    1919
    20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
    21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
     20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
    2222IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
    2323DISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
    2424DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
    2525(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
    26 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 
     26LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
    2727ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    2828(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
    29 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
     29SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    3030
    3131*/
  • cpukit/score/cpu/m32r/cpu.c

    r42e243e r5bb38e15  
    3737 *  XXX document implementation including references if appropriate
    3838 */
    39  
     39
    4040uint32_t   _CPU_ISR_Get_level( void )
    4141{
     
    5151 *  XXX document implementation including references if appropriate
    5252 */
    53  
     53
    5454void _CPU_ISR_install_raw_handler(
    5555  uint32_t    vector,
  • cpukit/score/cpu/m32r/cpu_asm.c

    r42e243e r5bb38e15  
    8585   *  LABEL "exit interrupt (simple case):
    8686   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
    87    *    if outermost interrupt 
     87   *    if outermost interrupt
    8888   *      restore stack
    8989   *  #endif
  • cpukit/score/cpu/m32r/rtems/score/cpu.h

    r42e243e r5bb38e15  
    1414 *  + Anywhere there is an XXX, it should be replaced
    1515 *    with information about the CPU family being ported to.
    16  * 
     16 *
    1717 *  + At the end of each comment section, there is a heading which
    1818 *    says "Port Specific Information:".  When porting to RTEMS,
     
    169169/**
    170170 *  Does the RTEMS invoke the user's ISR with the vector number and
    171  *  a pointer to the saved interrupt frame (1) or just the vector 
     171 *  a pointer to the saved interrupt frame (1) or just the vector
    172172 *  number (0)?
    173173 *
     
    196196 */
    197197
    198 /** 
     198/**
    199199 *  @def CPU_SOFTWARE_FP
    200200 *
     
    204204 *
    205205 *  This feature conditional is used to indicate whether or not there
    206  *  is software implemented floating point that must be context 
     206 *  is software implemented floating point that must be context
    207207 *  switched.  The determination of whether or not this applies
    208208 *  is very tool specific and the state saved/restored is also
     
    495495 *
    496496 *  @param[in] _context is the thread context area to access
    497  * 
     497 *
    498498 *  @return This method returns the stack pointer.
    499499 */
     
    518518 */
    519519typedef struct {
    520     /** This field is a hint that a port will have a number of integer 
     520    /** This field is a hint that a port will have a number of integer
    521521     *  registers that need to be saved when an interrupt occurs or
    522522     *  when a context switch occurs at the end of an ISR.
     
    558558/**
    559559 *  @ingroup CPUInterrupt
    560  *  This variable points to the lowest physical address of the interrupt 
     560 *  This variable points to the lowest physical address of the interrupt
    561561 *  stack.
    562562 */
     
    565565/**
    566566 *  @ingroup CPUInterrupt
    567  *  This variable points to the lowest physical address of the interrupt 
     567 *  This variable points to the lowest physical address of the interrupt
    568568 *  stack.
    569569 */
     
    659659 *  @note  This does not have to be a power of 2 although it should be
    660660 *         a multiple of 2 greater than or equal to 2.  The requirement
    661  *         to be a multiple of 2 is because the heap uses the least 
     661 *         to be a multiple of 2 is because the heap uses the least
    662662 *         significant field of the front and back flags to indicate
    663663 *         that a block is in use or free.  So you do not want any odd
     
    940940 *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
    941941 *
    942  *  This set of routines are used to implement fast searches for 
     942 *  This set of routines are used to implement fast searches for
    943943 *  the most important ready task.
    944944 */
     
    965965 *  @ingroup CPUBitfield
    966966 *  This routine sets @a _output to the bit number of the first bit
    967  *  set in @a _value.  @a _value is of CPU dependent type 
     967 *  set in @a _value.  @a _value is of CPU dependent type
    968968 *  @a Priority_Bit_map_control.  This type may be either 16 or 32 bits
    969969 *  wide although only the 16 least significant bits will be used.
     
    10081008          _value >>=8
    10091009          _number = 8;
    1010  
     1010
    10111011        if _value > 0x0000f
    10121012          _value >=8
    10131013          _number += 4
    1014  
     1014
    10151015        _number += bit_set_table[ _value ]
    10161016@endverbatim
    1017  
     1017
    10181018 *    where bit_set_table[ 16 ] has values which indicate the first
    10191019 *      bit set
     
    10871087/**
    10881088 *  @ingroup CPUInterrupt
    1089  *  This routine installs a "raw" interrupt handler directly into the 
     1089 *  This routine installs a "raw" interrupt handler directly into the
    10901090 *  processor's vector table.
    10911091 *
     
    12371237{
    12381238  uint32_t byte1, byte2, byte3, byte4, swapped;
    1239  
     1239
    12401240  byte4 = (value >> 24) & 0xff;
    12411241  byte3 = (value >> 16) & 0xff;
    12421242  byte2 = (value >> 8)  & 0xff;
    12431243  byte1 =  value        & 0xff;
    1244  
     1244
    12451245  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
    12461246  return swapped;
  • cpukit/score/cpu/m32r/rtems/score/m32r.h

    r42e243e r5bb38e15  
    11/*
    2  *  This file sets up basic CPU dependency settings based on 
     2 *  This file sets up basic CPU dependency settings based on
    33 *  compiler settings.  For example, it can determine if
    44 *  floating point is available.  This particular implementation
     
    3333 *  to.
    3434 */
    35  
     35
    3636#if defined(rtems_multilib)
    3737/*
    38  *  Figure out all CPU Model Feature Flags based upon compiler 
    39  *  predefines. 
     38 *  Figure out all CPU Model Feature Flags based upon compiler
     39 *  predefines.
    4040 */
    4141
     
    4444
    4545#elif defined(__m32r__)
    46  
     46
    4747#define CPU_MODEL_NAME  "m32r"
    4848#define NOCPU_HAS_FPU     1
    49  
     49
    5050#else
    51  
     51
    5252#error "Unsupported CPU Model"
    53  
     53
    5454#endif
    5555
  • cpukit/score/cpu/m68k/cpu.c

    r42e243e r5bb38e15  
    5050 *  _CPU_ISR_Get_level
    5151 */
    52  
     52
    5353uint32_t   _CPU_ISR_Get_level( void )
    5454{
     
    6464 *  _CPU_ISR_install_raw_handler
    6565 */
    66  
     66
    6767void _CPU_ISR_install_raw_handler(
    6868  uint32_t    vector,
     
    8989   *  On CPU models without a VBR, it is necessary for there to be some
    9090   *  header code for each ISR which saves a register, loads the vector
    91    *  number, and jumps to _ISR_Handler. 
     91   *  number, and jumps to _ISR_Handler.
    9292   */
    9393
  • cpukit/score/cpu/m68k/rtems/m68k/m68302.h

    r42e243e r5bb38e15  
    228228 * structures in the parameter RAM.
    229229 *
    230  * Access to the DRAM registers can be accomplished by 
     230 * Access to the DRAM registers can be accomplished by
    231231 * the following approach:
    232232 *
     
    600600
    601601/* some useful defines the some of the registers above */
    602  
     602
    603603
    604604/* ----
  • cpukit/score/cpu/m68k/rtems/m68k/qsm.h

    r42e243e r5bb38e15  
    1515 * For more information, refer to Motorola's "Modular Microcontroller
    1616 * Family Queued Serial Module Reference Manual" (Motorola document
    17  * QSMRM/AD). 
     17 * QSMRM/AD).
    1818 *
    1919 * This file was created by John S. Gwynne to support Motorola's 68332 MCU.
    20  * 
     20 *
    2121 * Redistribution and use in source and binary forms are permitted
    2222 * provided that the following conditions are met:
     
    5454#define SIM_MM 1
    5555#define QSM_CRB 0xfffc00
    56 #endif 
     56#endif
    5757
    5858
  • cpukit/score/cpu/m68k/rtems/m68k/sim.h

    r42e243e r5bb38e15  
    1313 *  and external devices.
    1414 *
    15  *  () The generation of chip-select signals that simplify external 
     15 *  () The generation of chip-select signals that simplify external
    1616 *  circuitry interface.
    1717 *
     
    2323 * For more information, refer to Motorola's "Modular Microcontroller
    2424 * Family System Integration Module Reference Manual" (Motorola document
    25  * SIMRM/AD). 
     25 * SIMRM/AD).
    2626 *
    2727 * This file was created by John S. Gwynne to support Motorola's 68332 MCU.
    28  * 
     28 *
    2929 * Redistribution and use in source and binary forms are permitted
    3030 * provided that the following conditions are met:
     
    216216   1 always reads one; writes to CSPAR0 bit 1 have no effect. */
    217217#define CSPAR1 SIM_VOLATILE_USHORT_POINTER(0x46 + SIM_CRB)
    218                                 /* Chip Select Pin Assignment 
     218                                /* Chip Select Pin Assignment
    219219                                   Register 1 */
    220220/* CSPAR1 contains five two-bit fields that determine the finctions of
  • cpukit/score/cpu/m68k/rtems/score/cpu.h

    r42e243e r5bb38e15  
    6767/*
    6868 *  Does the RTEMS invoke the user's ISR with the vector number and
    69  *  a pointer to the saved interrupt frame (1) or just the vector 
     69 *  a pointer to the saved interrupt frame (1) or just the vector
    7070 *  number (0)?
    7171 */
     
    312312SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
    313313
    314 extern void*                     _VBR; 
     314extern void*                     _VBR;
    315315
    316316#if ( M68K_HAS_VBR == 0 )
     
    337337
    338338      /* points to jsr-exception-table in targets wo/ VBR register */
    339 SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256]; 
     339SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256];
    340340
    341341#endif /* M68K_HAS_VBR */
     
    660660 *  _CPU_ISR_install_raw_handler
    661661 *
    662  *  This routine installs a "raw" interrupt handler directly into the 
     662 *  This routine installs a "raw" interrupt handler directly into the
    663663 *  processor's vector table.
    664664 */
    665  
     665
    666666void _CPU_ISR_install_raw_handler(
    667667  uint32_t    vector,
     
    725725 *  Hooks for the Floating Point Support Package (FPSP) provided by Motorola
    726726 *
    727  *  NOTES: 
     727 *  NOTES:
    728728 *
    729729 *  Motorola 68k family CPU's before the 68040 used a coprocessor
  • cpukit/score/cpu/m68k/rtems/score/m68k.h

    r42e243e r5bb38e15  
    7272 *
    7373 *  M68K_HAS_EXTB_L is used to enable/disable usage of the extb.l instruction
    74  *  which is not available for 68000 or 68ec000 cores (68000, 68001, 68008, 
     74 *  which is not available for 68000 or 68ec000 cores (68000, 68001, 68008,
    7575 *  68010, 68302, 68306, 68307).  This instruction is available on the 68020
    76  *  up and the cpu32 based models. 
     76 *  up and the cpu32 based models.
    7777 *
    7878 *  M68K_HAS_MISALIGNED is non-zero if the CPU allows byte-misaligned
     
    9292
    9393# if defined(__mcfisaa__)
    94 /* Motorola ColdFire ISA A */ 
     94/* Motorola ColdFire ISA A */
    9595# define CPU_MODEL_NAME         "mcfisaa"
    9696# define M68K_HAS_VBR             1
     
    102102
    103103# elif defined(__mcfisaaplus__)
    104 /* Motorola ColdFire ISA A+ */ 
     104/* Motorola ColdFire ISA A+ */
    105105# define CPU_MODEL_NAME         "mcfisaaplus"
    106106# define M68K_HAS_VBR             1
     
    112112
    113113# elif defined(__mcfisab__)
    114 /* Motorola ColdFire ISA B */ 
     114/* Motorola ColdFire ISA B */
    115115# define CPU_MODEL_NAME         "mcfisab"
    116116# define M68K_HAS_VBR             1
     
    170170
    171171/*
    172  *  Figure out all CPU Model Feature Flags based upon compiler 
    173  *  predefines.   Notice the only exception to this is that 
     172 *  Figure out all CPU Model Feature Flags based upon compiler
     173 *  predefines.   Notice the only exception to this is that
    174174 *  gcc does not distinguish between CPU32 and CPU32+.  This
    175175 *  feature selection logic is setup such that if RTEMS__mcpu32p__
     
    182182/*
    183183 * One stack size fits all 68000 processors.
    184  */ 
     184 */
    185185# define M68K_CPU_STACK_MINIMUM_SIZE 4096
    186186
     
    201201#  define M68K_HAS_FPSP_PACKAGE   0
    202202#  endif
    203  
     203
    204204# elif defined(__mc68030__)
    205  
     205
    206206# define CPU_MODEL_NAME          "m68030"
    207207# define M68K_HAS_VBR             1
     
    218218#  define M68K_HAS_FPSP_PACKAGE   0
    219219#  endif
    220  
     220
    221221# elif defined(__mc68040__)
    222222
     
    235235#  define M68K_HAS_FPSP_PACKAGE   0
    236236#  endif
    237  
     237
    238238# elif defined(__mc68060__)
    239239
     
    252252#  define M68K_HAS_FPSP_PACKAGE   0
    253253#  endif
    254  
     254
    255255# elif defined(__mc68302__)
    256256
     
    267267  /* gcc and egcs do not distinguish between CPU32 and CPU32+ */
    268268# elif defined(RTEMS__mcpu32p__)
    269  
     269
    270270# define CPU_MODEL_NAME          "mcpu32+"
    271271# define M68K_HAS_VBR             1
     
    279279
    280280# elif defined(__mcpu32__)
    281  
     281
    282282# define CPU_MODEL_NAME          "mcpu32"
    283283# define M68K_HAS_VBR             1
     
    291291
    292292# elif defined(__mc68000__)
    293  
     293
    294294# define CPU_MODEL_NAME          "m68000"
    295295# define M68K_HAS_VBR             0
     
    377377    _level = (_tmpsr & 0x0700) >> 8; \
    378378  } while (0)
    379    
     379
    380380#define m68k_set_interrupt_level( _newlevel ) \
    381381  do { \
     
    395395
    396396#elif ( defined(__mcoldfire__) )
    397 extern void*                     _VBR; 
     397extern void*                     _VBR;
    398398#define m68k_get_vbr( _vbr ) _vbr = &_VBR
    399399
     
    403403    _VBR = (void *)_vbr; \
    404404  } while(0)
    405  
     405
    406406#else
    407407#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR
     
    430430{
    431431  uint32_t   byte1, byte2, byte3, byte4, swapped;
    432    
     432
    433433  byte4 = (value >> 24) & 0xff;
    434434  byte3 = (value >> 16) & 0xff;
    435435  byte2 = (value >> 8)  & 0xff;
    436436  byte1 =  value        & 0xff;
    437            
     437
    438438  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
    439439  return( swapped );
    440440}
    441  
     441
    442442static inline uint16_t m68k_swap_u16(
    443443  uint16_t value
     
    446446  return (((value & 0xff) << 8) | ((value >> 8) & 0xff));
    447447}
    448                  
     448
    449449#else
    450450
     
    485485 *      This function is used to map virtual addresses to physical
    486486 *      addresses.
    487  * 
     487 *
    488488 *      FIXME: ASSUMES THAT VIRTUAL ADDRESSES ARE THE SAME AS THE
    489489 *      PHYSICAL ADDRESSES
  • cpukit/score/cpu/mips/cpu.c

    r42e243e r5bb38e15  
    99 *
    1010 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
    11  *           Joel Sherrill <joel@OARcorp.com>. 
     11 *           Joel Sherrill <joel@OARcorp.com>.
    1212 *
    1313 *    These changes made the code conditional on standard cpp predefines,
     
    3030 *             advertising or publicity pertaining to distribution of the
    3131 *             software without specific, written prior permission.
    32  *             Transition Networks makes no representations about the 
     32 *             Transition Networks makes no representations about the
    3333 *             suitability of this software for any purpose.
    3434 *
     
    5050
    5151
    52 /* 
    53 ** Exception stack frame pointer used in cpu_asm to pass the exception stack frame 
     52/*
     53** Exception stack frame pointer used in cpu_asm to pass the exception stack frame
    5454** address to the context switch code.
    5555*/
    5656#if (__mips == 1) || (__mips == 32)
    5757typedef uint32_t ESF_PTR_TYPE;
    58 #elif (__mips == 3) 
     58#elif (__mips == 3)
    5959typedef uint64_t ESF_PTR_TYPE;
    6060#else
     
    6262#endif
    6363
    64 ESF_PTR_TYPE __exceptionStackFrame = 0; 
     64ESF_PTR_TYPE __exceptionStackFrame = 0;
    6565
    6666
     
    125125  unsigned int sr, srbits;
    126126
    127   /* 
    128   ** mask off the int level bits only so we can 
     127  /*
     128  ** mask off the int level bits only so we can
    129129  ** preserve software int settings and FP enable
    130130  ** for this thread.  Note we don't force software ints
    131131  ** enabled when changing level, they were turned on
    132   ** when this task was created, but may have been turned 
     132  ** when this task was created, but may have been turned
    133133  ** off since, so we'll just leave them alone.
    134134  */
     
    159159  }
    160160*/
    161  
     161
    162162#elif __mips == 1
    163163  mips_set_sr( (sr & ~SR_IEC) );
     
    185185 *
    186186 */
    187  
     187
    188188void _CPU_ISR_install_raw_handler(
    189189  uint32_t    vector,
  • cpukit/score/cpu/mips/cpu_asm.S

    r42e243e r5bb38e15  
    2020 *             of this software for any purpose.
    2121 *    2000: Reworked by Alan Cudmore <alanc@linuxstart.com> to become
    22  *          the baseline of the more general MIPS port. 
     22 *          the baseline of the more general MIPS port.
    2323 *    2001: Joel Sherrill <joel@OARcorp.com> continued this rework,
    2424 *          rewriting as much as possible in C and added the JMR3904 BSP
     
    4040 *          problems that caused fpu code to always be included even when no
    4141 *          fpu is present.
    42  * 
     42 *
    4343 *  COPYRIGHT (c) 1989-2002.
    4444 *  On-Line Applications Research Corporation (OAR).
     
    161161
    162162/* NOTE: these constants must match the Context_Control_fp structure in cpu.h */
    163 #define FP0_OFFSET  0 
    164 #define FP1_OFFSET  1 
    165 #define FP2_OFFSET  2 
    166 #define FP3_OFFSET  3 
    167 #define FP4_OFFSET  4 
    168 #define FP5_OFFSET  5 
    169 #define FP6_OFFSET  6 
    170 #define FP7_OFFSET  7 
    171 #define FP8_OFFSET  8 
    172 #define FP9_OFFSET  9 
    173 #define FP10_OFFSET 10 
    174 #define FP11_OFFSET 11 
    175 #define FP12_OFFSET 12 
    176 #define FP13_OFFSET 13 
    177 #define FP14_OFFSET 14 
    178 #define FP15_OFFSET 15 
    179 #define FP16_OFFSET 16 
    180 #define FP17_OFFSET 17 
    181 #define FP18_OFFSET 18 
    182 #define FP19_OFFSET 19 
    183 #define FP20_OFFSET 20 
    184 #define FP21_OFFSET 21 
    185 #define FP22_OFFSET 22 
    186 #define FP23_OFFSET 23 
    187 #define FP24_OFFSET 24 
    188 #define FP25_OFFSET 25 
    189 #define FP26_OFFSET 26 
    190 #define FP27_OFFSET 27 
    191 #define FP28_OFFSET 28 
    192 #define FP29_OFFSET 29 
    193 #define FP30_OFFSET 30 
    194 #define FP31_OFFSET 31 
     163#define FP0_OFFSET  0
     164#define FP1_OFFSET  1
     165#define FP2_OFFSET  2
     166#define FP3_OFFSET  3
     167#define FP4_OFFSET  4
     168#define FP5_OFFSET  5
     169#define FP6_OFFSET  6
     170#define FP7_OFFSET  7
     171#define FP8_OFFSET  8
     172#define FP9_OFFSET  9
     173#define FP10_OFFSET 10
     174#define FP11_OFFSET 11
     175#define FP12_OFFSET 12
     176#define FP13_OFFSET 13
     177#define FP14_OFFSET 14
     178#define FP15_OFFSET 15
     179#define FP16_OFFSET 16
     180#define FP17_OFFSET 17
     181#define FP18_OFFSET 18
     182#define FP19_OFFSET 19
     183#define FP20_OFFSET 20
     184#define FP21_OFFSET 21
     185#define FP22_OFFSET 22
     186#define FP23_OFFSET 23
     187#define FP24_OFFSET 24
     188#define FP25_OFFSET 25
     189#define FP26_OFFSET 26
     190#define FP27_OFFSET 27
     191#define FP28_OFFSET 28
     192#define FP29_OFFSET 29
     193#define FP30_OFFSET 30
     194#define FP31_OFFSET 31
    195195#define FPCS_OFFSET 32
    196196
     
    223223        .set noat
    224224
    225         /* 
    226         ** Make sure the FPU is on before we save state.  This code 
    227         ** is here because the FPU context switch might occur when an 
     225        /*
     226        ** Make sure the FPU is on before we save state.  This code
     227        ** is here because the FPU context switch might occur when an
    228228        ** integer task is switching out with a FP task switching in.
    229229        */
     
    246246        NOP
    247247       
    248         /* 
     248        /*
    249249        ** Reassert the task's state because we've not saved it yet.
    250250        */
     
    322322        .set noreorder
    323323       
    324         /* 
    325         ** Make sure the FPU is on before we retrieve state.  This code 
    326         ** is here because the FPU context switch might occur when an 
     324        /*
     325        ** Make sure the FPU is on before we retrieve state.  This code
     326        ** is here because the FPU context switch might occur when an
    327327        ** integer task is switching out with a FP task switching in.
    328328        */
     
    345345        NOP
    346346
    347         /* 
     347        /*
    348348        ** Reassert the old task's state because we've not restored the
    349349        ** new one yet.
     
    440440
    441441       
    442         /* 
     442        /*
    443443        ** this code grabs the userspace EPC if we're dispatching from
    444444        ** an interrupt frame or supplies the address of the dispatch
    445         ** routines if not.  This is entirely for the gdbstub's benefit so 
     445        ** routines if not.  This is entirely for the gdbstub's benefit so
    446446        ** it can know where each task is running.
    447447        **
    448448        ** Its value is only set when calling threadDispatch from
    449         ** the interrupt handler and is cleared immediately when this 
     449        ** the interrupt handler and is cleared immediately when this
    450450        ** routine gets it.
    451451        */
     
    505505/*
    506506** Incorporate the incoming task's FP coprocessor state and interrupt mask/enable
    507 ** into the status register.  We jump thru the requisite hoops to ensure we 
     507** into the status register.  We jump thru the requisite hoops to ensure we
    508508** maintain all other SR bits as global values.
    509509**
    510 ** Get the task's FPU enable, int mask & int enable bits.  Although we keep the 
     510** Get the task's FPU enable, int mask & int enable bits.  Although we keep the
    511511** software int enables on a per-task basis, the rtems_task_create
    512 ** Interrupt Level & int level manipulation functions cannot enable/disable them, 
    513 ** so they are automatically enabled for all tasks.  To turn them off, a task 
    514 ** must itself manipulate the SR register. 
     512** Interrupt Level & int level manipulation functions cannot enable/disable them,
     513** so they are automatically enabled for all tasks.  To turn them off, a task
     514** must itself manipulate the SR register.
    515515**
    516516** Although something of a hack on this processor, we treat the SR register
     
    524524** specific SR bits, including interrupt enable.  If further task-specific
    525525** SR bits are arranged, it is this code, the cpu.c interrupt level stuff and
    526 ** cpu.h task initialization code that will be affected. 
     526** cpu.h task initialization code that will be affected.
    527527*/
    528528
     
    532532        /* int enable bits */
    533533#if (__mips == 3) || (__mips == 32)
    534         /* 
     534        /*
    535535        ** Save IE
    536536        */
    537537        or      t2,SR_IE
    538538#elif __mips == 1
    539         /* 
     539        /*
    540540        ** Save current, previous & old int enables.  This is key because
    541541        ** we can dispatch from within the stack frame used by an
     
    624624 *
    625625 *  void _ISR_Handler()
    626  * 
     626 *
    627627 *
    628628 *  This discussion ignores a lot of the ugly details in a real
     
    655655        ADDIU    sp,sp,-EXCP_STACK_SIZE
    656656
    657         STREG ra, R_RA*R_SZ(sp)  /* store ra on the stack */ 
     657        STREG ra, R_RA*R_SZ(sp)  /* store ra on the stack */
    658658        STREG v0, R_V0*R_SZ(sp)
    659659        STREG v1, R_V1*R_SZ(sp)
     
    672672        mflo  t0
    673673        STREG t8, R_T8*R_SZ(sp)
    674         STREG t0, R_MDLO*R_SZ(sp) 
     674        STREG t0, R_MDLO*R_SZ(sp)
    675675        STREG t9, R_T9*R_SZ(sp)
    676676        mfhi  t0
    677677        STREG gp, R_GP*R_SZ(sp)
    678         STREG t0, R_MDHI*R_SZ(sp) 
     678        STREG t0, R_MDHI*R_SZ(sp)
    679679        STREG fp, R_FP*R_SZ(sp)
    680680       
     
    748748        beqz     t0, 1f
    749749        NOP
    750        
     750
    751751        la       a1,R_F0*R_SZ(sp)
    752         jal      _CPU_Context_save_fp_from_exception 
     752        jal      _CPU_Context_save_fp_from_exception
    753753        NOP
    754754        mfc1     t0,C1_REVISION
     
    756756        STREG    t0,R_FEIR*R_SZ(sp)
    757757        STREG    t1,R_FCSR*R_SZ(sp)
    758        
    759 1:     
     758
     7591:
    760760#endif
    761761       
     
    765765
    766766       
    767         /* 
     767        /*
    768768        ** Note, if the exception vector returns, rely on it to have
    769769        ** adjusted EPC so we will return to some correct address.  If
    770         ** this is not done, we might get stuck in an infinite loop because 
     770        ** this is not done, we might get stuck in an infinite loop because
    771771        ** we'll return to the instruction where the exception occured and
    772772        ** it could throw again.
     
    840840        beqz     t0, 2f
    841841        NOP
    842        
     842
    843843        la       a1,R_F0*R_SZ(sp)
    844844        jal      _CPU_Context_restore_fp_from_exception
     
    862862        /* do NOT restore the cause as this could mess up the world */
    863863
    864         /* 
     864        /*
    865865        ** Jump all the way out.  If theres a pending interrupt, just
    866         ** let it be serviced later.  Since we're probably using the 
     866        ** let it be serviced later.  Since we're probably using the
    867867        ** gdb stub, we've already disrupted the ISR service timing
    868868        ** anyhow.  We oughtn't mix exception and interrupt processing
     
    961961   *    restore stack
    962962   *  #endif
    963    * 
     963   *
    964964   *  if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing )
    965965   *    goto the label "exit interrupt (simple case)"
     
    995995#elif (__mips == 3) || (__mips == 32)
    996996       
    997         /* 
     997        /*
    998998        ** clear XL and set IE so we can get interrupts.
    999999        */
     
    10141014        NOP
    10151015
    1016         /* 
     1016        /*
    10171017        ** And make sure its clear in case we didn't dispatch.  if we did, its
    1018         ** already cleared 
     1018        ** already cleared
    10191019        */
    10201020        la      t0,__exceptionStackFrame
     
    10221022        NOP
    10231023
    1024 /* 
     1024/*
    10251025** turn interrupts back off while we restore context so
    10261026** a badly timed interrupt won't mess things up
     
    10291029
    10301030#if __mips == 1
    1031  
     1031
    10321032        /* ints off, current & prev kernel mode on (kernel mode enabled is bit clear..argh!) */
    10331033        li      t1,SR_IEC | SR_KUP | SR_KUC     
     
    10391039#elif (__mips == 3) || (__mips == 32)
    10401040
    1041         /* make sure EXL and IE are set so ints are disabled & we can update EPC for the return */ 
     1041        /* make sure EXL and IE are set so ints are disabled & we can update EPC for the return */
    10421042        li   t1,SR_IE           /* Clear IE first (recommended) */
    1043         not  t1 
    1044         and  t0,t1 
     1043        not  t1
     1044        and  t0,t1
    10451045        mtc0 t0,C0_SR
    10461046        NOP
     
    10981098        LDREG t0, R_T0*R_SZ(sp)
    10991099        mtlo  t8
    1100         LDREG t8, R_MDHI*R_SZ(sp)           
     1100        LDREG t8, R_MDHI*R_SZ(sp)
    11011101        LDREG t1, R_T1*R_SZ(sp)
    11021102        mthi  t8
  • cpukit/score/cpu/mips/rtems/mips/idtcpu.h

    r42e243e r5bb38e15  
    2222
    2323  $Id$
    24 */ 
     24*/
    2525
    2626/*
     
    7171#define C_VEC   (K0BASE+0x100)          /* cache error vector */
    7272#define E_VEC   (K0BASE+0x180)          /* exception vector */
    73 #else 
     73#else
    7474#error "EXCEPTION VECTORS: unknown ISA level"
    7575#endif
     
    185185*/
    186186/* Disabled by joel -- horrible overload of common word.
    187 #ifndef wait 
     187#ifndef wait
    188188#define wait .word 0x42000020
    189189#endif wait
     
    280280*/
    281281/* Disabled by joel -- horrible overload of common word.
    282 #ifndef wait 
     282#ifndef wait
    283283#define wait .word 0x42000020
    284284#endif wait
  • cpukit/score/cpu/mips/rtems/mips/iregdef.h

    r42e243e r5bb38e15  
    2222
    2323  $Id$
    24 */ 
     24*/
    2525
    2626/*
     
    4040 */
    4141/*
    42 ** register names 
     42** register names
    4343*/
    4444#define r0      $0
  • cpukit/score/cpu/mips/rtems/score/cpu.h

    r42e243e r5bb38e15  
    392392/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
    393393#if (__mips == 1) || (__mips == 32)
    394 #define __MIPS_REGISTER_TYPE     uint32_t 
    395 #define __MIPS_FPU_REGISTER_TYPE uint32_t 
     394#define __MIPS_REGISTER_TYPE     uint32_t
     395#define __MIPS_FPU_REGISTER_TYPE uint32_t
    396396#elif __mips == 3
    397 #define __MIPS_REGISTER_TYPE     uint64_t 
    398 #define __MIPS_FPU_REGISTER_TYPE uint64_t 
     397#define __MIPS_REGISTER_TYPE     uint64_t
     398#define __MIPS_FPU_REGISTER_TYPE uint64_t
    399399#else
    400400#error "mips register size: unknown architecture level!!"
     
    465465 *  that the ISR routine save some of the registers to this frame for
    466466 *  all interrupts and exceptions.  Other registers are saved only on
    467  *  exceptions, while others are not touched at all.  The untouched 
    468  *  registers are not normally disturbed by high-level language 
     467 *  exceptions, while others are not touched at all.  The untouched
     468 *  registers are not normally disturbed by high-level language
    469469 *  programs so they can be accessed when required.
    470470 *
    471471 *  The registers and their ordering in this struct must directly
    472472 *  correspond to the layout and ordering of * shown in iregdef.h,
    473  *  as cpu_asm.S uses those definitions to fill the stack frame. 
     473 *  as cpu_asm.S uses those definitions to fill the stack frame.
    474474 *  This struct provides access to the stack frame for C code.
    475475 *
     
    821821 *  and global interrupt enable for that thread.  It means each thread can
    822822 *  enable its own set of interrupts.  If interrupts are disabled, RTEMS
    823  *  can still dispatch via blocking calls.  This is the function of the 
    824  *  "Interrupt Level", and on the MIPS, it controls the IEC bit and all 
     823 *  can still dispatch via blocking calls.  This is the function of the
     824 *  "Interrupt Level", and on the MIPS, it controls the IEC bit and all
    825825 *  the hardware interrupts as defined in the SR.  Software ints
    826  *  are automatically enabled for all threads, as they will only occur under 
    827  *  program control anyhow.  Besides, the interrupt level parm is only 8 bits, 
     826 *  are automatically enabled for all threads, as they will only occur under
     827 *  program control anyhow.  Besides, the interrupt level parm is only 8 bits,
    828828 *  and controlling the software ints plus the others would require 9.
    829829 *
    830  *  If the Interrupt Level is 0, all ints are on.  Otherwise, the 
    831  *  Interrupt Level should supply a bit pattern to impose on the SR 
     830 *  If the Interrupt Level is 0, all ints are on.  Otherwise, the
     831 *  Interrupt Level should supply a bit pattern to impose on the SR
    832832 *  interrupt bits; bit 0 applies to the mips1 IEC bit/mips3 EXL&IE, bits 1 thru 6
    833  *  apply to the SR register Intr bits from bit 10 thru bit 15.  Bit 7 of 
     833 *  apply to the SR register Intr bits from bit 10 thru bit 15.  Bit 7 of
    834834 *  the Interrupt Level parameter is unused at this time.
    835835 *
  • cpukit/score/cpu/mips/rtems/score/mips.h

    r42e243e r5bb38e15  
    5353 *  of the family.
    5454 */
    55  
     55
    5656#if defined(__mips_soft_float)
    5757#define MIPS_HAS_FPU 0
    5858#else
    5959#define MIPS_HAS_FPU 1
    60 #endif 
     60#endif
    6161
    6262
     
    166166
    167167/*
    168  *  Access the Breakpoint Program Counter & Mask registers 
     168 *  Access the Breakpoint Program Counter & Mask registers
    169169 *  (_x for BPC, _y for mask)
    170170 */
     
    191191
    192192/*
    193  *  Access the Breakpoint Data Address & Mask registers 
     193 *  Access the Breakpoint Data Address & Mask registers
    194194 *  (_x for BDA, _y for mask)
    195195 */
     
    242242
    243243/*
    244  *  Manipulate interrupt mask 
    245  *
    246  *  mips_unmask_interrupt( _mask) 
     244 *  Manipulate interrupt mask
     245 *
     246 *  mips_unmask_interrupt( _mask)
    247247 *    enables interrupts - mask is positioned so it only needs to be or'ed
    248248 *    into the status reg. This also does some other things !!!! Caution
  • cpukit/score/cpu/powerpc/rtems/asm.h

    r42e243e r5bb38e15  
    5050
    5151#ifndef __USER_LABEL_PREFIX__
    52 #define __USER_LABEL_PREFIX__ 
     52#define __USER_LABEL_PREFIX__
    5353#endif
    5454
     
    211211#define eie     0x050   /* External Interrupt Enable Register */
    212212#define eid     0x051   /* External Interrupt Disable Register */
    213 #define nri     0x052   /* Non-Recoverable Interrupt Register */ 
    214  
     213#define nri     0x052   /* Non-Recoverable Interrupt Register */
     214
    215215#elif defined(mpc860) || defined(mpc821)
    216216/* The following registers are for the MPC8x0 */
  • cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h

    r42e243e r5bb38e15  
    105105/*
    106106 *  Does the RTEMS invoke the user's ISR with the vector number and
    107  *  a pointer to the saved interrupt frame (1) or just the vector 
     107 *  a pointer to the saved interrupt frame (1) or just the vector
    108108 *  number (0)?
    109109 */
     
    154154
    155155#ifndef ASM
    156  
     156
    157157/*
    158158 *  This variable is optional.  It is used on CPUs on which it is difficult
     
    195195
    196196#ifndef ASM
    197  
     197
    198198SCORE_EXTERN struct {
    199199  uint32_t      *Disable_level;
     
    260260
    261261#ifndef ASM
    262  
     262
    263263static inline uint32_t   _CPU_ISR_Get_level( void )
    264264{
     
    281281  _CPU_MSR_SET(msr);
    282282}
    283  
     283
    284284void BSP_panic(char *);
    285285
  • cpukit/score/cpu/powerpc/rtems/powerpc/registers.h

    r42e243e r5bb38e15  
    4444   on PowerPC 603, 604, etc. processors (not 601). */
    4545
    46 /* WARNING: HID0/HID1 are *truely* implementation dependent! 
     46/* WARNING: HID0/HID1 are *truely* implementation dependent!
    4747 *          you *cannot* rely on the same bits to be present,
    4848 *          at the same place or even in the same register
  • cpukit/score/cpu/powerpc/rtems/score/cpu.h

    r42e243e r5bb38e15  
    1313 * $Id$
    1414 */
    15  
     15
    1616#ifndef _RTEMS_SCORE_CPU_H
    1717#define _RTEMS_SCORE_CPU_H
     
    395395 *  will be fetched incorrectly.
    396396 */
    397  
     397
    398398static inline uint32_t CPU_swap_u32(
    399399  uint32_t value
     
    401401{
    402402  uint32_t   swapped;
    403  
     403
    404404  asm volatile("rlwimi %0,%1,8,24,31;"
    405405               "rlwimi %0,%1,24,16,23;"
  • cpukit/score/cpu/powerpc/rtems/score/powerpc.h

    r42e243e r5bb38e15  
    6262 *  RTEMS for the PowerPC family.
    6363 */
    64  
     64
    6565/* Generic ppc */
    6666
     
    7373#endif
    7474
    75 #define PPC_ALIGNMENT                   8 
     75#define PPC_ALIGNMENT                   8
    7676#define PPC_STRUCTURE_ALIGNMENT 32
    7777
     
    133133 *
    134134 *  If the model does NOT have FP support, then the model does
    135  *  NOT have double length FP registers. 
     135 *  NOT have double length FP registers.
    136136 */
    137137
  • cpukit/score/cpu/sh/cpu.c

    r42e243e r5bb38e15  
    1111 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1212 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    13  * 
     13 *
    1414 *
    1515 *  COPYRIGHT (c) 1998-2001.
     
    2222 *  $Id$
    2323 */
    24  
     24
    2525#include <rtems/system.h>
    2626#include <rtems/score/isr.h>
     
    7272 *  _CPU_ISR_Get_level
    7373 */
    74  
     74
    7575uint32_t   _CPU_ISR_Get_level( void )
    7676{
     
    8080
    8181  register uint32_t   _mask ;
    82  
     82
    8383  sh_get_interrupt_level( _mask );
    84  
     84
    8585  return ( _mask);
    8686}
     
    9090 *  _CPU_ISR_install_raw_handler
    9191 */
    92  
     92
    9393void _CPU_ISR_install_raw_handler(
    9494  uint32_t    vector,
     
    103103  volatile proc_ptr     *vbr ;
    104104
    105 #if SH_PARANOID_ISR 
     105#if SH_PARANOID_ISR
    106106  uint32_t              level ;
    107107
    108108  sh_disable_interrupts( level );
    109 #endif   
     109#endif
    110110
    111111  /* get vbr */
     
    156156
    157157 /*
    158   *  We put the actual user ISR address in '_ISR_Vector_table'. 
     158  *  We put the actual user ISR address in '_ISR_Vector_table'.
    159159  *  This will be used by __ISR_Handler so the user gets control.
    160160  */
     
    194194#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
    195195
    196 uint8_t   _bit_set_table[16] = 
     196uint8_t   _bit_set_table[16] =
    197197  { 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 1,0};
    198198
  • cpukit/score/cpu/sh/rtems/score/cpu.h

    r42e243e r5bb38e15  
    1515 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1616 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    17  * 
     17 *
    1818 *
    1919 *  COPYRIGHT (c) 1998-2006.
     
    126126 * We define the interrupt stack in the linker script
    127127 */
    128 #define CPU_ALLOCATE_INTERRUPT_STACK FALSE 
     128#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
    129129
    130130/*
    131131 *  Does the RTEMS invoke the user's ISR with the vector number and
    132  *  a pointer to the saved interrupt frame (1) or just the vector 
     132 *  a pointer to the saved interrupt frame (1) or just the vector
    133133 *  number (0)?
    134134 */
     
    294294#define CPU_LITTLE_ENDIAN                        FALSE
    295295#endif
    296  
     296
    297297/*
    298298 *  The following defines the number of bits actually used in the
     
    375375
    376376  uint32_t   gbr;
    377   uint32_t   sr; 
     377  uint32_t   sr;
    378378
    379379} Context_Control;
     
    537537 *  SH Specific Information: NONE
    538538 */
    539  
     539
    540540#define _CPU_Initialize_vectors()
    541  
     541
    542542/*
    543543 *  Disable all interrupts for an RTEMS critical section.  The previous
     
    608608 */
    609609
    610 /* 
     610/*
    611611 * FIXME: defined as a function for debugging - should be a macro
    612612 */
     
    819819 *  _CPU_ISR_install_raw_handler
    820820 *
    821  *  This routine installs a "raw" interrupt handler directly into the 
     821 *  This routine installs a "raw" interrupt handler directly into the
    822822 *  processor's vector table.
    823823 */
    824  
     824
    825825void _CPU_ISR_install_raw_handler(
    826826  uint32_t    vector,
  • cpukit/score/cpu/sh/rtems/score/sh.h

    r42e243e r5bb38e15  
    1515 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1616 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
    17  * 
     17 *
    1818 *
    1919 *  COPYRIGHT (c) 1998-2001.
     
    3737 *  This file contains the information required to build
    3838 *  RTEMS for a particular member of the "SH" family.
    39  * 
     39 *
    4040 *  It does  this by setting variables to indicate which implementation
    4141 *  dependent features are present in a particular member of the family.
     
    4343
    4444/*
    45  *  Figure out all CPU Model Feature Flags based upon compiler 
    46  *  predefines. 
     45 *  Figure out all CPU Model Feature Flags based upon compiler
     46 *  predefines.
    4747 */
    4848
     
    5454#elif defined(__SH4__) || defined(__SH4_SINGLE_ONLY__)
    5555
    56 /* 
     56/*
    5757 * Define this if you want to use XD-registers.
    5858 * Then this registers will be saved/restored on context switch.
     
    6969#endif
    7070
    71 #elif defined(__sh1__) || defined(__sh2__) || defined(__sh3__) 
     71#elif defined(__sh1__) || defined(__sh2__) || defined(__sh3__)
    7272#define SH_HAS_FPU 0
    7373#else
     
    109109    "ldc %1,sr\n\t"\
    110110  : "=&r" (_level ) \
    111   : "r" (SH_IRQDIS_VALUE) ); 
     111  : "r" (SH_IRQDIS_VALUE) );
    112112
    113113#define sh_enable_interrupts( _level ) \
     
    122122 *  modified.
    123123 */
    124      
     124
    125125#define sh_flash_interrupts( _level ) \
    126126  asm volatile( \
     
    143143  : "=&r" (_level ) \
    144144  : "r" (SH_IRQDIS_MASK) \
    145   : "r5" ); 
     145  : "r5" );
    146146
    147147#define sh_enable_interrupts( _level ) \
     
    156156 *  modified.
    157157 */
    158      
     158
    159159#define sh_flash_interrupts( _level ) \
    160160  asm volatile( \
     
    190190 *  It must be static because it is referenced indirectly.
    191191 */
    192  
     192
    193193static inline uint32_t sh_swap_u32(
    194194  uint32_t value
     
    196196{
    197197  register uint32_t swapped;
    198  
    199   asm volatile ( 
     198
     199  asm volatile (
    200200    "swap.b %1,%0; "
    201201    "swap.w %0,%0; "
    202     "swap.b %0,%0" 
    203     : "=r" (swapped) 
     202    "swap.b %0,%0"
     203    : "=r" (swapped)
    204204    : "r"  (value) );
    205205
     
    221221#define CPU_swap_u16( value ) sh_swap_u16( value )
    222222
    223 extern unsigned int sh_set_irq_priority( 
    224   unsigned int irq, 
     223extern unsigned int sh_set_irq_priority(
     224  unsigned int irq,
    225225  unsigned int prio );
    226226
  • cpukit/score/cpu/sh/rtems/score/sh_io.h

    r42e243e r5bb38e15  
    1717 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1818 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    19  * 
     19 *
    2020 *
    2121 *  COPYRIGHT (c) 1998-2001.
     
    3131#ifndef _RTEMS_SCORE_SH_IO_H
    3232#define _RTEMS_SCORE_SH_IO_H
    33  
     33
    3434#define readb(addr)     (*(volatile unsigned char *) (addr))
    3535#define readw(addr)     (*(volatile unsigned short *) (addr))
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