Changeset 5b6111b in rtems
- Timestamp:
- Feb 3, 2005, 4:01:04 PM (16 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 2538e7ae
- Parents:
- 0c20a46
- Location:
- c/src/lib/libbsp/m68k/uC5282
- Files:
-
- 6 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/m68k/uC5282/clock/clock.c
r0c20a46 r5b6111b 48 48 int level; \ 49 49 int preScaleCode = -2; \ 50 int preScaleDivisor = get_CPU_clock_speed() / 1000000;\50 int preScaleDivisor = bsp_get_CPU_clock_speed() / 1000000; \ 51 51 while (preScaleDivisor) { \ 52 52 preScaleDivisor >>= 1; \ 53 53 preScaleCode++; \ 54 54 } \ 55 bsp_allocate_interrupt(PIT3_IRQ_LEVEL, PIT3_IRQ_PRIORITY); \ 55 56 MCF5282_INTC0_ICR58 = MCF5282_INTC_ICR_IL(PIT3_IRQ_LEVEL) | \ 56 57 MCF5282_INTC_ICR_IP(PIT3_IRQ_PRIORITY); \ -
c/src/lib/libbsp/m68k/uC5282/console/console.c
r0c20a46 r5b6111b 137 137 info->hwflow = hwflow; 138 138 139 clock_speed = get_CPU_clock_speed();139 clock_speed = bsp_get_CPU_clock_speed(); 140 140 /* determine the baud divisor value */ 141 141 divisor = (clock_speed / ( 32 * baud )); … … 397 397 switch(chan) { 398 398 case 0: 399 bsp_allocate_interrupt(UART0_IRQ_LEVEL, UART0_IRQ_PRIORITY); 399 400 MCF5282_INTC0_ICR13 = MCF5282_INTC_ICR_IL(UART0_IRQ_LEVEL) | 400 401 MCF5282_INTC_ICR_IP(UART0_IRQ_PRIORITY); … … 404 405 405 406 case 1: 407 bsp_allocate_interrupt(UART1_IRQ_LEVEL, UART1_IRQ_PRIORITY); 406 408 MCF5282_INTC0_ICR14 = MCF5282_INTC_ICR_IL(UART1_IRQ_LEVEL) | 407 409 MCF5282_INTC_ICR_IP(UART1_IRQ_PRIORITY); … … 411 413 412 414 case 2: 415 bsp_allocate_interrupt(UART2_IRQ_LEVEL, UART2_IRQ_PRIORITY); 413 416 MCF5282_INTC0_ICR15 = MCF5282_INTC_ICR_IL(UART2_IRQ_LEVEL) | 414 417 MCF5282_INTC_ICR_IP(UART2_IRQ_PRIORITY); -
c/src/lib/libbsp/m68k/uC5282/include/bsp.h
r0c20a46 r5b6111b 68 68 /* functions */ 69 69 70 unsigned32 get_CPU_clock_speed(void); 70 unsigned32 bsp_get_CPU_clock_speed(void); 71 int bsp_allocate_interrupt(int level, int priority); 71 72 unsigned const char *uC5282_gethwaddr(int a); 72 73 const char *uC5282_getbenv(const char *a); -
c/src/lib/libbsp/m68k/uC5282/network/network.c
r0c20a46 r5b6111b 180 180 rtems_status_code status; 181 181 rtems_isr_entry old_handler; 182 unsigned32 clock_speed = get_CPU_clock_speed();182 unsigned32 clock_speed = bsp_get_CPU_clock_speed(); 183 183 184 184 /* … … 298 298 rtems_panic ("Can't attach MCF5282 FEC RX interrupt handler: %s\n", 299 299 rtems_status_text(status)); 300 bsp_allocate_interrupt(FEC_IRQ_LEVEL, FEC_IRQ_TX_PRIORITY); 300 301 MCF5282_INTC0_ICR23 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) | 301 302 MCF5282_INTC_ICR_IP(FEC_IRQ_TX_PRIORITY); 302 303 MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT23 | MCF5282_INTC_IMRL_MASKALL); 304 bsp_allocate_interrupt(FEC_IRQ_LEVEL, FEC_IRQ_RX_PRIORITY); 303 305 MCF5282_INTC0_ICR27 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) | 304 306 MCF5282_INTC_ICR_IP(FEC_IRQ_RX_PRIORITY); -
c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c
r0c20a46 r5b6111b 247 247 } 248 248 249 unsigned32 get_CPU_clock_speed(void)249 unsigned32 bsp_get_CPU_clock_speed(void) 250 250 { 251 251 extern char _CPUClockSpeed[]; 252 252 return( (unsigned32)_CPUClockSpeed); 253 } 254 255 /* 256 * Interrupt controller allocation 257 */ 258 int bsp_allocate_interrupt(int level, int priority) 259 { 260 static char used[7]; 261 rtems_interrupt_level l; 262 int ret = -1; 263 264 if ((level < 1) || (level > 7) || (priority < 0) || (priority > 7)) 265 return ret; 266 rtems_interrupt_disable(l); 267 if ((used[level-1] & (1 << priority)) == 0) { 268 used[level-1] |= (1 << priority); 269 ret = 0; 270 } 271 rtems_interrupt_enable(l); 272 return ret; 253 273 } 254 274 -
c/src/lib/libbsp/m68k/uC5282/timer/timer.c
r0c20a46 r5b6111b 11 11 Timer_initialize(void) 12 12 { 13 int preScaleDivisor = get_CPU_clock_speed() / 1000000;13 int preScaleDivisor = bsp_get_CPU_clock_speed() / 1000000; 14 14 int div = MCF5282_TIMER_DTMR_CLK_DIV1; 15 15
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