Changeset 5a820308 in rtems


Ignore:
Timestamp:
Dec 3, 1999, 1:42:34 PM (20 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
5707fe9
Parents:
fc81cc9
Message:

Modification from Emmanuel Raguet <raguet@…> to merge the
dec21140 drivers from the i386/pc386 and powerpc/mcp750 (all Motorola
PowerPC boards) and move the network driver to libchip. This driver
should work on all PCI based uses of this chip.

Location:
c/src
Files:
4 added
1 deleted
6 edited
1 moved

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/i386/pc386/Makefile.in

    rfc81cc9 r5a820308  
    2020
    2121# We only build the Network library if HAS_NETWORKING was defined
    22 NETWORK_yes_V = dec21140 ne2000 wd8003 3c509
     22# dec21140 is supported via libchip
     23NETWORK_yes_V = ne2000 wd8003 3c509
    2324NETWORK = $(NETWORK_$(HAS_NETWORKING)_V)
    2425
  • c/src/lib/libbsp/i386/pc386/wrapup/Makefile.in

    rfc81cc9 r5a820308  
    1515
    1616# We only build the Network library if HAS_NETWORKING was defined
    17 NETWORK_yes_V = dec21140 ne2000 wd8003 3c509
     17# dec21140 is supported via libchip
     18NETWORK_yes_V = ne2000 wd8003 3c509
    1819NETWORK = $(NETWORK_$(HAS_NETWORKING)_V)
    1920
  • c/src/lib/libbsp/powerpc/mcp750/Makefile.in

    rfc81cc9 r5a820308  
    2323all: $(SRCS)
    2424
    25 # We only build the Network library if HAS_NETWORKING was defined
    26 NETWORK_yes_V = dec21140
    27 NETWORK = $(NETWORK_$(HAS_NETWORKING)_V)
    28 
    2925# wrapup is the one that actually builds and installs the library
    3026#  from the individual .rel files built in other directories
    3127SUBDIRS = clock console include pci residual openpic irq vectors start \
    32     startup bootloader $(NETWORK) motorola wrapup
     28    startup bootloader motorola wrapup
    3329
    3430Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
  • c/src/lib/libbsp/powerpc/mcp750/wrapup/Makefile.in

    rfc81cc9 r5a820308  
    1414VPATH = @srcdir@
    1515
    16 # We only build the Network library if HAS_NETWORKING was defined
    17 NETWORK_yes_V = dec21140
    18 NETWORK = $(NETWORK_$(HAS_NETWORKING)_V)
    19 
    20 BSP_PIECES = clock console irq openpic pci residual startup $(NETWORK) \
    21     vectors motorola
     16BSP_PIECES = clock console irq openpic pci residual startup vectors motorola
    2217GENERIC_PIECES =
    2318
  • c/src/lib/libbsp/powerpc/motorola_powerpc/Makefile.in

    rfc81cc9 r5a820308  
    2323all: $(SRCS)
    2424
    25 # We only build the Network library if HAS_NETWORKING was defined
    26 NETWORK_yes_V = dec21140
    27 NETWORK = $(NETWORK_$(HAS_NETWORKING)_V)
    28 
    2925# wrapup is the one that actually builds and installs the library
    3026#  from the individual .rel files built in other directories
    3127SUBDIRS = clock console include pci residual openpic irq vectors start \
    32     startup bootloader $(NETWORK) motorola wrapup
     28    startup bootloader motorola wrapup
    3329
    3430Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
  • c/src/lib/libbsp/powerpc/motorola_powerpc/wrapup/Makefile.in

    rfc81cc9 r5a820308  
    1414VPATH = @srcdir@
    1515
    16 # We only build the Network library if HAS_NETWORKING was defined
    17 NETWORK_yes_V = dec21140
    18 NETWORK = $(NETWORK_$(HAS_NETWORKING)_V)
    19 
    20 BSP_PIECES = clock console irq openpic pci residual startup $(NETWORK) \
    21     vectors motorola
     16BSP_PIECES = clock console irq openpic pci residual startup vectors motorola
    2217GENERIC_PIECES =
    2318
  • c/src/libchip/network/dec21140.c

    rfc81cc9 r5a820308  
    11/*
    2  * RTEMS driver for TULIP based Ethernet Controller
     2 *  RTEMS driver for TULIP based Ethernet Controller
    33 *
    4  *  $Header$
     4 *  Copyright (C) 1999 Emmanuel Raguet. raguet@crf.canon.fr
     5 *
     6 *  The license and distribution terms for this file may be
     7 *  found in found in the file LICENSE in this distribution or at
     8 *  http://www.OARcorp.com/rtems/license.html.
     9 *
     10 * $Id$
    511 */
    612
    713#include <bsp.h>
     14#if defined(i386)
    815#include <pcibios.h>
     16#endif
     17#if defined(__PPC)
     18#include <bsp/pci.h>
     19#include <libcpu/byteorder.h>
     20#include <libcpu/io.h>
     21#endif
    922
    1023#include <stdlib.h>
     
    2538#include <netinet/if_ether.h>
    2639 
     40#if defined(i386)
    2741#include <irq.h>
     42#endif
     43#if defined(__PPC)
     44#include <bsp/irq.h>
     45#endif
    2846
    2947#ifdef malloc
     
    3452#endif
    3553
     54#define DEC_DEBUG
     55
     56#define PCI_INVALID_VENDORDEVICEID      0xffffffff
    3657#define PCI_VENDOR_ID_DEC 0x1011
    3758#define PCI_DEVICE_ID_DEC_TULIP_FAST 0x0009
     
    3960#define IO_MASK  0x3
    4061#define MEM_MASK  0xF
     62#define MASK_OFFSET 0xF
    4163
    4264/* command and status registers, 32-bit access, only if IO-ACCESS */
     
    79101
    80102#define RESET_CHIP   0x00000001
    81 #define CSR0_MODE    0x01a08000   /* 01a08000 */
     103#if defined(__PPC)
     104#define CSR0_MODE    0x0030e002   /* 01b08000 */
     105#else
     106#define CSR0_MODE    0x0020e002   /* 01b08000 */
     107#endif
    82108#define ROM_ADDRESS  0x00004800
    83 #define CSR6_INIT    0x020c0000   /* 020c0000 */ 
     109#define CSR6_INIT    0x022cc000   /* 022c0000 020c0000 */ 
    84110#define CSR6_TX      0x00002000   
    85111#define CSR6_TXRX    0x00002002   
    86 #define IT_SETUP     0x00010040   /* 0001ebef */
     112#define IT_SETUP     0x000100c0   /* 000100e0 */
    87113#define CLEAR_IT     0xFFFFFFFF   
    88114#define NO_IT        0x00000000   
    89115
    90 #define NRXBUFS 7       /* number of receive buffers */
    91 #define NTXBUFS 1       /* number of transmit buffers */
     116#define NRXBUFS 32      /* number of receive buffers */
     117#define NTXBUFS 16      /* number of transmit buffers */
    92118
    93119/* message descriptor entry */
    94120struct MD {
    95     volatile unsigned long status;
    96     volatile unsigned long counts;
    97     unsigned long buf1, buf2;   
     121    /* used by hardware */
     122    volatile unsigned32 status;
     123    volatile unsigned32 counts;
     124    unsigned32 buf1, buf2; 
     125    /* used by software */
     126    volatile struct mbuf *m;
     127    volatile struct MD *next;
    98128};
    99129
    100130/*
    101  * Number of WDs supported by this driver
     131 * Number of DECs supported by this driver
    102132 */
    103133#define NDECDRIVER      1
     
    122152#define START_TRANSMIT_EVENT    RTEMS_EVENT_2
    123153
     154#if defined(__PPC)
     155#define phys_to_bus(address) ((unsigned int)(address) + PREP_PCI_DRAM_OFFSET)
     156#define bus_to_phys(address) ((unsigned int)(address) - PREP_PCI_DRAM_OFFSET)
     157#define CPU_CACHE_ALIGNMENT_FOR_BUFFER PPC_CACHE_ALIGNMENT
     158#else
     159#define phys_to_bus(address) address
     160#define bus_to_phys(address) address
     161#define delay_in_bus_cycles(cycle) Wait_X_ms( cycle/100 )
     162#define CPU_CACHE_ALIGNMENT_FOR_BUFFER PG_SIZE
     163
     164inline void st_le32(volatile unsigned32 *addr, unsigned32 value)
     165{
     166  *(addr)=value ;
     167}
     168
     169inline unsigned32 ld_le32(volatile unsigned32 *addr)
     170{
     171  return(*addr);
     172}
     173
     174#endif
     175
    124176#if (MCLBYTES < RBUF_SIZE)
    125177# error "Driver must have MCLBYTES > RBUF_SIZE"
     
    130182 */
    131183 struct dec21140_softc {
    132   struct arpcom                 arpcom;
    133   rtems_irq_connect_data        irqInfo;
    134   struct MD                     *MDbase;
    135   char                          *bufferBase;
    136   int                           acceptBroadcast;
    137   int                           rxBdCount;
    138   int                           txBdCount;
    139   rtems_id                      rxDaemonTid;
    140   rtems_id                      txDaemonTid;
     184
     185   struct arpcom                        arpcom;
     186
     187   rtems_irq_connect_data       irqInfo;
     188
     189   volatile struct MD           *MDbase;
     190   volatile unsigned char       *bufferBase;
     191   int                          acceptBroadcast;
     192   rtems_id                     rxDaemonTid;
     193   rtems_id                     txDaemonTid;
     194   
     195   volatile struct MD   *TxMD;
     196   volatile struct MD   *SentTxMD;
     197   int         PendingTxCount;
     198   int         TxSuspended;
    141199
    142200  unsigned int                  port;
    143   unsigned int                  *base;
    144   unsigned long                 bpar;
     201  volatile unsigned int         *base;
    145202   
    146203  /*
     
    175232dec21140Enet_interrupt_handler (rtems_vector_number v)
    176233{
    177   unsigned int *tbase;
    178   unsigned long status;
    179 
    180   unsigned int sc;
    181  
    182   tbase = dec21140_softc[0].base ;
    183 
    184   /*
    185    * Read status
    186    */
    187   *(tbase+memCSR7) = NO_IT;
    188   status = *(tbase+memCSR5);
    189   *(tbase+memCSR5) = CLEAR_IT;
    190 
    191   /*
    192    * Frame received?
    193    */
    194   if (status & 0x00000040){
    195     dec21140_softc[0].rxInterrupts++;
    196     sc = rtems_event_send (dec21140_softc[0].rxDaemonTid, INTERRUPT_EVENT);
    197   }
     234    volatile unsigned32 *tbase;
     235    unsigned32 status;
     236    struct dec21140_softc *sc;
     237
     238    sc = &dec21140_softc[0];
     239    tbase = (unsigned32 *)(sc->base) ;
     240
     241    /*
     242     * Read status
     243     */
     244    status = ld_le32(tbase+memCSR5);
     245    st_le32((tbase+memCSR5), status); /* clear the bits we've read */
     246
     247    /*
     248     * Frame received?
     249     */
     250    if (status & 0x000000c0){
     251      sc->rxInterrupts++;
     252      rtems_event_send (sc->rxDaemonTid, INTERRUPT_EVENT);
     253    }
    198254}
    199255
     
    211267}
    212268
    213 /*
    214  * Read and write the MII registers using software-generated serial
    215  * MDIO protocol.
    216  */
    217 #define MDIO_SHIFT_CLK          0x10000
    218 #define MDIO_DATA_WRITE0        0x00000
    219 #define MDIO_DATA_WRITE1        0x20000
    220 #define MDIO_ENB                0x00000 
    221 #define MDIO_ENB_IN             0x40000
    222 #define MDIO_DATA_READ          0x80000
    223 
    224 static int mdio_read(unsigned int *ioaddr, int phy_id, int location)
    225 {
    226         int i, i3;
    227         int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
    228         unsigned short retval = 0;
    229 
    230         /* Establish sync by sending at least 32 logic ones. */
    231         for (i = 32; i >= 0; i--) {
    232                 *ioaddr = MDIO_ENB | MDIO_DATA_WRITE1;
    233                 for(i3=0; i3<1000; i3++);
    234                 *ioaddr =  MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK;
    235                 for(i3=0; i3<1000; i3++);
    236         }
    237         /* Shift the read command bits out. */
    238         for (i = 17; i >= 0; i--) {
    239                 int dataval = (read_cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
    240                 *ioaddr =  dataval;
    241                 for(i3=0; i3<1000; i3++);
    242                 *ioaddr =  dataval | MDIO_SHIFT_CLK;
    243                 for(i3=0; i3<1000; i3++);
    244                 *ioaddr =  dataval;
    245                 for(i3=0; i3<1000; i3++);
    246         }
    247         *ioaddr =  MDIO_ENB_IN | MDIO_SHIFT_CLK;
    248         for(i3=0; i3<1000; i3++);
    249         *ioaddr =  MDIO_ENB_IN;
    250 
    251         for (i = 16; i > 0; i--) {
    252                 *ioaddr =  MDIO_ENB_IN | MDIO_SHIFT_CLK;
    253                 for(i3=0; i3<1000; i3++);
    254                 retval = (retval << 1) | ((*ioaddr & MDIO_DATA_READ) ? 1 : 0);
    255                 *ioaddr =  MDIO_ENB_IN;
    256                 for(i3=0; i3<1000; i3++);
    257         }
    258         /* Clear out extra bits. */
    259         for (i = 16; i > 0; i--) {
    260                 *ioaddr =  MDIO_ENB_IN | MDIO_SHIFT_CLK;
    261                 for(i3=0; i3<1000; i3++);
    262                 *ioaddr =  MDIO_ENB_IN;
    263                 for(i3=0; i3<1000; i3++);
    264         }
    265         return retval;
    266 }
    267 
    268 static int mdio_write(unsigned int *ioaddr, int phy_id, int location, int value)
    269 {
    270         int i, i3;
    271         int cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
    272 
    273         /* Establish sync by sending at least 32 logic ones. */
    274         for (i = 32; i >= 0; i--) {
    275                 *ioaddr =  MDIO_ENB | MDIO_DATA_WRITE1;
    276                 for(i3=0; i3<1000; i3++);
    277                 *ioaddr = MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK;
    278                 for(i3=0; i3<1000; i3++);
    279         }
    280         /* Shift the read command bits out. */
    281         for (i = 31; i >= 0; i--) {
    282                 int dataval = (cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
    283                 *ioaddr =  dataval;
    284                 for(i3=0; i3<1000; i3++);
    285                 *ioaddr =  dataval | MDIO_SHIFT_CLK;
    286                 for(i3=0; i3<1000; i3++);
    287         }
    288 
    289         /* Clear out extra bits. */
    290         for (i = 2; i > 0; i--) {
    291                 *ioaddr =  MDIO_ENB_IN;
    292                 for(i3=0; i3<1000; i3++);
    293                 *ioaddr = MDIO_ENB_IN | MDIO_SHIFT_CLK;
    294                 for(i3=0; i3<1000; i3++);
    295         }
    296         return 0;
    297 
    298 
    299 }
    300269
    301270/*
     
    316285#define EE_ERASE_CMD    (7 << 6)
    317286
    318 static int eeget16(unsigned int *ioaddr, int location)
    319 {
    320         int i, i3;
     287static int eeget16(volatile unsigned int *ioaddr, int location)
     288{
     289        int i;
    321290        unsigned short retval = 0;
    322291        int read_cmd = location | EE_READ_CMD;
    323292       
    324         *ioaddr = EE_ENB & ~EE_CS;
    325         *ioaddr = EE_ENB;
     293        st_le32(ioaddr, EE_ENB & ~EE_CS);
     294        st_le32(ioaddr, EE_ENB);
    326295       
    327296        /* Shift the read command bits out. */
    328297        for (i = 10; i >= 0; i--) {
    329298                short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
    330                 *ioaddr = EE_ENB | dataval;
    331                 for (i3=0; i3<1000; i3++) ;
    332                 *ioaddr = EE_ENB | dataval | EE_SHIFT_CLK;
    333                 for (i3=0; i3<1000; i3++) ;
    334                 *ioaddr = EE_ENB | dataval; /* Finish EEPROM a clock tick. */
    335                 for (i3=0; i3<1000; i3++) ;
     299                st_le32(ioaddr, EE_ENB | dataval);
     300                delay_in_bus_cycles(200);
     301                st_le32(ioaddr, EE_ENB | dataval | EE_SHIFT_CLK);
     302                delay_in_bus_cycles(200);
     303                st_le32(ioaddr, EE_ENB | dataval); /* Finish EEPROM a clock tick. */
     304                delay_in_bus_cycles(200);
    336305        }
    337         *ioaddr = EE_ENB;
     306        st_le32(ioaddr, EE_ENB);
    338307       
    339308        for (i = 16; i > 0; i--) {
    340                 *ioaddr = EE_ENB | EE_SHIFT_CLK;
    341                 for (i3=0; i3<1000; i3++) ;
    342                 retval = (retval << 1) | ((*ioaddr & EE_DATA_READ) ? 1 : 0);
    343                 *ioaddr = EE_ENB;
    344                 for (i3=0; i3<1000; i3++) ;
     309                st_le32(ioaddr, EE_ENB | EE_SHIFT_CLK);
     310                delay_in_bus_cycles(200);
     311                retval = (retval << 1) | ((ld_le32(ioaddr) & EE_DATA_READ) ? 1 : 0);
     312                st_le32(ioaddr, EE_ENB);
     313                delay_in_bus_cycles(200);
    345314        }
    346315
    347316        /* Terminate the EEPROM access. */
    348         *ioaddr = EE_ENB & ~EE_CS;
    349         return retval;
     317        st_le32(ioaddr, EE_ENB & ~EE_CS);
     318        return ( ((retval<<8)&0xff00) | ((retval>>8)&0xff) );
    350319}
    351320
     
    357326{
    358327  rtems_status_code st;
    359   unsigned int *tbase;
     328  volatile unsigned int *tbase;
    360329  union {char c[64]; unsigned short s[32];} rombuf;
    361   int i, i2, i3;
    362   char *cp, direction, *setup_frm, *eaddrs;
    363   unsigned long csr12_val, mii_reg0;
    364   unsigned char *buffer;
    365   struct MD *rmd;
    366 
    367  
     330  int i;
     331  volatile unsigned char *cp, *setup_frm, *eaddrs;
     332  volatile unsigned char *buffer;
     333  volatile struct MD *rmd;
     334
    368335  tbase = sc->base;
    369336
     
    372339   *           Then Reset the chip ( 1 in CSR0)
    373340   */
    374 
    375   *(tbase+memCSR6) = CSR6_INIT; 
    376   *(tbase+memCSR0) = RESET_CHIP; 
    377   for(i3=0; i3<1000; i3++);
     341  st_le32( (tbase+memCSR6), CSR6_INIT); 
     342  st_le32( (tbase+memCSR0), RESET_CHIP); 
     343  delay_in_bus_cycles(200);
    378344
    379345  /*
    380346   * Init CSR0
    381347   */
    382   *(tbase+memCSR0) = CSR0_MODE
    383 
    384   csr12_val = *(tbase+memCSR8);
    385  
    386   for (i=0; i<32; i++)
     348  st_le32( (tbase+memCSR0), CSR0_MODE)
     349
     350  /*  csr12_val = ld_le32( (tbase+memCSR8) );*/
     351
     352  for (i=0; i<32; i++){
    387353    rombuf.s[i] = eeget16(tbase+memCSR9, i);
     354  }
    388355  memcpy (sc->arpcom.ac_enaddr, rombuf.c+20, ETHER_ADDR_LEN);
    389356
    390 
    391   mii_reg0 = mdio_read(tbase+memCSR9, 0, 0);
    392   mdio_write(tbase+memCSR9, 0, 0, mii_reg0 | 0x1000);
    393  
    394357#ifdef DEC_DEBUG
    395358  printk("DC21140 %x:%x:%x:%x:%x:%x IRQ %d IO %x M %x .........\n",
     
    397360         sc->arpcom.ac_enaddr[2], sc->arpcom.ac_enaddr[3],
    398361         sc->arpcom.ac_enaddr[4], sc->arpcom.ac_enaddr[5],
    399          sc->irqInfo.name, sc->port, sc->base);
     362         sc->irqInfo.name, sc->port, (unsigned) sc->base);
    400363#endif
    401364 
     
    403366   * Init RX ring
    404367   */
    405   sc->rxBdCount = 0;
    406  
    407   cp = (char *)malloc((NRXBUFS+NTXBUFS)*(sizeof(struct MD)+ RBUF_SIZE) + PG_SIZE);
     368  cp = (volatile unsigned char *)malloc(((NRXBUFS+NTXBUFS)*sizeof(struct MD))
     369                                        + (NTXBUFS*RBUF_SIZE)
     370                                        + CPU_CACHE_ALIGNMENT_FOR_BUFFER);
    408371  sc->bufferBase = cp;
    409   cp += (PG_SIZE - (int)cp) & MASK_OFFSET;
     372  cp += (CPU_CACHE_ALIGNMENT_FOR_BUFFER - (int)cp)
     373         & (CPU_CACHE_ALIGNMENT_FOR_BUFFER - 1);
     374#if defined(__i386)
    410375#ifdef PCI_BRIDGE_DOES_NOT_ENSURE_CACHE_COHERENCY_FOR_DMA
    411376  if (_CPU_is_paging_enabled())
    412377    _CPU_change_memory_mapping_attribute
    413378                   (NULL, cp,
    414                     (NRXBUFS+NTXBUFS)*(sizeof(struct MD)+ RBUF_SIZE),
     379                    ((NRXBUFS+NTXBUFS)*sizeof(struct MD))
     380                    + (NTXBUFS*RBUF_SIZE),
    415381                    PTE_CACHE_DISABLE | PTE_WRITABLE);
    416382#endif
    417   rmd = (struct MD*)cp;
     383#endif
     384  rmd = (volatile struct MD*)cp;
    418385  sc->MDbase = rmd;
    419386  buffer = cp + ((NRXBUFS+NTXBUFS)*sizeof(struct MD));
    420  
    421   *(tbase+memCSR3) = (long)(sc->MDbase);
     387  st_le32( (tbase+memCSR3), (long)(phys_to_bus((long)(sc->MDbase))));
    422388  for (i=0 ; i<NRXBUFS; i++){
    423     rmd->buf2 = 0;
    424     rmd->buf1 = (unsigned long)(buffer + (i*RBUF_SIZE)); 
    425     if (i == NRXBUFS-1)
    426       rmd->counts = 0xfec00000 | (RBUF_SIZE);
    427     else
    428       rmd->counts = 0xfcc00000 | (RBUF_SIZE);
     389    struct mbuf *m;
     390   
     391    /* allocate an mbuf for each receive descriptor */
     392    MGETHDR (m, M_WAIT, MT_DATA);
     393    MCLGET (m, M_WAIT);
     394    m->m_pkthdr.rcvif = &sc->arpcom.ac_if;
     395    rmd->m = m;
     396
     397    rmd->buf2   = phys_to_bus(rmd+1);
     398    rmd->buf1   = phys_to_bus(mtod(m, void *)); 
     399    rmd->counts = 0xfdc00000 | (RBUF_SIZE);
    429400    rmd->status = 0x80000000;
     401    rmd->next   = rmd + 1;
    430402    rmd++;
    431403  }
     404  /*
     405   * mark last RX buffer.
     406   */
     407  sc->MDbase [NRXBUFS-1].counts = 0xfec00000 | (RBUF_SIZE);
     408  sc->MDbase [NRXBUFS-1].next   = sc->MDbase;
    432409
    433410  /*
    434411   * Init TX ring
    435412   */
    436   sc->txBdCount = 0;
    437   *(tbase+memCSR4) = (long)(rmd);
    438   rmd->buf2 = 0;
    439   rmd->buf1 = (unsigned long)(buffer + (NRXBUFS*RBUF_SIZE));
    440   rmd->counts = 0x62000000;
    441   rmd->status = 0x0;
     413  st_le32( (tbase+memCSR4), (long)(phys_to_bus((long)(rmd))) );
     414  for (i=0 ; i<NTXBUFS; i++){
     415    (rmd+i)->buf2   = phys_to_bus(rmd+i+1);
     416    (rmd+i)->buf1   = phys_to_bus(buffer + (i*RBUF_SIZE));
     417    (rmd+i)->counts = 0x01000000;
     418    (rmd+i)->status = 0x0;
     419    (rmd+i)->next   = rmd+i+1;
     420    (rmd+i)->m      = 0;
     421  }
     422
     423  /*
     424   * mark last TX buffer.
     425   */
     426  (rmd+NTXBUFS-1)->buf2   = phys_to_bus(rmd);
     427  (rmd+NTXBUFS-1)->next   = rmd;
    442428 
    443429  /*
    444430   * Set up interrupts
    445431   */
    446   *(tbase+memCSR5) = IT_SETUP;
    447   *(tbase+memCSR7) = IT_SETUP;
    448 
    449432  sc->irqInfo.hdl = (rtems_irq_hdl)dec21140Enet_interrupt_handler;
    450433  sc->irqInfo.on  = nopOn;
     
    456439                  sc->irqInfo.name);
    457440
    458   /*
    459    * Start TX for setup frame
    460    */
    461   *(tbase+memCSR6) = CSR6_INIT | CSR6_TX;
     441  st_le32( (tbase+memCSR7), NO_IT);
    462442
    463443  /*
    464444   * Build setup frame
    465445   */
    466   setup_frm = (char *)(rmd->buf1);
     446  setup_frm = (volatile unsigned char *)(bus_to_phys(rmd->buf1));
    467447  eaddrs = (char *)(sc->arpcom.ac_enaddr);
    468448  /* Fill the buffer with our physical address. */
     
    470450        *setup_frm++ = eaddrs[0];
    471451        *setup_frm++ = eaddrs[1];
    472         setup_frm += 2;
     452        *setup_frm++ = eaddrs[0];
     453        *setup_frm++ = eaddrs[1];
    473454        *setup_frm++ = eaddrs[2];
    474455        *setup_frm++ = eaddrs[3];
    475         setup_frm += 2;
     456        *setup_frm++ = eaddrs[2];
     457        *setup_frm++ = eaddrs[3];
    476458        *setup_frm++ = eaddrs[4];
    477459        *setup_frm++ = eaddrs[5];
    478         setup_frm += 2;
     460        *setup_frm++ = eaddrs[4];
     461        *setup_frm++ = eaddrs[5];
    479462  }
    480463  /* Add the broadcast address when doing perfect filtering */
    481   memset(setup_frm, 0xff, 12);
    482   rmd->counts = 0x0a000000 | 192 ;
     464  memset((void*) setup_frm, 0xff, 12);
     465  rmd->counts = 0x09000000 | 192 ;
    483466  rmd->status = 0x80000000;
    484   *(tbase+memCSR1) = 1;
     467  st_le32( (tbase+memCSR6), CSR6_INIT | CSR6_TX);
     468  st_le32( (tbase+memCSR1), 1);
    485469  while (rmd->status != 0x7fffffff);
    486 
     470  rmd->counts = 0x01000000;   
     471  sc->TxMD = rmd+1;
     472 
    487473  /*
    488474   * Enable RX and TX
    489475   */
    490   *(tbase+memCSR6) = CSR6_INIT | CSR6_TXRX;
     476  st_le32( (tbase+memCSR5), IT_SETUP);
     477  st_le32( (tbase+memCSR7), IT_SETUP);
     478  st_le32( (unsigned int*)(tbase+memCSR6), CSR6_INIT | CSR6_TXRX);
    491479 
    492   /*
    493    * Set up PHY
    494    */
    495  
    496   i = rombuf.c[27];
    497   i+=2;
    498   direction = rombuf.c[i];
    499   i +=4;
    500   *(tbase+memCSR12) = direction | 0x100;
    501   for (i2 = 0; i2 < rombuf.c[(i+2) + rombuf.c[i+1]]; i2++){
    502     *(tbase + memCSR12) = rombuf.c[(i+3) + rombuf.c[i+1] + i2];
    503   }
    504   for (i2 = 0; i2 < rombuf.c[i+1]; i2++){
    505     *(tbase + memCSR12) = rombuf.c[(i+2) + i2];
    506   }
    507480}
    508481
     
    510483dec21140_rxDaemon (void *arg)
    511484{
    512   unsigned int *tbase;
     485  volatile unsigned int *tbase;
    513486  struct ether_header *eh;
    514487  struct dec21140_softc *dp = (struct dec21140_softc *)&dec21140_softc[0];
    515488  struct ifnet *ifp = &dp->arpcom.ac_if;
    516489  struct mbuf *m;
    517   struct MD *rmd;
     490  volatile struct MD *rmd;
    518491  unsigned int len;
    519   char *temp;
    520492  rtems_event_set events;
    521   int nbMD;
    522493 
    523494  tbase = dec21140_softc[0].base ;
     495  rmd = dec21140_softc[0].MDbase;
    524496
    525497  for (;;){
     
    529501                                RTEMS_NO_TIMEOUT,
    530502                                &events);
    531     rmd = dec21140_softc[0].MDbase;
    532     nbMD = 0;
    533503   
    534     while (nbMD < NRXBUFS){
    535       if ( (rmd->status & 0x80000000) == 0){
    536         len = (rmd->status >> 16) & 0x7ff;
    537         MGETHDR (m, M_WAIT, MT_DATA);
    538         MCLGET (m, M_WAIT);
    539         m->m_pkthdr.rcvif = ifp;
    540         temp = m->m_data;
    541         m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header);
    542         memcpy(temp, (char *)rmd->buf1, len);
    543         rmd->status = 0x80000000;
    544         eh = mtod (m, struct ether_header *);
    545         m->m_data += sizeof(struct ether_header);
    546         ether_input (ifp, eh, m);
    547       }
    548       rmd++;
    549       nbMD++;
     504    while((rmd->status & 0x80000000) == 0){
     505      /* pass on the packet in the mbuf */
     506      len = (rmd->status >> 16) & 0x7ff;
     507      m = (struct mbuf *)(rmd->m);
     508      m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header);
     509      eh = mtod (m, struct ether_header *);
     510      m->m_data += sizeof(struct ether_header);
     511      ether_input (ifp, eh, m);
     512       
     513      /* get a new mbuf for the 21140 */
     514      MGETHDR (m, M_WAIT, MT_DATA);
     515      MCLGET (m, M_WAIT);
     516      m->m_pkthdr.rcvif = ifp;
     517      rmd->m = m;
     518      rmd->buf1 = phys_to_bus(mtod(m, void *)); 
     519
     520      rmd->status = 0x80000000;
     521     
     522      rmd=rmd->next;
    550523    }
    551     *(tbase+memCSR7) = IT_SETUP;
    552524  }     
    553525}
     
    558530  struct dec21140_softc *dp = ifp->if_softc;
    559531  volatile struct MD *tmd;
    560   unsigned char *temp;
     532  volatile unsigned char *temp;
    561533  struct mbuf *n;
    562534  unsigned int len;
    563   unsigned int *tbase;
     535  volatile unsigned int *tbase;
    564536
    565537  tbase = dp->base;
    566 
    567538  /*
    568539   * Waiting for Transmitter ready
    569540   */   
    570   tmd = dec21140_softc[0].MDbase + NRXBUFS;
    571   while ( (tmd->status & 0x80000000) != 0 );
     541  tmd = dec21140_softc[0].TxMD;
     542  n = m;
     543
     544  while ((tmd->status & 0x80000000) != 0){
     545    tmd=tmd->next;
     546    }
     547
    572548  len = 0;
    573   n = m;
    574   temp = (char *)(tmd->buf1);
     549  temp = (volatile unsigned char *)(bus_to_phys(tmd->buf1));
    575550 
    576551  for (;;){
    577552    len += m->m_len;
    578     memcpy(temp, (char *)m->m_data, m->m_len);
     553    memcpy((void*) temp, (char *)m->m_data, m->m_len);
    579554    temp += m->m_len ;
    580555    if ((m = m->m_next) == NULL)
     
    583558
    584559  if (len < ET_MINLEN) len = ET_MINLEN;
    585   tmd->counts = 0xe2000000 | len;
     560  tmd->counts =  0xe1000000 | (len & 0x7ff); 
    586561  tmd->status = 0x80000000;
    587562
    588   *(tbase+memCSR1) = 0x1;
     563  st_le32( (tbase+memCSR1), 0x1);
    589564
    590565  m_freem(n);
     566  dec21140_softc[0].TxMD = tmd->next;
    591567}
    592568
     
    673649dec21140_stop (struct dec21140_softc *sc)
    674650{
    675   unsigned int *tbase;
     651  volatile unsigned int *tbase;
    676652  struct ifnet *ifp = &sc->arpcom.ac_if;
    677653
     
    682658   */
    683659  tbase=dec21140_softc[0].base ;
    684   *(tbase+memCSR7) = NO_IT;
    685   *(tbase+memCSR6) = CSR6_INIT;
    686   free(sc->bufferBase);
     660  st_le32( (tbase+memCSR7), NO_IT);
     661  st_le32( (tbase+memCSR6), CSR6_INIT);
     662  free((void*)sc->bufferBase);
    687663}
    688664
     
    760736                break;
    761737        }
     738
    762739        return error;
    763740}
     
    773750        int mtu;
    774751        int i;
     752       
     753        /*
     754         * First, find a DEC board
     755         */
     756#if defined(__i386)
    775757        int signature;
    776758        int value;
    777759        char interrupt;
    778760        int diag;
    779        
    780         /*
    781          * Initialise PCI module
    782          */
     761
    783762        if (pcib_init() == PCIB_ERR_NOTPRESENT)
    784763          rtems_panic("PCI BIOS not found !!");
     
    795774          printk("DEC PCI Device found\n");
    796775        }
     776#endif 
     777#if defined(__PPC)
     778        unsigned char ucSlotNumber, ucFnNumber;
     779        unsigned int  ulDeviceID, lvalue, tmp; 
     780        unsigned char cvalue;
     781
     782        for(ucSlotNumber=0;ucSlotNumber<PCI_MAX_DEVICES;ucSlotNumber++) {
     783          for(ucFnNumber=0;ucFnNumber<PCI_MAX_FUNCTIONS;ucFnNumber++) {
     784            (void)pci_read_config_dword(0,
     785                                        ucSlotNumber,
     786                                        ucFnNumber,
     787                                        PCI_VENDOR_ID,
     788                                        &ulDeviceID);
     789            if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) {
     790              /*
     791               * This slot is empty
     792               */
     793              continue;
     794            }
     795            if (ulDeviceID == ((PCI_DEVICE_ID_DEC_TULIP_FAST<<16) + PCI_VENDOR_ID_DEC))
     796              break;
     797          }
     798          if (ulDeviceID == ((PCI_DEVICE_ID_DEC_TULIP_FAST<<16) + PCI_VENDOR_ID_DEC)){
     799            printk("DEC Adapter found !!\n");
     800            break;
     801          }
     802        }
    797803       
     804        if(ulDeviceID==PCI_INVALID_VENDORDEVICEID)
     805          rtems_panic("DEC PCI board not found !!\n");
     806#endif 
    798807        /*
    799808         * Find a free driver
     
    813822         * Process options
    814823         */
    815 
     824#if defined(__i386)
    816825        pcib_conf_read32(signature, 16, &value);
    817826        sc->port = value & ~IO_MASK;
     
    828837        pcib_conf_read8(signature, 60, &interrupt);
    829838          sc->irqInfo.name = (rtems_irq_symbolic_name)interrupt;
    830        
     839#endif
     840#if defined(__PPC)
     841        (void)pci_read_config_dword(0,
     842                                    ucSlotNumber,
     843                                    ucFnNumber,
     844                                    PCI_BASE_ADDRESS_0,
     845                                    &lvalue);
     846
     847        sc->port = lvalue & (unsigned int)(~IO_MASK);
     848       
     849        (void)pci_read_config_dword(0,
     850                                    ucSlotNumber,
     851                                    ucFnNumber,
     852                                    PCI_BASE_ADDRESS_1  ,
     853                                    &lvalue);
     854
     855
     856        tmp = (unsigned int)(lvalue & (unsigned int)(~MEM_MASK))
     857          + (unsigned int)PREP_ISA_MEM_BASE;
     858        sc->base = (unsigned int *)(tmp);
     859
     860        (void)pci_read_config_byte(0,
     861                                   ucSlotNumber,
     862                                   ucFnNumber,
     863                                   PCI_INTERRUPT_LINE,
     864                                   &cvalue);
     865        sc->irqInfo.name = (rtems_irq_symbolic_name)cvalue;
     866#endif
    831867        if (config->hardware_address) {
    832868          memcpy (sc->arpcom.ac_enaddr, config->hardware_address,
     
    867903};
    868904
    869 
    870 
    871 
    872 
    873 
    874 
    875 
    876 
    877 
    878 
Note: See TracChangeset for help on using the changeset viewer.