Changeset 5a715de in rtems


Ignore:
Timestamp:
05/01/02 22:35:52 (22 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
b97b2202
Parents:
80fe968c
Message:

2002-04-30 Ralf Corsepius <corsepiu@…>

  • rtems/score/ppc.h: Remove rtems_multilib. Add mpc555 (Based on comments from Sergei Organov <osv@…>).
  • rtems/old-exceptions/cpu.h: Remove _CPU_Data_Cache_Block_Flush. Remove _CPU_Data_Cache_Block_Invalidate.
Files:
6 edited

Legend:

Unmodified
Added
Removed

  • c/src/exec/score/cpu/powerpc/ChangeLog

    r80fe968c r5a715de  
     12002-04-30      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
     2
     3        * rtems/score/ppc.h: Remove rtems_multilib.
     4        Add mpc555 (Based on comments from Sergei Organov <osv@javad.ru>).
     5        * rtems/old-exceptions/cpu.h: Remove _CPU_Data_Cache_Block_Flush.
     6        Remove _CPU_Data_Cache_Block_Invalidate.
     7
    182002-04-18      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    29

  • c/src/exec/score/cpu/powerpc/rtems/old-exceptions/cpu.h

    r80fe968c r5a715de  
    766766  }
    767767
    768 
    769 #define _CPU_Data_Cache_Block_Flush( _address ) \
    770   do { register void *__address = (_address); \
    771        register unsigned32 _zero = 0; \
    772        asm volatile ( "dcbf %0,%1" : \
    773                       "=r" (_zero), "=r" (__address) : \
    774                       "0" (_zero), "1" (__address) \
    775        ); \
    776   } while (0)
    777 
    778 #define _CPU_Data_Cache_Block_Invalidate( _address ) \
    779   do { register void *__address = (_address); \
    780        register unsigned32 _zero = 0; \
    781        asm volatile ( "dcbi %0,%1" : \
    782                       "=r" (_zero), "=r" (__address) : \
    783                       "0" (_zero), "1" (__address) \
    784        ); \
    785   } while (0)
    786 
    787 
    788768/*
    789769 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).

  • c/src/exec/score/cpu/powerpc/rtems/score/ppc.h

    r80fe968c r5a715de  
    9999#define PPC_LOW_POWER_MODE_STANDARD  1
    100100
    101 #if defined(rtems_multilib)
    102101/*
    103102 *  Figure out all CPU Model Feature Flags based upon compiler
    … …  
    105104 */
    106105
    107 #define CPU_MODEL_NAME           "rtems_multilib"
    108 #define PPC_ALIGNMENT            4 
    109 #define PPC_CACHE_ALIGNMENT      16
    110 #define PPC_HAS_RFCI             1
    111 #if defined(_SOFT_FLOAT)
    112 #define PPC_HAS_FPU              0
    113 #else
    114 #define PPC_HAS_FPU              1
    115 #endif
    116 
    117 #define PPC_USE_MULTIPLE         1
    118 #define PPC_I_CACHE              2048
    119 #define PPC_D_CACHE              1024
    120 #define PPC_DEBUG_MODEL          PPC_DEBUG_MODEL_STANDARD
    121 #define PPC_HAS_EXCEPTION_PREFIX 0
    122 #define PPC_HAS_EVPR             0
    123 #define PPC_INTERRUPT_MAX        16
    124 #define PPC_LOW_POWER_MODE       PPC_LOW_POWER_MODE_STANDARD
    125 #define PPC_HAS_DOUBLE           0
    126 
    127 #elif defined(ppc403) || defined(ppc405)
     106#if defined(ppc403) || defined(ppc405)
    128107/*
    129108 *  IBM 403
    … …  
    151130#define PPC_HAS_EVPR             1
    152131
     132#elif defined(mpc555)
     133
     134#define CPU_MODEL_NAME  "PowerPC 555"
     135
     136/* Copied from mpc505 */
     137#define PPC_ALIGNMENT           4
     138#define PPC_CACHE_ALIGNMENT     16
     139
     140/* Based on comments by Sergei Organov <osv@Javad.RU> */
     141#define PPC_I_CACHE             0
     142#define PPC_D_CACHE             0
    153143
    154144#elif defined(mpc505) || defined(mpc509)

  • cpukit/score/cpu/powerpc/ChangeLog

    r80fe968c r5a715de  
     12002-04-30      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
     2
     3        * rtems/score/ppc.h: Remove rtems_multilib.
     4        Add mpc555 (Based on comments from Sergei Organov <osv@javad.ru>).
     5        * rtems/old-exceptions/cpu.h: Remove _CPU_Data_Cache_Block_Flush.
     6        Remove _CPU_Data_Cache_Block_Invalidate.
     7
    182002-04-18      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    29

  • cpukit/score/cpu/powerpc/rtems/old-exceptions/cpu.h

    r80fe968c r5a715de  
    766766  }
    767767
    768 
    769 #define _CPU_Data_Cache_Block_Flush( _address ) \
    770   do { register void *__address = (_address); \
    771        register unsigned32 _zero = 0; \
    772        asm volatile ( "dcbf %0,%1" : \
    773                       "=r" (_zero), "=r" (__address) : \
    774                       "0" (_zero), "1" (__address) \
    775        ); \
    776   } while (0)
    777 
    778 #define _CPU_Data_Cache_Block_Invalidate( _address ) \
    779   do { register void *__address = (_address); \
    780        register unsigned32 _zero = 0; \
    781        asm volatile ( "dcbi %0,%1" : \
    782                       "=r" (_zero), "=r" (__address) : \
    783                       "0" (_zero), "1" (__address) \
    784        ); \
    785   } while (0)
    786 
    787 
    788768/*
    789769 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).

  • cpukit/score/cpu/powerpc/rtems/score/ppc.h

    r80fe968c r5a715de  
    9999#define PPC_LOW_POWER_MODE_STANDARD  1
    100100
    101 #if defined(rtems_multilib)
    102101/*
    103102 *  Figure out all CPU Model Feature Flags based upon compiler
    … …  
    105104 */
    106105
    107 #define CPU_MODEL_NAME           "rtems_multilib"
    108 #define PPC_ALIGNMENT            4 
    109 #define PPC_CACHE_ALIGNMENT      16
    110 #define PPC_HAS_RFCI             1
    111 #if defined(_SOFT_FLOAT)
    112 #define PPC_HAS_FPU              0
    113 #else
    114 #define PPC_HAS_FPU              1
    115 #endif
    116 
    117 #define PPC_USE_MULTIPLE         1
    118 #define PPC_I_CACHE              2048
    119 #define PPC_D_CACHE              1024
    120 #define PPC_DEBUG_MODEL          PPC_DEBUG_MODEL_STANDARD
    121 #define PPC_HAS_EXCEPTION_PREFIX 0
    122 #define PPC_HAS_EVPR             0
    123 #define PPC_INTERRUPT_MAX        16
    124 #define PPC_LOW_POWER_MODE       PPC_LOW_POWER_MODE_STANDARD
    125 #define PPC_HAS_DOUBLE           0
    126 
    127 #elif defined(ppc403) || defined(ppc405)
     106#if defined(ppc403) || defined(ppc405)
    128107/*
    129108 *  IBM 403
    … …  
    151130#define PPC_HAS_EVPR             1
    152131
     132#elif defined(mpc555)
     133
     134#define CPU_MODEL_NAME  "PowerPC 555"
     135
     136/* Copied from mpc505 */
     137#define PPC_ALIGNMENT           4
     138#define PPC_CACHE_ALIGNMENT     16
     139
     140/* Based on comments by Sergei Organov <osv@Javad.RU> */
     141#define PPC_I_CACHE             0
     142#define PPC_D_CACHE             0
    153143
    154144#elif defined(mpc505) || defined(mpc509)
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