Changeset 59a4066 in rtems


Ignore:
Timestamp:
Dec 11, 2007, 5:18:06 AM (12 years ago)
Author:
Till Straumann <strauman@…>
Branches:
4.10, 4.11, 4.9, master
Children:
f328b69
Parents:
7c86d66b
Message:

2007-12-10 Till Straumann <strauman@…>

  • new-exceptions/bspsupport/README, new-exceptions/bspsupport/ppc_exc_bspsupp.h new-exceptions/bspsupport/vectors_init.c: added crude test to make sure MMU maps memory as write-back enabled.
Location:
c/src/lib/libcpu/powerpc
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/powerpc/ChangeLog

    r7c86d66b r59a4066  
     12007-12-10      Till Straumann <strauman@slac.stanford.edu>
     2
     3        * new-exceptions/bspsupport/README,
     4        new-exceptions/bspsupport/ppc_exc_bspsupp.h
     5        new-exceptions/bspsupport/vectors_init.c:
     6        added crude test to make sure MMU maps memory as
     7        write-back enabled.
     8
    192007-12-09      Till Straumann <strauman@slac.stanford.edu>
    210
  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/README

    r7c86d66b r59a4066  
    243243                  to 'libbsp_a_LIBADD'
    244244
     245CAVEATS
     246=======
     247
     248On classic PPCs, early (and late) parts of the low-level
     249exception handling code run with the MMU disabled which mean
     250that the default caching attributes (write-back) are in effect
     251(thanks to Thomas Doerfler for bringing this up).
     252The code currently assumes that the MMU translations
     253for the task and interrupt stacks as well as some
     254variables in the data-area MATCH THE DEFAULT CACHING
     255ATTRIBUTES (this assumption also holds for the old code
     256in libbsp/powepc/shared/vectors ../irq).
     257
     258During initialization of exception handling, a crude test
     259is performed to check if memory seems to have the write-back
     260attribute. The 'dcbz' instruction should - on most PPCs - cause
     261an alignment exception if the tested cache-line does not
     262have this attribute.
     263
     264BSPs which entirely disable caching (e.g., by physically
     265disabling the cache(s)) should set the variable
     266  ppc_exc_cache_wb_check = 0
     267prior to calling initialize_exceptions().
     268Note that this check does not catch all possible
     269misconfigurations (e.g., on the 860, the default attribute
     270is AFAIK [libcpu/powerpc/mpc8xx/mmu/mmu_init.c] set to
     271'caching-disabled' which is potentially harmful but
     272this situation is not detected).
    245273
    246274
  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_bspsupp.h

    r7c86d66b r59a4066  
    4646 */
    4747extern uint32_t ppc_exc_msr_irq_mask;
     48
     49/* (See README under CAVEATS). During initialization
     50 * a check is performed to assert that write-back
     51 * caching is enabled for memory accesses. If a BSP
     52 * runs entirely without any caching then it should
     53 * set this variable to zero prior to initializing
     54 * exceptions in order to skip the test.
     55 * NOTE: The code does NOT support mapping memory
     56 *       with cache-attributes other than write-back
     57 *       (unless the entire cache is physically disabled)
     58 */
     59extern uint32_t ppc_exc_cache_wb_check;
    4860
    4961/*
  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors_init.c

    r7c86d66b r59a4066  
    2727static rtems_raw_except_connect_data    exception_table[LAST_VALID_EXC + 1];
    2828
     29uint32_t ppc_exc_cache_wb_check = 1;
     30
    2931#if 0
    3032typedef struct ppc_exc_connect_data_ {
     
    106108  int recoverable = 0;
    107109  int synch       = (int)excPtr->_EXC_number >= 0 ;
    108 
    109   printk("Exception handler called for exception %d\n", excPtr->_EXC_number & 0x7fff);
    110   printk("\t Next PC or Address of fault = %x\n", excPtr->EXC_SRR0);
    111   printk("\t Saved MSR = %x\n", excPtr->EXC_SRR1);
    112   printk("\t R0 = %08x",  excPtr->GPR0);
     110  unsigned n      = excPtr->_EXC_number & 0x7fff;
     111
     112  printk("Exception handler called for exception %d (0x%x)\n", n, n);
     113  printk("\t Next PC or Address of fault = %08x\n", excPtr->EXC_SRR0);
     114  printk("\t Saved MSR = %08x\n", excPtr->EXC_SRR1);
     115  printk("\t R0  = %08x", excPtr->GPR0);
    113116  if ( synch ) {
    114     printk(" R1 = %08x", excPtr->GPR1);
    115     printk(" R2 = %08x", excPtr->GPR2);
     117    printk(" R1  = %08x", excPtr->GPR1);
     118    printk(" R2  = %08x", excPtr->GPR2);
    116119  } else {
    117120    printk("              ");
    118121    printk("              ");
    119122  }
    120   printk(" R3 = %08x\n", excPtr->GPR3);
    121   printk("\t R4 = %08x", excPtr->GPR4);
    122   printk(" R5 = %08x",    excPtr->GPR5);
    123   printk(" R6 = %08x",    excPtr->GPR6);
    124   printk(" R7 = %08x\n", excPtr->GPR7);
    125   printk("\t R8 = %08x", excPtr->GPR8);
    126   printk(" R9 = %08x",    excPtr->GPR9);
     123  printk(" R3  = %08x\n", excPtr->GPR3);
     124  printk("\t R4  = %08x", excPtr->GPR4);
     125  printk(" R5  = %08x",   excPtr->GPR5);
     126  printk(" R6  = %08x",   excPtr->GPR6);
     127  printk(" R7  = %08x\n", excPtr->GPR7);
     128  printk("\t R8  = %08x", excPtr->GPR8);
     129  printk(" R9  = %08x",   excPtr->GPR9);
    127130  printk(" R10 = %08x",   excPtr->GPR10);
    128131  printk(" R11 = %08x\n", excPtr->GPR11);
     
    151154      printk("\n");
    152155  }
    153   printk("\t CR = %08x\n", excPtr->EXC_CR);
     156  printk("\t CR  = %08x\n", excPtr->EXC_CR);
    154157  printk("\t CTR = %08x\n", excPtr->EXC_CTR);
    155158  printk("\t XER = %08x\n", excPtr->EXC_XER);
    156   printk("\t LR = %08x\n", excPtr->EXC_LR);
     159  printk("\t LR  = %08x\n", excPtr->EXC_LR);
    157160
    158161  /* Would be great to print DAR but unfortunately,
     
    347350                exception_table[i].hdl.vector = i;
    348351        ppc_exc_init(exception_table, n);
    349 }
     352
     353        /* If we are on a classic PPC with MSR_DR enabled then
     354         * assert that the mapping for at least this task's
     355         * stack is write-back-caching enabled (see README/CAVEATS)
     356         * Do this only if the cache is physically enabled.
     357         * Since it is not easy to figure that out in a
     358         * generic way we need help from the BSP: BSPs
     359         * which run entirely w/o the cache may set
     360         * ppc_exc_cache_wb_check to zero prior to calling
     361         * this routine.
     362         *
     363         * We run this check only after exception handling is
     364         * initialized so that we have some chance to get
     365         * information printed if it fails.
     366         *
     367         * Note that it is unsafe to ignore this issue; if
     368         * the check fails, do NOT disable it unless caches
     369         * are always physically disabled.
     370         */
     371        if ( ppc_exc_cache_wb_check && (MSR_DR & ppc_exc_msr_bits) ) {
     372                /* The size of 63 assumes cache lines are at most 32 bytes */
     373                uint8_t   dummy[63];
     374                uintptr_t p = (uintptr_t)dummy;
     375                /* If the dcbz instruction raises an alignment exception
     376                 * then the stack is mapped as write-thru or caching-disabled.
     377                 * The low-level code is not capable of dealing with this
     378                 * ATM.
     379                 */
     380                p = (p + 31) & ~31;
     381                asm volatile("dcbz 0, %0"::"b"(p));
     382                /* If we make it thru here then things seem to be OK */
     383        }
     384
     385}
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