Changeset 599e6fbd in rtems


Ignore:
Timestamp:
Sep 19, 2017, 7:02:30 AM (2 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
fd70e206
Parents:
9a50e32
git-author:
Sebastian Huber <sebastian.huber@…> (09/19/17 07:02:30)
git-committer:
Sebastian Huber <sebastian.huber@…> (09/19/17 08:57:27)
Message:

bsps/powerpc: PPC_EXC_CONFIG_USE_FIXED_HANDLER

Make PPC_EXC_CONFIG_USE_FIXED_HANDLER mandatory for BSPs using
ppc_exc_interrupt(). Pass exception number to bsp_interrupt_dispatch()
to allow processing of decrementer and doorbell exceptions as hypervisor
guest.

Update #3085.

Location:
c/src/lib
Files:
7 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/mpc55xxevb/startup/bspstart.c

    r9a50e32 r599e6fbd  
    103103                mpc55xx_exc_vector_base
    104104        );
    105         #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
    106                 ppc_exc_set_handler(ASM_ALIGN_VECTOR, ppc_exc_alignment_handler);
    107         #endif
    108105
    109106        /* Initialize interrupts */
  • c/src/lib/libbsp/powerpc/mpc55xxevb/startup/exc-vector-base.S

    r9a50e32 r599e6fbd  
    6060        b       ppc_exc_wrap_nopush_std
    6161        stwu    r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
    62 #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
    63         stw     r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
    64         li      r4, -32763
    65 #endif
     62        stw     r3, GPR3_OFFSET(r1)
     63        li      r3, -32763
    6664        b       ppc_exc_interrupt
    67 #ifdef PPC_EXC_CONFIG_USE_FIXED_HANDLER
    68         nop
    69         nop
    70 #endif
    7165        stwu    r1, -EXC_GENERIC_SIZE(r1)
    7266        stw     r4, GPR4_OFFSET(r1)
     
    9084        b       ppc_exc_wrap_nopush_std
    9185        stwu    r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
    92 #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
    93         stw     r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
    94         li      r4, -32752
    95 #endif
     86        stw     r3, GPR3_OFFSET(r1)
     87        li      r3, -32752
    9688        b       ppc_exc_interrupt
    97 #ifdef PPC_EXC_CONFIG_USE_FIXED_HANDLER
    98         nop
    99         nop
    100 #endif
    10189        stwu    r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
    102 #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
    103         stw     r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
    104         li      r4, -32749
    105 #endif
     90        stw     r3, GPR3_OFFSET(r1)
     91        li      r3, -32749
    10692        b       ppc_exc_interrupt
    107 #ifdef PPC_EXC_CONFIG_USE_FIXED_HANDLER
    108         nop
    109         nop
    110 #endif
    11193        stw     r1, ppc_exc_lock_crit@sdarel(r13)
    11294        stw     r4, ppc_exc_vector_register_crit@sdarel(r13)
  • c/src/lib/libbsp/powerpc/qoriq/irq/irq.c

    r9a50e32 r599e6fbd  
    8686}
    8787
    88 void bsp_interrupt_dispatch(void)
     88void bsp_interrupt_dispatch(uintptr_t exception_number)
    8989{
    9090        unsigned int vector;
     
    264264}
    265265
    266 static void qoriq_interrupt_dispatch(void)
     266void bsp_interrupt_dispatch(uintptr_t exception_number)
    267267{
    268268        rtems_vector_number vector = qoriq.pic.iack;
     
    282282}
    283283
    284 #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
    285 static int qoriq_external_exception_handler(BSP_Exception_frame *frame, unsigned exception_number)
    286 {
    287         qoriq_interrupt_dispatch();
    288 
    289         return 0;
    290 }
    291 #else
    292 void bsp_interrupt_dispatch(void)
    293 {
    294         qoriq_interrupt_dispatch();
    295 }
    296 #endif
    297 
    298284static bool pic_is_ipi(rtems_vector_number vector)
    299285{
     
    326312        rtems_vector_number i = 0;
    327313        uint32_t processor_id = ppc_processor_id();
    328 
    329 #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
    330         if (ppc_exc_set_handler(ASM_EXT_VECTOR, qoriq_external_exception_handler)) {
    331                 return RTEMS_IO_ERROR;
    332         }
    333 #endif
    334314
    335315        if (processor_id == 0) {
  • c/src/lib/libbsp/powerpc/qoriq/start/start.S

    r9a50e32 r599e6fbd  
    387387        /* External input */
    388388        PPC_REG_STORE_UPDATE    r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
     389        PPC_REG_STORE   r3, GPR3_OFFSET(r1)
     390        li      r3, 4
    389391        b       ppc_exc_interrupt
    390         nop
    391         nop
    392392        START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
    393393        /* Alignment */
  • c/src/lib/libcpu/powerpc/mpc55xx/irq/irq.c

    r9a50e32 r599e6fbd  
    114114}
    115115
    116 static void mpc55xx_interrupt_dispatch(void)
     116void bsp_interrupt_dispatch(uintptr_t exception_number)
    117117{
    118         /* Acknowlege interrupt request */
     118        /* Acknowledge interrupt request */
    119119        rtems_vector_number vector = INTC.IACKR.B.INTVEC;
    120120
     
    132132}
    133133
    134 #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
    135 
    136 /**
    137  * @brief External exception handler.
    138  */
    139 static int mpc55xx_external_exception_handler( BSP_Exception_frame *frame, unsigned exception_number)
    140 {
    141         mpc55xx_interrupt_dispatch();
    142 
    143         return 0;
    144 }
    145 
    146 #else /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */
    147 
    148 void bsp_interrupt_dispatch(void)
    149 {
    150         mpc55xx_interrupt_dispatch();
    151 }
    152 
    153 #endif /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */
    154 
    155134rtems_status_code bsp_interrupt_facility_initialize(void)
    156135{
    157136        rtems_vector_number vector;
    158 
    159 #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
    160         /* Install exception handler */
    161         if (ppc_exc_set_handler( ASM_EXT_VECTOR, mpc55xx_external_exception_handler)) {
    162                 return RTEMS_IO_ERROR;
    163         }
    164 #endif
    165137
    166138        /* Initialize interrupt controller */
  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S

    r9a50e32 r599e6fbd  
    1717#include <bsp/vectors.h>
    1818
    19 #define VECTOR_REGISTER r4
    20 #define SELF_CPU_REGISTER r5
    21 #define ISR_NEST_REGISTER r6
    22 #define DISPATCH_LEVEL_REGISTER r7
    23 #define HANDLER_REGISTER r8
    2419#define SCRATCH_0_REGISTER r0
    2520#define SCRATCH_1_REGISTER r3
    26 #define SCRATCH_2_REGISTER r9
    27 #define SCRATCH_3_REGISTER r10
    28 #define SCRATCH_4_REGISTER r11
    29 #define SCRATCH_5_REGISTER r12
     21#define SCRATCH_2_REGISTER r4
     22#define SCRATCH_3_REGISTER r5
     23#define SCRATCH_4_REGISTER r6
     24#define SCRATCH_5_REGISTER r7
     25#define SCRATCH_6_REGISTER r8
     26#define SCRATCH_7_REGISTER r9
     27#define SCRATCH_8_REGISTER r10
     28#define SCRATCH_9_REGISTER r11
     29#define SCRATCH_10_REGISTER r12
    3030#define FRAME_REGISTER r14
    3131
    32 #define VECTOR_OFFSET GPR4_OFFSET
    33 #define SELF_CPU_OFFSET GPR5_OFFSET
    34 #define ISR_NEST_OFFSET GPR6_OFFSET
    35 #define DISPATCH_LEVEL_OFFSET GPR7_OFFSET
    36 #define HANDLER_OFFSET GPR8_OFFSET
    3732#define SCRATCH_0_OFFSET GPR0_OFFSET
    3833#define SCRATCH_1_OFFSET GPR3_OFFSET
    39 #define SCRATCH_2_OFFSET GPR9_OFFSET
    40 #define SCRATCH_3_OFFSET GPR10_OFFSET
    41 #define SCRATCH_4_OFFSET GPR11_OFFSET
    42 #define SCRATCH_5_OFFSET GPR12_OFFSET
     34#define SCRATCH_2_OFFSET GPR4_OFFSET
     35#define SCRATCH_3_OFFSET GPR5_OFFSET
     36#define SCRATCH_4_OFFSET GPR6_OFFSET
     37#define SCRATCH_5_OFFSET GPR7_OFFSET
     38#define SCRATCH_6_OFFSET GPR8_OFFSET
     39#define SCRATCH_7_OFFSET GPR9_OFFSET
     40#define SCRATCH_8_OFFSET GPR10_OFFSET
     41#define SCRATCH_9_OFFSET GPR11_OFFSET
     42#define SCRATCH_10_OFFSET GPR12_OFFSET
    4343#define FRAME_OFFSET PPC_EXC_INTERRUPT_FRAME_OFFSET
    4444
     
    5555#endif /* RTEMS_PROFILING */
    5656
    57 #ifdef PPC_EXC_CONFIG_USE_FIXED_HANDLER
    58         .global bsp_interrupt_dispatch
    59 #endif /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */
    60 
    6157        .global ppc_exc_min_prolog_async_tmpl_normal
    6258        .global ppc_exc_interrupt
     
    6561
    6662        stwu    r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
    67 
    68 #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
    69         stw     VECTOR_REGISTER, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
    70         li      VECTOR_REGISTER, 0xffff8000
    71 #endif /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */
     63        PPC_REG_STORE   SCRATCH_1_REGISTER, SCRATCH_1_OFFSET(r1)
     64        li      SCRATCH_1_REGISTER, 0xffff8000
    7265
    7366        /*
     
    112105        mr      FRAME_REGISTER, r1
    113106
    114         /* Load ISR nest level and thread dispatch disable level */
    115         PPC_GPR_STORE   SELF_CPU_REGISTER, SELF_CPU_OFFSET(r1)
    116         GET_SELF_CPU_CONTROL    SELF_CPU_REGISTER
    117         PPC_GPR_STORE   ISR_NEST_REGISTER, ISR_NEST_OFFSET(r1)
    118         lwz     ISR_NEST_REGISTER, PER_CPU_ISR_NEST_LEVEL(SELF_CPU_REGISTER)
    119         PPC_GPR_STORE   DISPATCH_LEVEL_REGISTER, DISPATCH_LEVEL_OFFSET(r1)
    120         lwz     DISPATCH_LEVEL_REGISTER, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(SELF_CPU_REGISTER)
    121 
     107        /*
     108         * Save volatile registers.  The SCRATCH_1_REGISTER has been saved in
     109         * minimum prologue.
     110         */
    122111        PPC_GPR_STORE   SCRATCH_0_REGISTER, SCRATCH_0_OFFSET(r1)
    123 
    124 #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
    125 #ifdef __SPE__
    126         /*
    127          * Save high order part of VECTOR_REGISTER here.  The low order part
    128          * was saved in the minimal prologue.
    129          */
    130         evmergehi       SCRATCH_0_REGISTER, SCRATCH_0_REGISTER, VECTOR_REGISTER
    131         stw     SCRATCH_0_REGISTER, VECTOR_OFFSET(r1)
    132 #endif
    133 #else /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */
    134         /* The vector register has no special purpose in this case */
    135         PPC_GPR_STORE   VECTOR_REGISTER, VECTOR_OFFSET(r1)
    136 #endif /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */
    137 
    138         PPC_GPR_STORE   HANDLER_REGISTER, HANDLER_OFFSET(r1)
    139 
    140 #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
    141         /*
    142          * Load the handler address.  Get the handler table index from the
    143          * vector number.  We have to discard the exception type.  Take only
    144          * the least significant five bits (= LAST_VALID_EXC + 1) from the
    145          * vector register.  Multiply by four (= size of function pointer).
    146          */
    147         rlwinm  SCRATCH_0_REGISTER, VECTOR_REGISTER, 2, 25, 29
    148         lis     HANDLER_REGISTER, ppc_exc_handler_table@h
    149         ori     HANDLER_REGISTER, HANDLER_REGISTER, ppc_exc_handler_table@l
    150         lwzx    HANDLER_REGISTER, HANDLER_REGISTER, SCRATCH_0_REGISTER
    151 #endif /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */
    152 
    153112#ifdef __powerpc64__
    154113        PPC_GPR_STORE   r2, GPR2_OFFSET(r1)
    155114        LA32    r2, .TOC.
    156115#endif
    157         PPC_GPR_STORE   SCRATCH_1_REGISTER, SCRATCH_1_OFFSET(r1)
    158116        PPC_GPR_STORE   SCRATCH_2_REGISTER, SCRATCH_2_OFFSET(r1)
     117        GET_SELF_CPU_CONTROL    SCRATCH_2_REGISTER
    159118        PPC_GPR_STORE   SCRATCH_3_REGISTER, SCRATCH_3_OFFSET(r1)
    160119        PPC_GPR_STORE   SCRATCH_4_REGISTER, SCRATCH_4_OFFSET(r1)
    161120        PPC_GPR_STORE   SCRATCH_5_REGISTER, SCRATCH_5_OFFSET(r1)
     121        PPC_GPR_STORE   SCRATCH_6_REGISTER, SCRATCH_6_OFFSET(r1)
     122        PPC_GPR_STORE   SCRATCH_7_REGISTER, SCRATCH_7_OFFSET(r1)
     123        PPC_GPR_STORE   SCRATCH_8_REGISTER, SCRATCH_8_OFFSET(r1)
     124        PPC_GPR_STORE   SCRATCH_9_REGISTER, SCRATCH_9_OFFSET(r1)
     125        PPC_GPR_STORE   SCRATCH_10_REGISTER, SCRATCH_10_OFFSET(r1)
     126
     127        /* Load ISR nest level and thread dispatch disable level */
     128        lwz     SCRATCH_3_REGISTER, PER_CPU_ISR_NEST_LEVEL(SCRATCH_2_REGISTER)
     129        lwz     SCRATCH_4_REGISTER, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(SCRATCH_2_REGISTER)
    162130
    163131        /* Save SRR0, SRR1, CR, XER, CTR, and LR */
    164132        mfsrr0  SCRATCH_0_REGISTER
    165         mfsrr1  SCRATCH_1_REGISTER
    166         mfcr    SCRATCH_2_REGISTER
    167         mfxer   SCRATCH_3_REGISTER
    168         mfctr   SCRATCH_4_REGISTER
    169         mflr    SCRATCH_5_REGISTER
     133        mfsrr1  SCRATCH_5_REGISTER
     134        mfcr    SCRATCH_6_REGISTER
     135        mfxer   SCRATCH_7_REGISTER
     136        mfctr   SCRATCH_8_REGISTER
     137        mflr    SCRATCH_9_REGISTER
    170138        PPC_REG_STORE   SCRATCH_0_REGISTER, SRR0_FRAME_OFFSET(r1)
    171         PPC_REG_STORE   SCRATCH_1_REGISTER, SRR1_FRAME_OFFSET(r1)
    172         stw     SCRATCH_2_REGISTER, EXC_CR_OFFSET(r1)
    173         stw     SCRATCH_3_REGISTER, EXC_XER_OFFSET(r1)
    174         PPC_REG_STORE   SCRATCH_4_REGISTER, EXC_CTR_OFFSET(r1)
    175         PPC_REG_STORE   SCRATCH_5_REGISTER, EXC_LR_OFFSET(r1)
     139        PPC_REG_STORE   SCRATCH_5_REGISTER, SRR1_FRAME_OFFSET(r1)
     140        stw     SCRATCH_6_REGISTER, EXC_CR_OFFSET(r1)
     141        stw     SCRATCH_7_REGISTER, EXC_XER_OFFSET(r1)
     142        PPC_REG_STORE   SCRATCH_8_REGISTER, EXC_CTR_OFFSET(r1)
     143        PPC_REG_STORE   SCRATCH_9_REGISTER, EXC_LR_OFFSET(r1)
    176144
    177145#ifdef __SPE__
    178146        /* Save SPEFSCR and ACC */
    179147        mfspr   SCRATCH_0_REGISTER, FSL_EIS_SPEFSCR
    180         evxor   SCRATCH_1_REGISTER, SCRATCH_1_REGISTER, SCRATCH_1_REGISTER
    181         evmwumiaa       SCRATCH_1_REGISTER, SCRATCH_1_REGISTER, SCRATCH_1_REGISTER
     148        evxor   SCRATCH_5_REGISTER, SCRATCH_5_REGISTER, SCRATCH_5_REGISTER
     149        evmwumiaa       SCRATCH_5_REGISTER, SCRATCH_5_REGISTER, SCRATCH_5_REGISTER
    182150        stw     SCRATCH_0_REGISTER, PPC_EXC_SPEFSCR_OFFSET(r1)
    183         evstdd  SCRATCH_1_REGISTER, PPC_EXC_ACC_OFFSET(r1)
     151        evstdd  SCRATCH_5_REGISTER, PPC_EXC_ACC_OFFSET(r1)
    184152#endif
    185153
     
    252220
    253221        /* Increment ISR nest level and thread dispatch disable level */
    254         cmpwi   ISR_NEST_REGISTER, 0
     222        cmpwi   SCRATCH_3_REGISTER, 0
    255223#ifdef RTEMS_PROFILING
    256         cmpwi   cr2, ISR_NEST_REGISTER, 0
    257 #endif
    258         addi    ISR_NEST_REGISTER, ISR_NEST_REGISTER, 1
    259         addi    DISPATCH_LEVEL_REGISTER, DISPATCH_LEVEL_REGISTER, 1
    260         stw     ISR_NEST_REGISTER, PER_CPU_ISR_NEST_LEVEL(SELF_CPU_REGISTER)
    261         stw     DISPATCH_LEVEL_REGISTER, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(SELF_CPU_REGISTER)
     224        cmpwi   cr2, SCRATCH_3_REGISTER, 0
     225#endif
     226        addi    SCRATCH_3_REGISTER, SCRATCH_3_REGISTER, 1
     227        addi    SCRATCH_4_REGISTER, SCRATCH_4_REGISTER, 1
     228        stw     SCRATCH_3_REGISTER, PER_CPU_ISR_NEST_LEVEL(SCRATCH_2_REGISTER)
     229        stw     SCRATCH_4_REGISTER, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(SCRATCH_2_REGISTER)
    262230
    263231        /* Switch stack if necessary */
     
    265233        iselgt  r1, r1, SCRATCH_0_REGISTER
    266234
    267 #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
    268         /*
    269          * Call high level exception handler.
    270          *
    271          * First parameter = exception frame pointer + FRAME_LINK_SPACE
    272          * Second parameter = vector number (r4 is the VECTOR_REGISTER)
    273          */
    274         addi    r3, FRAME_REGISTER, FRAME_LINK_SPACE
    275         rlwinm  VECTOR_REGISTER, VECTOR_REGISTER, 0, 27, 31
    276         mtctr   HANDLER_REGISTER
    277         bctrl
    278 #else /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */
    279235        /* Call fixed high level handler */
    280236        bl      bsp_interrupt_dispatch
    281237        PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
    282 #endif /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */
    283238
    284239#ifdef RTEMS_PROFILING
     
    294249
    295250        /* Load some per-CPU variables */
    296         GET_SELF_CPU_CONTROL    SELF_CPU_REGISTER
    297         lbz     SCRATCH_0_REGISTER, PER_CPU_DISPATCH_NEEDED(SELF_CPU_REGISTER)
    298         lwz     SCRATCH_1_REGISTER, PER_CPU_ISR_DISPATCH_DISABLE(SELF_CPU_REGISTER)
    299         lwz     SCRATCH_2_REGISTER, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(SELF_CPU_REGISTER)
    300         lwz     ISR_NEST_REGISTER, PER_CPU_ISR_NEST_LEVEL(SELF_CPU_REGISTER)
     251        GET_SELF_CPU_CONTROL    SCRATCH_1_REGISTER
     252        lbz     SCRATCH_0_REGISTER, PER_CPU_DISPATCH_NEEDED(SCRATCH_1_REGISTER)
     253        lwz     SCRATCH_5_REGISTER, PER_CPU_ISR_DISPATCH_DISABLE(SCRATCH_1_REGISTER)
     254        lwz     SCRATCH_6_REGISTER, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(SCRATCH_1_REGISTER)
     255        lwz     SCRATCH_3_REGISTER, PER_CPU_ISR_NEST_LEVEL(SCRATCH_1_REGISTER)
    301256
    302257        /*
     
    309264        /* Decrement levels and determine thread dispatch state */
    310265        xori    SCRATCH_0_REGISTER, SCRATCH_0_REGISTER, 1
    311         or      SCRATCH_0_REGISTER, SCRATCH_0_REGISTER, SCRATCH_1_REGISTER
    312         subi    DISPATCH_LEVEL_REGISTER, SCRATCH_2_REGISTER, 1
    313         or.     SCRATCH_0_REGISTER, SCRATCH_0_REGISTER, DISPATCH_LEVEL_REGISTER
    314         subi    ISR_NEST_REGISTER, ISR_NEST_REGISTER, 1
     266        or      SCRATCH_0_REGISTER, SCRATCH_0_REGISTER, SCRATCH_5_REGISTER
     267        subi    SCRATCH_4_REGISTER, SCRATCH_6_REGISTER, 1
     268        or.     SCRATCH_0_REGISTER, SCRATCH_0_REGISTER, SCRATCH_4_REGISTER
     269        subi    SCRATCH_3_REGISTER, SCRATCH_3_REGISTER, 1
    315270
    316271        /* Store thread dispatch disable and ISR nest levels */
    317         stw     DISPATCH_LEVEL_REGISTER, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(SELF_CPU_REGISTER)
    318         stw     ISR_NEST_REGISTER, PER_CPU_ISR_NEST_LEVEL(SELF_CPU_REGISTER)
     272        stw     SCRATCH_4_REGISTER, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(SCRATCH_1_REGISTER)
     273        stw     SCRATCH_3_REGISTER, PER_CPU_ISR_NEST_LEVEL(SCRATCH_1_REGISTER)
    319274
    320275        /*
     
    329284        /* Set ISR dispatch disable and thread dispatch disable level to one */
    330285        li      SCRATCH_0_REGISTER, 1
    331         stw     SCRATCH_0_REGISTER, PER_CPU_ISR_DISPATCH_DISABLE(SELF_CPU_REGISTER)
    332         stw     SCRATCH_0_REGISTER, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(SELF_CPU_REGISTER)
    333 
    334         /* Call _Thread_Do_dispatch(), this function will enable interrupts */
    335         mr      r3, SELF_CPU_REGISTER
     286        stw     SCRATCH_0_REGISTER, PER_CPU_ISR_DISPATCH_DISABLE(SCRATCH_1_REGISTER)
     287        stw     SCRATCH_0_REGISTER, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(SCRATCH_1_REGISTER)
     288
     289        /*
     290         * Call _Thread_Do_dispatch(), this function will enable interrupts.
     291         * The r3 is SCRATCH_1_REGISTER.
     292         */
    336293        mfmsr   r4
    337294        ori     r4, r4, MSR_EE
     
    342299        wrteei  0
    343300
    344         /* SELF_CPU_REGISTER is volatile, we must set it again */
    345         GET_SELF_CPU_CONTROL    SELF_CPU_REGISTER
     301        /* SCRATCH_1_REGISTER is volatile, we must set it again */
     302        GET_SELF_CPU_CONTROL    SCRATCH_1_REGISTER
    346303
    347304        /* Check if we have to do the thread dispatch again */
    348         lbz     SCRATCH_0_REGISTER, PER_CPU_DISPATCH_NEEDED(SELF_CPU_REGISTER)
     305        lbz     SCRATCH_0_REGISTER, PER_CPU_DISPATCH_NEEDED(SCRATCH_1_REGISTER)
    349306        cmpwi   SCRATCH_0_REGISTER, 0
    350307        bne     .Ldo_thread_dispatch
     
    352309        /* We are done with thread dispatching */
    353310        li      SCRATCH_0_REGISTER, 0
    354         stw     SCRATCH_0_REGISTER, PER_CPU_ISR_DISPATCH_DISABLE(SELF_CPU_REGISTER)
     311        stw     SCRATCH_0_REGISTER, PER_CPU_ISR_DISPATCH_DISABLE(SCRATCH_1_REGISTER)
    355312
    356313.Lthread_dispatch_done:
     
    425382#ifdef __SPE__
    426383        /* Load SPEFSCR and ACC */
    427         lwz     DISPATCH_LEVEL_REGISTER, PPC_EXC_SPEFSCR_OFFSET(r1)
    428         evldd   HANDLER_REGISTER, PPC_EXC_ACC_OFFSET(r1)
     384        lwz     SCRATCH_3_REGISTER, PPC_EXC_SPEFSCR_OFFSET(r1)
     385        evldd   SCRATCH_4_REGISTER, PPC_EXC_ACC_OFFSET(r1)
    429386#endif
    430387
     
    455412
    456413        /* Load SRR0, SRR1, CR, XER, CTR, and LR */
    457         PPC_REG_LOAD    SCRATCH_0_REGISTER, SRR0_FRAME_OFFSET(r1)
    458         PPC_REG_LOAD    SCRATCH_1_REGISTER, SRR1_FRAME_OFFSET(r1)
    459         lwz     SCRATCH_2_REGISTER, EXC_CR_OFFSET(r1)
    460         lwz     SCRATCH_3_REGISTER, EXC_XER_OFFSET(r1)
    461         PPC_REG_LOAD    SCRATCH_4_REGISTER, EXC_CTR_OFFSET(r1)
    462         PPC_REG_LOAD    SCRATCH_5_REGISTER, EXC_LR_OFFSET(r1)
    463 
    464         PPC_GPR_LOAD    VECTOR_REGISTER, VECTOR_OFFSET(r1)
    465         PPC_GPR_LOAD    SELF_CPU_REGISTER, SELF_CPU_OFFSET(r1)
    466         PPC_GPR_LOAD    ISR_NEST_REGISTER, ISR_NEST_OFFSET(r1)
    467 
    468 #ifdef __SPE__
    469         /* Restore SPEFSCR */
    470         mtspr   FSL_EIS_SPEFSCR, DISPATCH_LEVEL_REGISTER
    471 #endif
    472         PPC_GPR_LOAD    DISPATCH_LEVEL_REGISTER, DISPATCH_LEVEL_OFFSET(r1)
    473 
    474 #ifdef __SPE__
    475         /* Restore ACC */
    476         evmra   HANDLER_REGISTER, HANDLER_REGISTER
    477 #endif
    478         PPC_GPR_LOAD    HANDLER_REGISTER, HANDLER_OFFSET(r1)
    479 
    480         /* Restore SRR0, SRR1, CR, CTR, XER, and LR */
    481         mtsrr0  SCRATCH_0_REGISTER
     414        PPC_REG_LOAD    SCRATCH_5_REGISTER, SRR0_FRAME_OFFSET(r1)
     415        PPC_REG_LOAD    SCRATCH_6_REGISTER, SRR1_FRAME_OFFSET(r1)
     416        lwz     SCRATCH_7_REGISTER, EXC_CR_OFFSET(r1)
     417        lwz     SCRATCH_8_REGISTER, EXC_XER_OFFSET(r1)
     418        PPC_REG_LOAD    SCRATCH_9_REGISTER, EXC_CTR_OFFSET(r1)
     419        PPC_REG_LOAD    SCRATCH_10_REGISTER, EXC_LR_OFFSET(r1)
     420
     421        /* Restore volatile registers */
    482422        PPC_GPR_LOAD    SCRATCH_0_REGISTER, SCRATCH_0_OFFSET(r1)
    483         mtsrr1  SCRATCH_1_REGISTER
    484423#ifdef __powerpc64__
    485424        PPC_GPR_LOAD    r2, GPR2_OFFSET(r1)
    486425#endif
    487426        PPC_GPR_LOAD    SCRATCH_1_REGISTER, SCRATCH_1_OFFSET(r1)
    488         mtcr    SCRATCH_2_REGISTER
    489427        PPC_GPR_LOAD    SCRATCH_2_REGISTER, SCRATCH_2_OFFSET(r1)
    490         mtxer   SCRATCH_3_REGISTER
     428
     429#ifdef __SPE__
     430        /* Restore SPEFSCR and ACC */
     431        mtspr   FSL_EIS_SPEFSCR, SCRATCH_3_REGISTER
     432        evmra   SCRATCH_4_REGISTER, SCRATCH_4_REGISTER
     433#endif
     434
     435        /* Restore volatile registers */
    491436        PPC_GPR_LOAD    SCRATCH_3_REGISTER, SCRATCH_3_OFFSET(r1)
    492         mtctr   SCRATCH_4_REGISTER
    493437        PPC_GPR_LOAD    SCRATCH_4_REGISTER, SCRATCH_4_OFFSET(r1)
    494         mtlr    SCRATCH_5_REGISTER
     438
     439        /* Restore SRR0, SRR1, CR, CTR, XER, and LR plus volatile registers */
     440        mtsrr0  SCRATCH_5_REGISTER
    495441        PPC_GPR_LOAD    SCRATCH_5_REGISTER, SCRATCH_5_OFFSET(r1)
     442        mtsrr1  SCRATCH_6_REGISTER
     443        PPC_GPR_LOAD    SCRATCH_6_REGISTER, SCRATCH_6_OFFSET(r1)
     444        mtcr    SCRATCH_7_REGISTER
     445        PPC_GPR_LOAD    SCRATCH_7_REGISTER, SCRATCH_7_OFFSET(r1)
     446        mtxer   SCRATCH_8_REGISTER
     447        PPC_GPR_LOAD    SCRATCH_8_REGISTER, SCRATCH_8_OFFSET(r1)
     448        mtctr   SCRATCH_9_REGISTER
     449        PPC_GPR_LOAD    SCRATCH_9_REGISTER, SCRATCH_9_OFFSET(r1)
     450        mtlr    SCRATCH_10_REGISTER
     451        PPC_GPR_LOAD    SCRATCH_10_REGISTER, SCRATCH_10_OFFSET(r1)
    496452
    497453        /* Pop stack */
  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h

    r9a50e32 r599e6fbd  
    423423   * @brief Interrupt dispatch routine provided by BSP.
    424424   */
    425   void bsp_interrupt_dispatch(void);
     425  void bsp_interrupt_dispatch(uintptr_t exception_number);
    426426#endif /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */
    427427
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