Changeset 582553d9 in rtems


Ignore:
Timestamp:
Dec 21, 2013, 9:46:33 PM (5 years ago)
Author:
Daniel Ramirez <javamonn@…>
Branches:
4.11, master
Children:
c0f731d
Parents:
49232d0
git-author:
Daniel Ramirez <javamonn@…> (12/21/13 21:46:33)
git-committer:
Gedare Bloom <gedare@…> (12/22/13 19:22:18)
Message:

arm_gp32: added new doxygen

Location:
c/src/lib/libbsp/arm/gp32
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/gp32/include/bsp.h

    r49232d0 r582553d9  
    11/**
    2  *  @file
    3  *
    4  *  This include file contains definitions related to the GP32 BSP.
     2 * @file
     3 * @ingroup arm_gp32
     4 * @brief Global BSP definitons.
    55 */
    66
     
    3636    ( (((~rPEDAT >> 6) & 0x3 )<<8) | (((~rPBDAT >> 8) & 0xFF)<<0) )
    3737
    38 /*functions to get the differents s3c2400 clks*/
     38/**
     39 * @defgroup arm_gp32 GP32 Support
     40 * @ingroup bsp_arm
     41 * @brief GP32 Support Pacakge
     42 * @{
     43 */
     44
     45/**
     46 * @brief functions to get the differents s3c2400 clks
     47 * @{
     48 */
     49
    3950uint32_t get_FCLK(void);
    4051uint32_t get_HCLK(void);
     
    4253uint32_t get_UCLK(void);
    4354
     55/** @} */
    4456
    4557void gp32_setPalette( unsigned char pos, uint16_t color);
    4658
    4759/* What is the input clock freq in hertz? */
    48 #define BSP_OSC_FREQ  12000000    /* 12 MHz oscillator */
    49 #define M_MDIV 81       /* FCLK=133Mhz */
     60/** @brief 12 MHz oscillator */
     61#define BSP_OSC_FREQ  12000000
     62/** @brief FCLK=133Mhz */
     63#define M_MDIV 81
    5064#define M_PDIV 2
    5165#define M_SDIV 1
    52 #define M_CLKDIVN 2     /* HCLK=FCLK/2, PCLK=FCLK/2 */
     66/** @brief HCLK=FCLK/2, PCLK=FCLK/2 */
     67#define M_CLKDIVN 2
     68/** @brief enable refresh */
     69#define REFEN   0x1
     70/** @brief CBR(CAS before RAS)/auto refresh */
     71#define TREFMD  0x0
     72/** @brief 2 clk */
     73#define Trp     0x0
     74/** @brief 7 clk */
     75#define Trc     0x3
     76/** @brief 3 clk */
     77#define Tchr    0x2
    5378
    54 #define REFEN   0x1     /* enable refresh */
    55 #define TREFMD  0x0     /* CBR(CAS before RAS)/auto refresh */
    56 #define Trp     0x0     /* 2 clk */
    57 #define Trc     0x3     /* 7 clk */
    58 #define Tchr    0x2     /* 3 clk */
    59 
    60 
    61 /*
    62  *  This BSP provides its own IDLE thread to override the RTEMS one.
     79/**
     80 * @brief This BSP provides its own IDLE thread to override the RTEMS one.
     81 *
    6382 *  So we prototype it and define the constant confdefs.h expects
    6483 *  to configure a BSP specific one.
    6584 */
    6685void *bsp_idle_thread(uintptr_t ignored);
     86
     87/** @} */
    6788
    6889#define BSP_IDLE_TASK_BODY bsp_idle_thread
  • c/src/lib/libbsp/arm/gp32/smc/smc.h

    r49232d0 r582553d9  
     1/**
     2 * @file
     3 * @ingroup gp32_smc
     4 * @brief SMC disk driver initialization entry point
     5 */
     6
    17#ifndef __SMC_H__
    28#define __SMC_H__
     
    1016#include "rtems/blkdev.h"
    1117
    12 /* smc_initialize --
     18/**
     19 * @defgroup gp32_smc SMC Disk Driver
     20 * @ingroup arm_gp32
     21 * @brief SMC Disk Driver Support
     22 * @{
     23 */
     24
     25/**
     26 * @brief smc_initialize
    1327 *     SMC disk driver initialization entry point.
    1428 */
     
    2236    { smc_initialize, GENERIC_BLOCK_DEVICE_DRIVER_ENTRIES }
    2337
     38/** @} */
     39
    2440#ifdef __cplusplus
    2541}
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