Index: bsps/arm/beagle/include/bsp.h
===================================================================
--- bsps/arm/beagle/include/bsp.h	(revision e1fdf975acdcd33a52cdc5d1c746c6946c90394e)
+++ bsps/arm/beagle/include/bsp.h	(revision 5810a08b574413a3aa66552d5eef62ab9bae0ce9)
@@ -117,5 +117,5 @@
 static inline void dsb(void)
 {
-    asm volatile("dsb" : : : "memory");
+    __asm__ volatile("dsb" : : : "memory");
 }
 
@@ -123,5 +123,5 @@
 static inline void isb(void)
 {
-    asm volatile("isb" : : : "memory");
+    __asm__ volatile("isb" : : : "memory");
 }
 
@@ -129,5 +129,5 @@
 static inline void flush_data_cache(void)
 {
-    asm volatile(
+    __asm__ volatile(
         "mov r0, #0\n"
         "mcr p15, #0, r0, c7, c10, #4\n"
@@ -230,5 +230,5 @@
     uint32_t ctl;
 
-    asm volatile("mrc p15, 0, %[ctl], c1, c0, 0 @ Read SCTLR\n\t"
+    __asm__ volatile("mrc p15, 0, %[ctl], c1, c0, 0 @ Read SCTLR\n\t"
         : [ctl] "=r" (ctl));
     return ctl;
@@ -238,5 +238,5 @@
 static inline void write_sctlr(uint32_t ctl)
 {
-    asm volatile("mcr p15, 0, %[ctl], c1, c0, 0 @ Write SCTLR\n\t"
+    __asm__ volatile("mcr p15, 0, %[ctl], c1, c0, 0 @ Write SCTLR\n\t"
         : : [ctl] "r" (ctl));
     isb();
@@ -248,5 +248,5 @@
     uint32_t ctl;
 
-    asm volatile("mrc p15, 0, %[ctl], c1, c0, 1 @ Read ACTLR\n\t"
+    __asm__ volatile("mrc p15, 0, %[ctl], c1, c0, 1 @ Read ACTLR\n\t"
             : [ctl] "=r" (ctl));
     return ctl;
@@ -256,5 +256,5 @@
 static inline void write_actlr(uint32_t ctl)
 {
-    asm volatile("mcr p15, 0, %[ctl], c1, c0, 1 @ Write ACTLR\n\t"
+    __asm__ volatile("mcr p15, 0, %[ctl], c1, c0, 1 @ Write ACTLR\n\t"
         : : [ctl] "r" (ctl));
     isb();
@@ -264,5 +264,5 @@
 static inline void write_ttbcr(uint32_t bcr)
 {
-        asm volatile("mcr p15, 0, %[bcr], c2, c0, 2 @ Write TTBCR\n\t"
+        __asm__ volatile("mcr p15, 0, %[bcr], c2, c0, 2 @ Write TTBCR\n\t"
                         : : [bcr] "r" (bcr));
 
@@ -275,5 +275,5 @@
         uint32_t dacr;
 
-        asm volatile("mrc p15, 0, %[dacr], c3, c0, 0 @ Read DACR\n\t"
+        __asm__ volatile("mrc p15, 0, %[dacr], c3, c0, 0 @ Read DACR\n\t"
                         : [dacr] "=r" (dacr));
 
@@ -285,5 +285,5 @@
 static inline void write_dacr(uint32_t dacr)
 {
-        asm volatile("mcr p15, 0, %[dacr], c3, c0, 0 @ Write DACR\n\t"
+        __asm__ volatile("mcr p15, 0, %[dacr], c3, c0, 0 @ Write DACR\n\t"
                         : : [dacr] "r" (dacr));
 
@@ -296,14 +296,14 @@
 
     /* Invalidate entire unified TLB */
-    asm volatile("mcr p15, 0, %[zero], c8, c7, 0 @ TLBIALL\n\t"
+    __asm__ volatile("mcr p15, 0, %[zero], c8, c7, 0 @ TLBIALL\n\t"
         : : [zero] "r" (0));
 
     /* Invalidate all instruction caches to PoU.
      * Also flushes branch target cache. */
-    asm volatile("mcr p15, 0, %[zero], c7, c5, 0"
+    __asm__ volatile("mcr p15, 0, %[zero], c7, c5, 0"
         : : [zero] "r" (0));
 
     /* Invalidate entire branch predictor array */
-    asm volatile("mcr p15, 0, %[zero], c7, c5, 6"
+    __asm__ volatile("mcr p15, 0, %[zero], c7, c5, 6"
         : : [zero] "r" (0)); /* flush BTB */
 
@@ -317,5 +317,5 @@
     uint32_t bar;
 
-    asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
+    __asm__ volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
         : [bar] "=r" (bar));
 
@@ -329,5 +329,5 @@
     uint32_t bar;
 
-    asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
+    __asm__ volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
         : [bar] "=r" (bar));
 
@@ -345,5 +345,5 @@
        flags here and remove them in the read_ttbr0 */
     uint32_t v  =  (bar  & ARM_TTBR_ADDR_MASK ) | ARM_TTBR_FLAGS_CACHED;
-    asm volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t"
+    __asm__ volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t"
         : : [bar] "r" (v));
 
Index: bsps/powerpc/include/bsp/tictac.h
===================================================================
--- bsps/powerpc/include/bsp/tictac.h	(revision e1fdf975acdcd33a52cdc5d1c746c6946c90394e)
+++ bsps/powerpc/include/bsp/tictac.h	(revision 5810a08b574413a3aa66552d5eef62ab9bae0ce9)
@@ -39,5 +39,5 @@
 {
 	uint32_t tmp;
-	asm volatile (
+	__asm__ volatile (
 		"mftb 0;"
 		"stw 0, ppc_tic_tac@sdarel(13);"
@@ -53,5 +53,5 @@
 	uint32_t ticks;
 	uint32_t tmp;
-	asm volatile (
+	__asm__ volatile (
 		"mftb %0;"
 		"lwz %1, ppc_tic_tac@sdarel(13);"
@@ -68,5 +68,5 @@
 {
 	uint32_t tmp;
-	asm volatile (
+	__asm__ volatile (
 		"mftb 0;"
 		"stw 0, ppc_boom_bam@sdarel(13);"
@@ -82,5 +82,5 @@
 	uint32_t ticks;
 	uint32_t tmp;
-	asm volatile (
+	__asm__ volatile (
 		"mftb %0;"
 		"lwz %1, ppc_boom_bam@sdarel(13);"
Index: bsps/powerpc/include/libcpu/spr.h
===================================================================
--- bsps/powerpc/include/libcpu/spr.h	(revision e1fdf975acdcd33a52cdc5d1c746c6946c90394e)
+++ bsps/powerpc/include/libcpu/spr.h	(revision 5810a08b574413a3aa66552d5eef62ab9bae0ce9)
@@ -52,5 +52,5 @@
 {
 	unsigned long val;
-	asm volatile("mfmsr %0" : "=r" (val));
+	__asm__ volatile("mfmsr %0" : "=r" (val));
 	return val;
 }
@@ -58,5 +58,5 @@
 static inline void _write_MSR(unsigned long val)
 {
-	asm volatile("mtmsr %0" : : "r" (val));
+	__asm__ volatile("mtmsr %0" : : "r" (val));
 	return;
 }
@@ -65,5 +65,5 @@
 {
 	unsigned long val;
-	asm volatile (
+	__asm__ volatile (
 		".machine \"push\"\n"
 		".machine \"any\"\n"
@@ -78,5 +78,5 @@
 static inline void _write_SR(unsigned long val, void * va)
 {
-	asm volatile (
+	__asm__ volatile (
 		".machine \"push\"\n"
 		".machine \"any\"\n"
Index: cpukit/score/cpu/or1k/include/rtems/score/or1k-utility.h
===================================================================
--- cpukit/score/cpu/or1k/include/rtems/score/or1k-utility.h	(revision e1fdf975acdcd33a52cdc5d1c746c6946c90394e)
+++ cpukit/score/cpu/or1k/include/rtems/score/or1k-utility.h	(revision 5810a08b574413a3aa66552d5eef62ab9bae0ce9)
@@ -346,5 +346,5 @@
    uint32_t spr_value;
 
-   asm volatile (
+   __asm__ volatile (
      "l.mfspr  %0, %1, 0;\n\t"
      : "=r" (spr_value) : "r" (reg));
@@ -355,5 +355,5 @@
 static inline void _OR1K_mtspr(uint32_t reg, uint32_t value)
 {
-   asm volatile (
+   __asm__ volatile (
      "l.mtspr  %1, %0, 0;\n\t"
      :: "r" (value), "r" (reg)
@@ -387,10 +387,10 @@
 static inline void _OR1K_Sync_mem( void )
 {
-  asm volatile("l.msync");
+  __asm__ volatile("l.msync");
 }
 
 static inline void _OR1K_Sync_pipeline( void )
 {
-  asm volatile("l.psync");
+  __asm__ volatile("l.psync");
 }
 
@@ -403,5 +403,5 @@
  */
 #define _OR1KSIM_CPU_Halt() \
-	asm volatile ("l.nop 0xc")
+	__asm__ volatile ("l.nop 0xc")
 
 #ifdef __cplusplus
