Changeset 5810a08 in rtems


Ignore:
Timestamp:
07/27/22 13:20:32 (7 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
b868d0a
Parents:
e1fdf97
git-author:
Sebastian Huber <sebastian.huber@…> (07/27/22 13:20:32)
git-committer:
Sebastian Huber <sebastian.huber@…> (07/27/22 15:01:14)
Message:

Use asm for standard C compatibility

Files:
4 edited

Legend:

Unmodified
Added
Removed
  • bsps/arm/beagle/include/bsp.h

    re1fdf97 r5810a08  
    117117static inline void dsb(void)
    118118{
    119     asm volatile("dsb" : : : "memory");
     119    __asm__ volatile("dsb" : : : "memory");
    120120}
    121121
     
    123123static inline void isb(void)
    124124{
    125     asm volatile("isb" : : : "memory");
     125    __asm__ volatile("isb" : : : "memory");
    126126}
    127127
     
    129129static inline void flush_data_cache(void)
    130130{
    131     asm volatile(
     131    __asm__ volatile(
    132132        "mov r0, #0\n"
    133133        "mcr p15, #0, r0, c7, c10, #4\n"
     
    230230    uint32_t ctl;
    231231
    232     asm volatile("mrc p15, 0, %[ctl], c1, c0, 0 @ Read SCTLR\n\t"
     232    __asm__ volatile("mrc p15, 0, %[ctl], c1, c0, 0 @ Read SCTLR\n\t"
    233233        : [ctl] "=r" (ctl));
    234234    return ctl;
     
    238238static inline void write_sctlr(uint32_t ctl)
    239239{
    240     asm volatile("mcr p15, 0, %[ctl], c1, c0, 0 @ Write SCTLR\n\t"
     240    __asm__ volatile("mcr p15, 0, %[ctl], c1, c0, 0 @ Write SCTLR\n\t"
    241241        : : [ctl] "r" (ctl));
    242242    isb();
     
    248248    uint32_t ctl;
    249249
    250     asm volatile("mrc p15, 0, %[ctl], c1, c0, 1 @ Read ACTLR\n\t"
     250    __asm__ volatile("mrc p15, 0, %[ctl], c1, c0, 1 @ Read ACTLR\n\t"
    251251            : [ctl] "=r" (ctl));
    252252    return ctl;
     
    256256static inline void write_actlr(uint32_t ctl)
    257257{
    258     asm volatile("mcr p15, 0, %[ctl], c1, c0, 1 @ Write ACTLR\n\t"
     258    __asm__ volatile("mcr p15, 0, %[ctl], c1, c0, 1 @ Write ACTLR\n\t"
    259259        : : [ctl] "r" (ctl));
    260260    isb();
     
    264264static inline void write_ttbcr(uint32_t bcr)
    265265{
    266         asm volatile("mcr p15, 0, %[bcr], c2, c0, 2 @ Write TTBCR\n\t"
     266        __asm__ volatile("mcr p15, 0, %[bcr], c2, c0, 2 @ Write TTBCR\n\t"
    267267                        : : [bcr] "r" (bcr));
    268268
     
    275275        uint32_t dacr;
    276276
    277         asm volatile("mrc p15, 0, %[dacr], c3, c0, 0 @ Read DACR\n\t"
     277        __asm__ volatile("mrc p15, 0, %[dacr], c3, c0, 0 @ Read DACR\n\t"
    278278                        : [dacr] "=r" (dacr));
    279279
     
    285285static inline void write_dacr(uint32_t dacr)
    286286{
    287         asm volatile("mcr p15, 0, %[dacr], c3, c0, 0 @ Write DACR\n\t"
     287        __asm__ volatile("mcr p15, 0, %[dacr], c3, c0, 0 @ Write DACR\n\t"
    288288                        : : [dacr] "r" (dacr));
    289289
     
    296296
    297297    /* Invalidate entire unified TLB */
    298     asm volatile("mcr p15, 0, %[zero], c8, c7, 0 @ TLBIALL\n\t"
     298    __asm__ volatile("mcr p15, 0, %[zero], c8, c7, 0 @ TLBIALL\n\t"
    299299        : : [zero] "r" (0));
    300300
    301301    /* Invalidate all instruction caches to PoU.
    302302     * Also flushes branch target cache. */
    303     asm volatile("mcr p15, 0, %[zero], c7, c5, 0"
     303    __asm__ volatile("mcr p15, 0, %[zero], c7, c5, 0"
    304304        : : [zero] "r" (0));
    305305
    306306    /* Invalidate entire branch predictor array */
    307     asm volatile("mcr p15, 0, %[zero], c7, c5, 6"
     307    __asm__ volatile("mcr p15, 0, %[zero], c7, c5, 6"
    308308        : : [zero] "r" (0)); /* flush BTB */
    309309
     
    317317    uint32_t bar;
    318318
    319     asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
     319    __asm__ volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
    320320        : [bar] "=r" (bar));
    321321
     
    329329    uint32_t bar;
    330330
    331     asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
     331    __asm__ volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
    332332        : [bar] "=r" (bar));
    333333
     
    345345       flags here and remove them in the read_ttbr0 */
    346346    uint32_t v  =  (bar  & ARM_TTBR_ADDR_MASK ) | ARM_TTBR_FLAGS_CACHED;
    347     asm volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t"
     347    __asm__ volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t"
    348348        : : [bar] "r" (v));
    349349
  • bsps/powerpc/include/bsp/tictac.h

    re1fdf97 r5810a08  
    3939{
    4040        uint32_t tmp;
    41         asm volatile (
     41        __asm__ volatile (
    4242                "mftb 0;"
    4343                "stw 0, ppc_tic_tac@sdarel(13);"
     
    5353        uint32_t ticks;
    5454        uint32_t tmp;
    55         asm volatile (
     55        __asm__ volatile (
    5656                "mftb %0;"
    5757                "lwz %1, ppc_tic_tac@sdarel(13);"
     
    6868{
    6969        uint32_t tmp;
    70         asm volatile (
     70        __asm__ volatile (
    7171                "mftb 0;"
    7272                "stw 0, ppc_boom_bam@sdarel(13);"
     
    8282        uint32_t ticks;
    8383        uint32_t tmp;
    84         asm volatile (
     84        __asm__ volatile (
    8585                "mftb %0;"
    8686                "lwz %1, ppc_boom_bam@sdarel(13);"
  • bsps/powerpc/include/libcpu/spr.h

    re1fdf97 r5810a08  
    5252{
    5353        unsigned long val;
    54         asm volatile("mfmsr %0" : "=r" (val));
     54        __asm__ volatile("mfmsr %0" : "=r" (val));
    5555        return val;
    5656}
     
    5858static inline void _write_MSR(unsigned long val)
    5959{
    60         asm volatile("mtmsr %0" : : "r" (val));
     60        __asm__ volatile("mtmsr %0" : : "r" (val));
    6161        return;
    6262}
     
    6565{
    6666        unsigned long val;
    67         asm volatile (
     67        __asm__ volatile (
    6868                ".machine \"push\"\n"
    6969                ".machine \"any\"\n"
     
    7878static inline void _write_SR(unsigned long val, void * va)
    7979{
    80         asm volatile (
     80        __asm__ volatile (
    8181                ".machine \"push\"\n"
    8282                ".machine \"any\"\n"
  • cpukit/score/cpu/or1k/include/rtems/score/or1k-utility.h

    re1fdf97 r5810a08  
    346346   uint32_t spr_value;
    347347
    348    asm volatile (
     348   __asm__ volatile (
    349349     "l.mfspr  %0, %1, 0;\n\t"
    350350     : "=r" (spr_value) : "r" (reg));
     
    355355static inline void _OR1K_mtspr(uint32_t reg, uint32_t value)
    356356{
    357    asm volatile (
     357   __asm__ volatile (
    358358     "l.mtspr  %1, %0, 0;\n\t"
    359359     :: "r" (value), "r" (reg)
     
    387387static inline void _OR1K_Sync_mem( void )
    388388{
    389   asm volatile("l.msync");
     389  __asm__ volatile("l.msync");
    390390}
    391391
    392392static inline void _OR1K_Sync_pipeline( void )
    393393{
    394   asm volatile("l.psync");
     394  __asm__ volatile("l.psync");
    395395}
    396396
     
    403403 */
    404404#define _OR1KSIM_CPU_Halt() \
    405         asm volatile ("l.nop 0xc")
     405        __asm__ volatile ("l.nop 0xc")
    406406
    407407#ifdef __cplusplus
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