Changeset 5810a08 in rtems

Timestamp:

07/27/22 13:20:32 (7 months ago)

Author:

Sebastian Huber <sebastian.huber@…>

Branches:

master

Children:

b868d0a

Parents:

e1fdf97

git-author:

Sebastian Huber <sebastian.huber@…> (07/27/22 13:20:32)

git-committer:

Sebastian Huber <sebastian.huber@…> (07/27/22 15:01:14)

Message:

Use asm for standard C compatibility

Files:

• bsps/arm/beagle/include/bsp.h (modified) (14 diffs)
• bsps/powerpc/include/bsp/tictac.h (modified) (4 diffs)
• bsps/powerpc/include/libcpu/spr.h (modified) (4 diffs)
• cpukit/score/cpu/or1k/include/rtems/score/or1k-utility.h (modified) (4 diffs)

bsps/arm/beagle/include/bsp.h

@@ -117 +117 @@
 static inline void dsb(void)
 {
-    asm volatile("dsb" : : : "memory");
+    __asm__ volatile("dsb" : : : "memory");
 }
 
@@ -123 +123 @@
 static inline void isb(void)
 {
-    asm volatile("isb" : : : "memory");
+    __asm__ volatile("isb" : : : "memory");
 }
 
@@ -129 +129 @@
 static inline void flush_data_cache(void)
 {
-    asm volatile(
+    __asm__ volatile(
         "mov r0, #0\n"
         "mcr p15, #0, r0, c7, c10, #4\n"
@@ -230 +230 @@
     uint32_t ctl;
 
-    asm volatile("mrc p15, 0, %[ctl], c1, c0, 0 @ Read SCTLR\n\t"
+    __asm__ volatile("mrc p15, 0, %[ctl], c1, c0, 0 @ Read SCTLR\n\t"
         : [ctl] "=r" (ctl));
     return ctl;
@@ -238 +238 @@
 static inline void write_sctlr(uint32_t ctl)
 {
-    asm volatile("mcr p15, 0, %[ctl], c1, c0, 0 @ Write SCTLR\n\t"
+    __asm__ volatile("mcr p15, 0, %[ctl], c1, c0, 0 @ Write SCTLR\n\t"
         : : [ctl] "r" (ctl));
     isb();
@@ -248 +248 @@
     uint32_t ctl;
 
-    asm volatile("mrc p15, 0, %[ctl], c1, c0, 1 @ Read ACTLR\n\t"
+    __asm__ volatile("mrc p15, 0, %[ctl], c1, c0, 1 @ Read ACTLR\n\t"
             : [ctl] "=r" (ctl));
     return ctl;
@@ -256 +256 @@
 static inline void write_actlr(uint32_t ctl)
 {
-    asm volatile("mcr p15, 0, %[ctl], c1, c0, 1 @ Write ACTLR\n\t"
+    __asm__ volatile("mcr p15, 0, %[ctl], c1, c0, 1 @ Write ACTLR\n\t"
         : : [ctl] "r" (ctl));
     isb();
@@ -264 +264 @@
 static inline void write_ttbcr(uint32_t bcr)
 {
-        asm volatile("mcr p15, 0, %[bcr], c2, c0, 2 @ Write TTBCR\n\t"
+        __asm__ volatile("mcr p15, 0, %[bcr], c2, c0, 2 @ Write TTBCR\n\t"
                         : : [bcr] "r" (bcr));
 
@@ -275 +275 @@
         uint32_t dacr;
 
-        asm volatile("mrc p15, 0, %[dacr], c3, c0, 0 @ Read DACR\n\t"
+        __asm__ volatile("mrc p15, 0, %[dacr], c3, c0, 0 @ Read DACR\n\t"
                         : [dacr] "=r" (dacr));
 
@@ -285 +285 @@
 static inline void write_dacr(uint32_t dacr)
 {
-        asm volatile("mcr p15, 0, %[dacr], c3, c0, 0 @ Write DACR\n\t"
+        __asm__ volatile("mcr p15, 0, %[dacr], c3, c0, 0 @ Write DACR\n\t"
                         : : [dacr] "r" (dacr));
 
@@ -296 +296 @@
 
     /* Invalidate entire unified TLB */
-    asm volatile("mcr p15, 0, %[zero], c8, c7, 0 @ TLBIALL\n\t"
+    __asm__ volatile("mcr p15, 0, %[zero], c8, c7, 0 @ TLBIALL\n\t"
         : : [zero] "r" (0));
 
     /* Invalidate all instruction caches to PoU.
      * Also flushes branch target cache. */
-    asm volatile("mcr p15, 0, %[zero], c7, c5, 0"
+    __asm__ volatile("mcr p15, 0, %[zero], c7, c5, 0"
         : : [zero] "r" (0));
 
     /* Invalidate entire branch predictor array */
-    asm volatile("mcr p15, 0, %[zero], c7, c5, 6"
+    __asm__ volatile("mcr p15, 0, %[zero], c7, c5, 6"
         : : [zero] "r" (0)); /* flush BTB */
 
@@ -317 +317 @@
     uint32_t bar;
 
-    asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
+    __asm__ volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
         : [bar] "=r" (bar));
 
@@ -329 +329 @@
     uint32_t bar;
 
-    asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
+    __asm__ volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
         : [bar] "=r" (bar));
 
@@ -345 +345 @@
        flags here and remove them in the read_ttbr0 */
     uint32_t v  =  (bar  & ARM_TTBR_ADDR_MASK ) | ARM_TTBR_FLAGS_CACHED;
-    asm volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t"
+    __asm__ volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t"
         : : [bar] "r" (v));
 

bsps/powerpc/include/bsp/tictac.h

@@ -39 +39 @@
 {
         uint32_t tmp;
-        asm volatile (
+        __asm__ volatile (
                 "mftb 0;"
                 "stw 0, ppc_tic_tac@sdarel(13);"
@@ -53 +53 @@
         uint32_t ticks;
         uint32_t tmp;
-        asm volatile (
+        __asm__ volatile (
                 "mftb %0;"
                 "lwz %1, ppc_tic_tac@sdarel(13);"
@@ -68 +68 @@
 {
         uint32_t tmp;
-        asm volatile (
+        __asm__ volatile (
                 "mftb 0;"
                 "stw 0, ppc_boom_bam@sdarel(13);"
@@ -82 +82 @@
         uint32_t ticks;
         uint32_t tmp;
-        asm volatile (
+        __asm__ volatile (
                 "mftb %0;"
                 "lwz %1, ppc_boom_bam@sdarel(13);"

bsps/powerpc/include/libcpu/spr.h

@@ -52 +52 @@
 {
         unsigned long val;
-        asm volatile("mfmsr %0" : "=r" (val));
+        __asm__ volatile("mfmsr %0" : "=r" (val));
         return val;
 }
@@ -58 +58 @@
 static inline void _write_MSR(unsigned long val)
 {
-        asm volatile("mtmsr %0" : : "r" (val));
+        __asm__ volatile("mtmsr %0" : : "r" (val));
         return;
 }
@@ -65 +65 @@
 {
         unsigned long val;
-        asm volatile (
+        __asm__ volatile (
                 ".machine \"push\"\n"
                 ".machine \"any\"\n"
@@ -78 +78 @@
 static inline void _write_SR(unsigned long val, void * va)
 {
-        asm volatile (
+        __asm__ volatile (
                 ".machine \"push\"\n"
                 ".machine \"any\"\n"

cpukit/score/cpu/or1k/include/rtems/score/or1k-utility.h

@@ -346 +346 @@
    uint32_t spr_value;
 
-   asm volatile (
+   __asm__ volatile (
      "l.mfspr  %0, %1, 0;\n\t"
      : "=r" (spr_value) : "r" (reg));
@@ -355 +355 @@
 static inline void _OR1K_mtspr(uint32_t reg, uint32_t value)
 {
-   asm volatile (
+   __asm__ volatile (
      "l.mtspr  %1, %0, 0;\n\t"
      :: "r" (value), "r" (reg)
@@ -387 +387 @@
 static inline void _OR1K_Sync_mem( void )
 {
-  asm volatile("l.msync");
+  __asm__ volatile("l.msync");
 }
 
 static inline void _OR1K_Sync_pipeline( void )
 {
-  asm volatile("l.psync");
+  __asm__ volatile("l.psync");
 }
 
@@ -403 +403 @@
  */
 #define _OR1KSIM_CPU_Halt() \
-        asm volatile ("l.nop 0xc")
+        __asm__ volatile ("l.nop 0xc")
 
 #ifdef __cplusplus