Index: c/src/lib/libbsp/powerpc/ChangeLog
===================================================================
--- c/src/lib/libbsp/powerpc/ChangeLog	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ c/src/lib/libbsp/powerpc/ChangeLog	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -1,2 +1,6 @@
+2008-07-14	Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+	* mpc55xxevb: New BSP.
+
 2008-07-14	Thomas Doefler <Thomas.Doerfler@embedded-brains.de>
 	* haleakala: added new BSP
Index: c/src/lib/libbsp/powerpc/acinclude.m4
===================================================================
--- c/src/lib/libbsp/powerpc/acinclude.m4	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ c/src/lib/libbsp/powerpc/acinclude.m4	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -15,4 +15,6 @@
   motorola_powerpc )
     AC_CONFIG_SUBDIRS([motorola_powerpc]);;
+  mpc55xxevb )
+    AC_CONFIG_SUBDIRS([mpc55xxevb]);;
   mpc8260ads )
     AC_CONFIG_SUBDIRS([mpc8260ads]);;
Index: c/src/lib/libbsp/powerpc/gen83xx/ChangeLog
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/ChangeLog	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ c/src/lib/libbsp/powerpc/gen83xx/ChangeLog	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -1,2 +1,16 @@
+2008-07-14	Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+	* irq/irq_init.c, irq/irq.h, startup/linkcmds:
+	Removed.
+
+	* README.mpc8313erdb, include/irq-config.h, include/irq.h, irq/irq.c,
+	startup/linkcmds.base, startup/linkcmds.mpc8313erdb: New files.
+
+	* Makefile.am, configure.ac, console/config.c, console/console.c,
+	i2c/i2c_init.c, include/bsp.h, include/hwreg_vals.h, network/network.c,
+	spi/spi_init.c, start/start.S, startup/bspstart.c, startup/cpuinit.c,
+	startup/linkcmds.hsc_cm01, startup/linkcmds.mpc8349eamds: Support
+	MPC8313ERDB.
+
 2008-05-15	Joel Sherrill <joel.sherrill@OARcorp.com>
 
Index: c/src/lib/libbsp/powerpc/gen83xx/Makefile.am
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/Makefile.am	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ c/src/lib/libbsp/powerpc/gen83xx/Makefile.am	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -12,4 +12,6 @@
 include_HEADERS = include/bsp.h 
 include_HEADERS += include/tm27.h
+
+libcpudir = ../../../libcpu/@RTEMS_CPU@
 
 nodist_include_HEADERS = include/bspopts.h
@@ -34,24 +36,37 @@
 project_lib_DATA += rtems_crti.$(OBJEXT)
 
-dist_project_lib_DATA += startup/linkcmds \
+dist_project_lib_DATA += startup/linkcmds.base \
+                         startup/linkcmds.mpc8313erdb \
                          startup/linkcmds.mpc8349eamds \
                          startup/linkcmds.hsc_cm01
 
 mpc83xx_regs_SOURCES = startup/mpc83xx_regs.c
-startup_SOURCES = ../../shared/bspclean.c ../../shared/bsplibc.c \
-    ../../shared/bsppost.c startup/bspstart.c ../../shared/bootcard.c \
-    ../../shared/bsppredriverhook.c \
-    ../../shared/sbrk.c ../../shared/gnatinstallhandler.c startup/cpuinit.c
-pclock_SOURCES = ../../powerpc/shared/clock/p_clock.c
 
-include_bsp_HEADERS = ./irq/irq.h \
-    ./include/hwreg_vals.h        \
-    ../../powerpc/shared/vectors/vectors.h
+startup_SOURCES = ../../shared/bspclean.c \
+	../../shared/bsplibc.c \
+	../../shared/bsppost.c \
+	../../shared/bootcard.c \
+	../../shared/bsppredriverhook.c \
+	../../shared/sbrk.c \
+	../../shared/gnatinstallhandler.c \
+	../shared/src/tictac.c \
+	startup/cpuinit.c \
+	startup/bspstart.c
 
-vectors_SOURCES = ../../powerpc/shared/vectors/vectors.h \
-    ../../powerpc/shared/vectors/vectors_init.c \
-    ../../powerpc/shared/vectors/vectors.S
-irq_SOURCES = ./irq/irq.h ./irq/irq_init.c ./irq/ipic.c \
-	../shared/irq/irq_asm.S
+clock_SOURCES = ../shared/clock/clock.c
+
+include_bsp_HEADERS = include/irq.h \
+	include/irq-config.h \
+	../../shared/include/irq-generic.h \
+	include/hwreg_vals.h \
+	../shared/include/u-boot.h \
+	../shared/include/tictac.h
+
+irq_SOURCES = include/irq.h \
+	include/irq-config.h \
+	irq/irq.c \
+	../../shared/src/irq-generic.c \
+	../../shared/src/irq-legacy.c
+
 console_SOURCES = console/console.c console/ns16550cfg.c 
 bsp_i2c_SOURCES   = i2c/i2c_init.c 
@@ -67,22 +82,22 @@
 
 noinst_LIBRARIES = libbsp.a
-libbsp_a_SOURCES = $(startup_SOURCES) $(pclock_SOURCES) $(console_SOURCES) \
-    $(vectors_SOURCES) $(irq_SOURCES) $(mpc83xx_regs_SOURCES) \
+libbsp_a_SOURCES = $(startup_SOURCES) $(clock_SOURCES) $(console_SOURCES) \
+    $(irq_SOURCES) $(mpc83xx_regs_SOURCES) \
     $(bsp_i2c_SOURCES) $(bsp_spi_SOURCES)
 
-libbsp_a_LIBADD = \
-    ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
-    ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
-    ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
-    ../../../libcpu/@RTEMS_CPU@/mpc6xx/mmu.rel   \
-    ../../../libcpu/@RTEMS_CPU@/mpc6xx/timer.rel \
-    ../../../libcpu/@RTEMS_CPU@/mpc6xx/clock.rel \
-    ../../../libcpu/@RTEMS_CPU@/mpc83xx/i2c.rel  \
-    ../../../libcpu/@RTEMS_CPU@/mpc83xx/spi.rel
+libbsp_a_LIBADD = $(libcpudir)/shared/cpuIdent.rel \
+	$(libcpudir)/shared/cache.rel \
+	$(libcpudir)/@exceptions@/rtems-cpu.rel \
+	$(libcpudir)/@exceptions@/raw_exception.rel \
+	$(libcpudir)/@exceptions@/exc_bspsupport.rel \
+	$(libcpudir)/mpc6xx/mmu.rel   \
+	$(libcpudir)/mpc6xx/timer.rel \
+	$(libcpudir)/mpc83xx/i2c.rel  \
+	$(libcpudir)/mpc83xx/spi.rel \
+	$(libcpudir)/mpc83xx/gtm.rel
 
 if HAS_NETWORKING
 libbsp_a_LIBADD += network.rel
-libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/mpc83xx/tsec.rel
+libbsp_a_LIBADD += $(libcpudir)/mpc83xx/tsec.rel
 endif
 
Index: c/src/lib/libbsp/powerpc/gen83xx/README.mpc8313erdb
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/README.mpc8313erdb	(revision 574fb675105b77dfe9598915207f1f32790f905f)
+++ c/src/lib/libbsp/powerpc/gen83xx/README.mpc8313erdb	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -0,0 +1,13 @@
+SPI:
+
+In master mode SCS (SPI_D) cannot be used as GPIO[31].  Unfortunately this pin
+is connected to the SD Card slot. See also [1] SPI 5.
+
+TSEC:
+
+The interrupt vector values are switched at the IPIC.  See also [1] IPIC 1.
+
+REFERENCES:
+
+[1]	MPC8313ECE Rev. 3, 3/2008: "MPC8313E PowerQUICCâ¢ II Pro Integrated Host
+	Processor Device Errata"
Index: c/src/lib/libbsp/powerpc/gen83xx/configure.ac
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/configure.ac	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ c/src/lib/libbsp/powerpc/gen83xx/configure.ac	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -11,4 +11,5 @@
 AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.10])
 RTEMS_BSP_CONFIGURE
+RTEMS_AMPOLISH3
 
 RTEMS_PROG_CC_FOR_TARGET([-ansi -fasm])
Index: c/src/lib/libbsp/powerpc/gen83xx/console/config.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/console/config.c	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ c/src/lib/libbsp/powerpc/gen83xx/console/config.c	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -98,5 +98,13 @@
 		16,				/* ulMargin */
 		8,				/* ulHysteresis */
-		(void *)9600,	/* baud rate */	/* pDeviceParams */
+
+		/* pDeviceParams */
+		/* baud rate */
+#ifdef MPC8313ERDB
+		(void *)115200,
+#else /* MPC8313ERDB */
+		(void *)9600,
+#endif /* MPC8313ERDB */
+
                 (uint32_t)&(mpc83xx.duart[0]),  /* ulCtrlPort1e */
 		0,				/* ulCtrlPort2 */
@@ -118,5 +126,13 @@
                 16,                             /* ulMargin */
                 8,                              /* ulHysteresis */
-                (void *)9600,   /* baud rate */ /* pDeviceParams */
+
+		/* pDeviceParams */
+		/* baud rate */
+#ifdef MPC8313ERDB
+		(void *)115200,
+#else /* MPC8313ERDB */
+		(void *)9600,
+#endif /* MPC8313ERDB */
+
                 (uint32_t)&(mpc83xx.duart[1]),  /* ulCtrlPort1-Filled in at runtime */
                 0,                              /* ulCtrlPort2 */
Index: c/src/lib/libbsp/powerpc/gen83xx/console/console.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/console/console.c	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ c/src/lib/libbsp/powerpc/gen83xx/console/console.c	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -45,4 +45,5 @@
 #include "console.h"
 #include <rtems/bspIo.h>
+#include <rtems/termiostypes.h>
 
 /*
@@ -99,4 +100,7 @@
 	status = rtems_termios_open ( major, minor, arg, &Callbacks);
 	Console_Port_Data[minor].termios_data = args->iop->data1;
+	if (status == 0) {
+		rtems_termios_set_initial_baud( Console_Port_Data [minor].termios_data, (int) Console_Port_Tbl [minor].pDeviceParams);
+	}
 
 	return status;
@@ -257,4 +261,9 @@
     Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
       deviceWritePolled(Console_Port_Minor,c);
+
+    if (c == '\n') {
+      Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
+        deviceWritePolled(Console_Port_Minor,'\r');
+    }
     
     rtems_interrupt_enable(Irql);
Index: c/src/lib/libbsp/powerpc/gen83xx/i2c/i2c_init.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/i2c/i2c_init.c	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ c/src/lib/libbsp/powerpc/gen83xx/i2c/i2c_init.c	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -26,12 +26,12 @@
   {
     {/* public fields */
-      ops:	&mpc83xx_i2c_ops,
-      size:	sizeof(mpc83xx_i2c_bus_tbl[0]),
+      .ops = &mpc83xx_i2c_ops,
+      .size = sizeof(mpc83xx_i2c_bus_tbl[0]),
     },
     { /* our private fields */
-      reg_ptr:	 &mpc83xx.i2c[0],
-      initialized: FALSE,
-      irq_number :  BSP_IPIC_IRQ_I2C1,
-      base_frq   : 0 /* will be set during initiailization */
+      .reg_ptr = &mpc83xx.i2c[0],
+      .initialized = FALSE,
+      .irq_number = BSP_IPIC_IRQ_I2C1,
+      .base_frq = 0 /* will be set during initiailization */
     }
   },
@@ -39,12 +39,12 @@
   {
     { /* public fields */
-      ops:	&mpc83xx_i2c_ops,
-      size:	sizeof(mpc83xx_i2c_bus_tbl[1]),
+      .ops = &mpc83xx_i2c_ops,
+      .size = sizeof(mpc83xx_i2c_bus_tbl[1]),
     },
     { /* our private fields */
-      reg_ptr:	 &mpc83xx.i2c[1],
-      initialized: FALSE,
-      irq_number :  BSP_IPIC_IRQ_I2C2,
-      base_frq   : 0 /* will be set during initiailization */
+      .reg_ptr = &mpc83xx.i2c[1],
+      .initialized = FALSE,
+      .irq_number = BSP_IPIC_IRQ_I2C2,
+      .base_frq = 0 /* will be set during initiailization */
     }
   } 
@@ -115,4 +115,6 @@
   i2c2_busno = ret_code;
 
+#ifdef RTEMS_BSP_I2C_EEPROM_DEVICE_NAME
+
   /*
    * register EEPROM to bus 1, Address 0x50
@@ -121,7 +123,10 @@
 				       i2c_2b_eeprom_driver_descriptor,
 				       i2c1_busno,0x50);
+
   if (ret_code < 0) {
     return -ret_code;
   }
+
+#endif /* RTEMS_BSP_I2C_EEPROM_DEVICE_NAME */
 
   /*
Index: c/src/lib/libbsp/powerpc/gen83xx/include/bsp.h
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/include/bsp.h	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ c/src/lib/libbsp/powerpc/gen83xx/include/bsp.h	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -21,5 +21,54 @@
 #define __GEN83xx_BSP_h
 
+/*
+ * MPC8313E Reference Design Board
+ */
+
+#ifdef MPC8313ERDB
+
+#define HAS_UBOOT
+
+/* For U-Boot */
+#define CONFIG_MPC83XX
+#define CONFIG_HAS_ETH1
+
+#endif /* MPC8313ERDB */
+
+#include <libcpu/powerpc-utility.h> 
+
 #include <bsp/hwreg_vals.h>
+
+/*
+ * Some symbols defined in the linker command file.
+ */
+
+LINKER_SYMBOL( bsp_ram_start);
+LINKER_SYMBOL( bsp_ram_end);
+LINKER_SYMBOL( bsp_ram_size);
+
+LINKER_SYMBOL( bsp_rom_start);
+LINKER_SYMBOL( bsp_rom_end);
+LINKER_SYMBOL( bsp_rom_size);
+
+LINKER_SYMBOL( bsp_section_text_start);
+LINKER_SYMBOL( bsp_section_text_end);
+LINKER_SYMBOL( bsp_section_text_size);
+
+LINKER_SYMBOL( bsp_section_data_start);
+LINKER_SYMBOL( bsp_section_data_end);
+LINKER_SYMBOL( bsp_section_data_size);
+
+LINKER_SYMBOL( bsp_section_bss_start);
+LINKER_SYMBOL( bsp_section_bss_end);
+LINKER_SYMBOL( bsp_section_bss_size);
+
+LINKER_SYMBOL( bsp_interrupt_stack_start);
+LINKER_SYMBOL( bsp_interrupt_stack_end);
+LINKER_SYMBOL( bsp_interrupt_stack_size);
+LINKER_SYMBOL( bsp_interrupt_stack_pointer);
+
+LINKER_SYMBOL( bsp_workspace_start);
+
+LINKER_SYMBOL( IMMRBAR);
 
 #ifndef ASM
@@ -36,4 +85,15 @@
 #include <bsp/irq.h>
 #include <bsp/vectors.h>
+#include <bsp/tictac.h>
+
+#ifdef HAS_UBOOT
+
+#include <bsp/u-boot.h>
+
+extern bd_t mpc83xx_uboot_board_info;
+
+extern const size_t mpc83xx_uboot_board_info_size;
+
+#endif /* HAS_UBOOT */
 
 /* miscellaneous stuff assumed to exist */
@@ -98,28 +158,21 @@
 
 /*
- *  Convert decrement value to tenths of microsecnds (used by
- *  shared timer driver).
- *
- *    + CPU has a csb_clock bus,
- *    + There are 4 bus cycles per click
- *    + We return value in 1/10 microsecond units.
- *   Modified following equation to integer equation to remove
- *   floating point math.
- *   (int) ((float)(_value) / ((XLB_CLOCK/1000000 * 0.1) / 4.0))
- */
-
-extern unsigned int BSP_bus_frequency;
-#define BSP_Convert_decrementer( _value ) \
-  (int) (((_value) * 4000) / (BSP_bus_frequency/10000))
-
-/*
  * Network driver configuration
  */
 struct rtems_bsdnet_ifconfig;
 extern int BSP_tsec_attach(struct rtems_bsdnet_ifconfig *config,int attaching);
+#define RTEMS_BSP_NETWORK_DRIVER_ATTACH	BSP_tsec_attach
+
+#ifdef MPC8313ERDB
+
+#define RTEMS_BSP_NETWORK_DRIVER_NAME	"tsec2"
+#define RTEMS_BSP_NETWORK_DRIVER_NAME2	"tsec1"
+
+#else /* MPC8313ERDB */
+
 #define RTEMS_BSP_NETWORK_DRIVER_NAME	"tsec1"
-#define RTEMS_BSP_NETWORK_DRIVER_ATTACH	BSP_tsec_attach
-
 #define RTEMS_BSP_NETWORK_DRIVER_NAME2	"tsec2"
+
+#endif /* MPC8313ERDB */
 
 #if defined(MPC8349EAMDS)
@@ -151,4 +204,17 @@
 #endif /* defined(HSC_CM01) */
 
+extern unsigned int BSP_bus_frequency;
+
+extern uint32_t bsp_clicks_per_usec;
+
+/*
+ *  Convert decrementer value to tenths of microseconds (used by shared timer
+ *  driver).
+ */
+#define BSP_Convert_decrementer( _value ) \
+  ((int) (((_value) * 10) / bsp_clicks_per_usec))
+
+void mpc83xx_zero_4( void *dest, size_t n);
+
 #ifdef __cplusplus
 }
Index: c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -22,4 +22,5 @@
 
 #include <mpc83xx/mpc83xx.h>
+
 /*
  * distinguish board characteristics
@@ -104,6 +105,13 @@
 			  RCWHR_LALE_NORM    |	\
 			  RCWHR_LDP_PAR)
+
+#elif defined( HAS_UBOOT)
+
+/* TODO */
+
 #else
+
 #error "board type not defined"
+
 #endif
 
@@ -112,26 +120,9 @@
  * for Freescale MPC8349EAMDS
  */
-/*
- * address range definitions
- */
-/* ROM definitions (8 MB, mirrored multiple times) */
-#define	ROM_START	0xFE000000
-#define ROM_SIZE        0x02000000
-#define	ROM_END		(ROM_START+ROM_SIZE-1)
-#define	BOOT_START      ROM_START
-#define	BOOT_END        ROM_END
-
-/* SDRAM definitions (256 MB) */
-#define	RAM_START       0x00000000
-#define RAM_SIZE        0x10000000
-#define	RAM_END		(RAM_START+RAM_SIZE-1)
-
-
-/* working internal memory map base address */
-#define	IMMRBAR         0xE0000000
 
 /*
  * working values for various registers, used in start/start.S
  */
+
 /*
  * Local Access Windows
@@ -184,26 +175,9 @@
  * for JPK HSC_CM01
  */
-/*
- * address range definitions
- */
-/* ROM definitions (8 MB, mirrored multiple times) */
-#define	ROM_START	0xFE000000
-#define ROM_SIZE        0x02000000
-#define	ROM_END		(ROM_START+ROM_SIZE-1)
-#define	BOOT_START      ROM_START
-#define	BOOT_END        ROM_END
-
-/* SDRAM definitions (256 MB) */
-#define	RAM_START       0x00000000
-#define RAM_SIZE        0x10000000
-#define	RAM_END		(RAM_START+RAM_SIZE-1)
-
-
-/* working internal memory map base address */
-#define	IMMRBAR         0xE0000000
 
 /*
  * working values for various registers, used in start/start.S
  */
+
 /*
  * Local Access Windows
@@ -211,9 +185,9 @@
  */
 
-#define LBLAWBAR0_VAL  ROM_START
+#define LBLAWBAR0_VAL  bsp_rom_start
 #define LBLAWAR0_VAL   0x80000018
 #define LBLAWBAR1_VAL  0xF8000000
 #define LBLAWAR1_VAL   0x80000015
-#define DDRLAWBAR0_VAL RAM_START
+#define DDRLAWBAR0_VAL bsp_ram_start
 #define DDRLAWAR0_VAL  0x8000001B
 /*
@@ -251,8 +225,14 @@
 #define DDR_SDRAM_INIT_ADDR_VAL      0
 #define DDR_SDRAM_INTERVAL_VAL       0x05080000
+
+#elif defined( HAS_UBOOT)
+
+/* TODO */
+
 #else
+
 #error "board type not defined"
+
 #endif
-
 
 /**************************
Index: c/src/lib/libbsp/powerpc/gen83xx/include/irq-config.h
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/include/irq-config.h	(revision 574fb675105b77dfe9598915207f1f32790f905f)
+++ c/src/lib/libbsp/powerpc/gen83xx/include/irq-config.h	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -0,0 +1,78 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief BSP interrupt support configuration.
+ */
+
+/*
+ * Copyright (c) 2008
+ * Embedded Brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * rtems@embedded-brains.de
+ *
+ * The license and distribution terms for this file may be found in the file
+ * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_POWERPC_GEN83XX_IRQ_CONFIG_H
+#define LIBBSP_POWERPC_GEN83XX_IRQ_CONFIG_H
+
+#include <stdint.h>
+
+#include <bsp/irq.h>
+
+/**
+ * @addtogroup bsp_interrupt
+ *
+ * @{
+ */
+
+/**
+ * @brief Minimum vector number.
+ */
+#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET
+
+/**
+ * @brief Maximum vector number.
+ */
+#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET
+
+/**
+ * @brief Enables the index table.
+ *
+ * If you enable the index table, you have to define a size for the handler
+ * table (@ref BSP_INTERRUPT_HANDLER_TABLE_SIZE) and must provide an integer
+ * type capable to index the complete handler table (@ref
+ * bsp_interrupt_handler_index_type).
+ */
+#undef BSP_INTERRUPT_USE_INDEX_TABLE
+
+/**
+ * @brief Disables usage of the heap.
+ *
+ * If you define this, you have to define @ref BSP_INTERRUPT_USE_INDEX_TABLE as
+ * well.
+ */
+#undef BSP_INTERRUPT_NO_HEAP_USAGE
+
+#ifdef BSP_INTERRUPT_USE_INDEX_TABLE
+
+/**
+ * @brief Size of the handler table.
+ */
+#define BSP_INTERRUPT_HANDLER_TABLE_SIZE 63
+
+/**
+ * @brief Integer type capable to index the complete handler table.
+ */
+typedef uint8_t bsp_interrupt_handler_index_type;
+
+#endif /* BSP_INTERRUPT_USE_INDEX_TABLE */
+
+/** @} */
+
+#endif /* LIBBSP_POWERPC_GEN83XX_IRQ_CONFIG_H */
Index: c/src/lib/libbsp/powerpc/gen83xx/include/irq.h
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/include/irq.h	(revision 574fb675105b77dfe9598915207f1f32790f905f)
+++ c/src/lib/libbsp/powerpc/gen83xx/include/irq.h	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -0,0 +1,147 @@
+/*===============================================================*\
+| Project: RTEMS generic MPC83xx BSP                              |
++-----------------------------------------------------------------+
+|                    Copyright (c) 2007                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.com/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+| this file declares constants of the interrupt controller        |
+\*===============================================================*/
+#ifndef GEN83xx_IRQ_IRQ_H
+#define GEN83xx_IRQ_IRQ_H
+
+#include <stdbool.h>
+
+#include <rtems.h>
+#include <rtems/irq.h>
+#include <rtems/irq-extension.h>
+
+/*
+ * the following definitions specify the indices used 
+ * to interface the interrupt handler API
+ */
+
+/*
+ * Peripheral IRQ handlers related definitions
+ */
+#define BSP_IPIC_PER_IRQ_NUMBER	        128
+#define BSP_IPIC_IRQ_LOWEST_OFFSET        0
+#define BSP_IPIC_IRQ_MAX_OFFSET      (BSP_IPIC_IRQ_LOWEST_OFFSET\
+                                         +BSP_IPIC_PER_IRQ_NUMBER-1)
+
+#define BSP_IS_IPIC_IRQ(irqnum)				\
+          (((irqnum) >= BSP_IPIC_IRQ_LOWEST_OFFSET) &&	\
+	   ((irqnum) <= BSP_IPIC_IRQ_MAX_OFFSET))
+/*
+ * Processor IRQ handlers related definitions
+ */
+#define BSP_PROCESSOR_IRQ_NUMBER        1
+#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET	(BSP_IPIC_IRQ_MAX_OFFSET+1)
+#define BSP_PROCESSOR_IRQ_MAX_OFFSET	(BSP_PROCESSOR_IRQ_LOWEST_OFFSET\
+                                         +BSP_PROCESSOR_IRQ_NUMBER-1)
+
+#define BSP_IS_PROCESSOR_IRQ(irqnum)				\
+          (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) &&	\
+	   ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET))
+/*
+ * Summary
+ */
+#define BSP_IRQ_NUMBER                  (BSP_PROCESSOR_IRQ_MAX_OFFSET+1)
+#define BSP_LOWEST_OFFSET		BSP_IPIC_IRQ_LOWEST_OFFSET
+#define BSP_MAX_OFFSET                  BSP_PROCESSOR_IRQ_MAX_OFFSET
+
+#define BSP_IS_VALID_IRQ(irqnum) 	\
+          (BSP_IS_PROCESSOR_IRQ(irqnum)	\
+           || BSP_IS_IPIC_IRQ(irqnum))
+
+#ifndef ASM
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * index table for the module specific handlers, a few entries are only placeholders
+ */
+  typedef enum {
+    BSP_IPIC_IRQ_FIRST	   = BSP_IPIC_IRQ_LOWEST_OFFSET,
+    BSP_IPIC_IRQ_ERROR	   = BSP_IPIC_IRQ_LOWEST_OFFSET +  0,
+    /* reserved irqs  1- 8 */
+    BSP_IPIC_IRQ_UART1	   = BSP_IPIC_IRQ_LOWEST_OFFSET +  9,
+    BSP_IPIC_IRQ_UART2 	   = BSP_IPIC_IRQ_LOWEST_OFFSET + 10,
+    BSP_IPIC_IRQ_SEC  	   = BSP_IPIC_IRQ_LOWEST_OFFSET + 11,
+    /* reserved irqs 12-13 */
+    BSP_IPIC_IRQ_I2C1      = BSP_IPIC_IRQ_LOWEST_OFFSET + 14,
+    BSP_IPIC_IRQ_I2C2      = BSP_IPIC_IRQ_LOWEST_OFFSET + 15,
+    BSP_IPIC_IRQ_SPI       = BSP_IPIC_IRQ_LOWEST_OFFSET + 16,
+    BSP_IPIC_IRQ_IRQ1      = BSP_IPIC_IRQ_LOWEST_OFFSET + 17,
+    BSP_IPIC_IRQ_IRQ2      = BSP_IPIC_IRQ_LOWEST_OFFSET + 18,
+    BSP_IPIC_IRQ_IRQ3      = BSP_IPIC_IRQ_LOWEST_OFFSET + 19,
+    BSP_IPIC_IRQ_IRQ4      = BSP_IPIC_IRQ_LOWEST_OFFSET + 20,
+    BSP_IPIC_IRQ_IRQ5      = BSP_IPIC_IRQ_LOWEST_OFFSET + 21,
+    BSP_IPIC_IRQ_IRQ6      = BSP_IPIC_IRQ_LOWEST_OFFSET + 22,
+    BSP_IPIC_IRQ_IRQ7      = BSP_IPIC_IRQ_LOWEST_OFFSET + 23,
+    /* reserved irqs 24-31 */
+    BSP_IPIC_IRQ_TSEC1_TX  = BSP_IPIC_IRQ_LOWEST_OFFSET + 32,
+    BSP_IPIC_IRQ_TSEC1_RX  = BSP_IPIC_IRQ_LOWEST_OFFSET + 33,
+    BSP_IPIC_IRQ_TSEC1_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 34,
+    BSP_IPIC_IRQ_TSEC2_TX  = BSP_IPIC_IRQ_LOWEST_OFFSET + 35,
+    BSP_IPIC_IRQ_TSEC2_RX  = BSP_IPIC_IRQ_LOWEST_OFFSET + 36,
+    BSP_IPIC_IRQ_TSEC2_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 37,
+    BSP_IPIC_IRQ_USB_DR    = BSP_IPIC_IRQ_LOWEST_OFFSET + 38,
+    BSP_IPIC_IRQ_USB_MPH   = BSP_IPIC_IRQ_LOWEST_OFFSET + 39,
+    /* reserved irqs 40-47 */
+    BSP_IPIC_IRQ_IRQ0      = BSP_IPIC_IRQ_LOWEST_OFFSET + 48,
+    /* reserved irqs 49-63 */
+    BSP_IPIC_IRQ_RTC_SEC   = BSP_IPIC_IRQ_LOWEST_OFFSET + 64,
+    BSP_IPIC_IRQ_PIT       = BSP_IPIC_IRQ_LOWEST_OFFSET + 65,
+    BSP_IPIC_IRQ_PCI1      = BSP_IPIC_IRQ_LOWEST_OFFSET + 66,
+    BSP_IPIC_IRQ_PCI2      = BSP_IPIC_IRQ_LOWEST_OFFSET + 67,
+    BSP_IPIC_IRQ_RTC_ALR   = BSP_IPIC_IRQ_LOWEST_OFFSET + 68,
+    BSP_IPIC_IRQ_MU        = BSP_IPIC_IRQ_LOWEST_OFFSET + 69,
+    BSP_IPIC_IRQ_SBA       = BSP_IPIC_IRQ_LOWEST_OFFSET + 70,
+    BSP_IPIC_IRQ_DMA       = BSP_IPIC_IRQ_LOWEST_OFFSET + 71,
+    BSP_IPIC_IRQ_GTM4      = BSP_IPIC_IRQ_LOWEST_OFFSET + 72,
+    BSP_IPIC_IRQ_GTM8      = BSP_IPIC_IRQ_LOWEST_OFFSET + 73,
+    BSP_IPIC_IRQ_GPIO1     = BSP_IPIC_IRQ_LOWEST_OFFSET + 74,
+    BSP_IPIC_IRQ_GPIO2     = BSP_IPIC_IRQ_LOWEST_OFFSET + 75,
+    BSP_IPIC_IRQ_DDR       = BSP_IPIC_IRQ_LOWEST_OFFSET + 76,
+    BSP_IPIC_IRQ_LBC       = BSP_IPIC_IRQ_LOWEST_OFFSET + 77,
+    BSP_IPIC_IRQ_GTM2      = BSP_IPIC_IRQ_LOWEST_OFFSET + 78,
+    BSP_IPIC_IRQ_GTM6      = BSP_IPIC_IRQ_LOWEST_OFFSET + 79,
+    BSP_IPIC_IRQ_PMC       = BSP_IPIC_IRQ_LOWEST_OFFSET + 80,
+    /* reserved irqs 81-83 */
+    BSP_IPIC_IRQ_GTM3      = BSP_IPIC_IRQ_LOWEST_OFFSET + 84,
+    BSP_IPIC_IRQ_GTM7      = BSP_IPIC_IRQ_LOWEST_OFFSET + 85,
+    /* reserved irqs 86-89 */
+    BSP_IPIC_IRQ_GTM1      = BSP_IPIC_IRQ_LOWEST_OFFSET + 90,
+    BSP_IPIC_IRQ_GTM5      = BSP_IPIC_IRQ_LOWEST_OFFSET + 91,
+    /* reserved irqs 92-127 */
+
+    BSP_IPIC_IRQ_LAST     = BSP_IPIC_IRQ_MAX_OFFSET,
+  } rtems_irq_symbolic_name;
+
+rtems_status_code mpc83xx_ipic_set_mask( rtems_vector_number vector, rtems_vector_number mask_vector, bool mask);
+
+#define MPC83XX_IPIC_INTERRUPT_NORMAL 0
+
+#define MPC83XX_IPIC_INTERRUPT_SYSTEM 1
+
+#define MPC83XX_IPIC_INTERRUPT_CRITICAL 2
+
+rtems_status_code mpc83xx_ipic_set_highest_priority_interrupt( rtems_vector_number vector, int type);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* ASM */
+
+#endif /* GEN83XX_IRQ_IRQ_H */
Index: c/src/lib/libbsp/powerpc/gen83xx/irq/ipic.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/irq/ipic.c	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ 	(revision )
@@ -1,408 +1,0 @@
-/*===============================================================*\
-| Project: RTEMS generic MPC83xx BSP                              |
-+-----------------------------------------------------------------+
-|                    Copyright (c) 2007                           |
-|                    Embedded Brains GmbH                         |
-|                    Obere Lagerstr. 30                           |
-|                    D-82178 Puchheim                             |
-|                    Germany                                      |
-|                    rtems@embedded-brains.de                     |
-+-----------------------------------------------------------------+
-| The license and distribution terms for this file may be         |
-| found in the file LICENSE in this distribution or at            |
-|                                                                 |
-| http://www.rtems.com/license/LICENSE.                           |
-|                                                                 |
-+-----------------------------------------------------------------+
-| this file integrates the IPIC irq controller                    |
-\*===============================================================*/
-
-#include <mpc83xx/mpc83xx.h>
-#include <rtems.h>
-#include <rtems/bspIo.h>
-#include <bsp.h>
-#include <bsp/irq.h>
-#include <rtems/powerpc/powerpc.h>
-
-typedef struct {
-  volatile uint32_t *pend_reg;
-  volatile uint32_t *mask_reg;
-  const    uint32_t  bit_num;
-} BSP_isrc_rsc_t;
-
-const BSP_isrc_rsc_t BSP_ipic_isrc_rsc[] = {
-  /* vector 0 */
-  {&mpc83xx.ipic.sersr,&mpc83xx.ipic.sermr,31},
-  {NULL,NULL,0},
-  {NULL,NULL,0},
-  {NULL,NULL,0},
-  {NULL,NULL,0},
-  {NULL,NULL,0},
-  {NULL,NULL,0},
-  {NULL,NULL,0},
-  /* vector  8 */
-  {NULL,NULL,0}, /* reserved vector  8 */
-  /* vector  9: UART1 SIxxR_H, Bit 24 */
-  {&mpc83xx.ipic.sipnr[0],&mpc83xx.ipic.simsr[0],24},
-  /* vector 10: UART2 SIxxR_H, Bit 25 */
-  {&mpc83xx.ipic.sipnr[0],&mpc83xx.ipic.simsr[0],25},
-  /* vector 11: SEC   SIxxR_H, Bit 26 */
-  {&mpc83xx.ipic.sipnr[0],&mpc83xx.ipic.simsr[0],26},
-  {NULL,NULL,0}, /* reserved vector 12 */
-  {NULL,NULL,0}, /* reserved vector 13 */
-  /* vector 14: I2C1 SIxxR_H, Bit 29 */
-  {&mpc83xx.ipic.sipnr[0],&mpc83xx.ipic.simsr[0],29},
-  /* vector 15: I2C2 SIxxR_H, Bit 30 */
-  {&mpc83xx.ipic.sipnr[0],&mpc83xx.ipic.simsr[0],30},
-  /* vector 16: SPI  SIxxR_H, Bit 31 */
-  {&mpc83xx.ipic.sipnr[0],&mpc83xx.ipic.simsr[0],31},
-  /* vector 17: IRQ1 SExxR  , Bit  1 */
-  {&mpc83xx.ipic.sepnr   ,&mpc83xx.ipic.semsr   , 1},
-  /* vector 18: IRQ2 SExxR  , Bit  2 */
-  {&mpc83xx.ipic.sepnr   ,&mpc83xx.ipic.semsr   , 2},
-  /* vector 19: IRQ3 SExxR  , Bit  3 */
-  {&mpc83xx.ipic.sepnr   ,&mpc83xx.ipic.semsr   , 3},
-  /* vector 20: IRQ4 SExxR  , Bit  4 */
-  {&mpc83xx.ipic.sepnr   ,&mpc83xx.ipic.semsr   , 4},
-  /* vector 21: IRQ5 SExxR  , Bit  5 */
-  {&mpc83xx.ipic.sepnr   ,&mpc83xx.ipic.semsr   , 5},
-  /* vector 22: IRQ6 SExxR  , Bit  6 */
-  {&mpc83xx.ipic.sepnr   ,&mpc83xx.ipic.semsr   , 6},
-  /* vector 23: IRQ7 SExxR  , Bit  7 */
-  {&mpc83xx.ipic.sepnr   ,&mpc83xx.ipic.semsr   , 7},
-  {NULL,NULL,0}, /* reserved vector 24 */
-  {NULL,NULL,0}, /* reserved vector 25 */
-  {NULL,NULL,0}, /* reserved vector 26 */
-  {NULL,NULL,0}, /* reserved vector 27 */
-  {NULL,NULL,0}, /* reserved vector 28 */
-  {NULL,NULL,0}, /* reserved vector 29 */
-  {NULL,NULL,0}, /* reserved vector 30 */
-  {NULL,NULL,0}, /* reserved vector 31 */
-  /* vector 32: TSEC1 Tx  SIxxR_H  , Bit  0 */
-  {&mpc83xx.ipic.sipnr[0],&mpc83xx.ipic.simsr[0], 0},
-  /* vector 33: TSEC1 Rx  SIxxR_H  , Bit  1 */
-  {&mpc83xx.ipic.sipnr[0],&mpc83xx.ipic.simsr[0], 1},
-  /* vector 34: TSEC1 Err SIxxR_H  , Bit  2 */
-  {&mpc83xx.ipic.sipnr[0],&mpc83xx.ipic.simsr[0], 2},
-  /* vector 35: TSEC2 Tx  SIxxR_H  , Bit  3 */
-  {&mpc83xx.ipic.sipnr[0],&mpc83xx.ipic.simsr[0], 3},
-  /* vector 36: TSEC2 Rx  SIxxR_H  , Bit  4 */
-  {&mpc83xx.ipic.sipnr[0],&mpc83xx.ipic.simsr[0], 4},
-  /* vector 37: TSEC2 Err SIxxR_H  , Bit  5 */
-  {&mpc83xx.ipic.sipnr[0],&mpc83xx.ipic.simsr[0], 5},
-  /* vector 38: USB DR    SIxxR_H  , Bit  6 */
-  {&mpc83xx.ipic.sipnr[0],&mpc83xx.ipic.simsr[0], 6},
-  /* vector 39: USB MPH   SIxxR_H  , Bit  7 */
-  {&mpc83xx.ipic.sipnr[0],&mpc83xx.ipic.simsr[0], 7},
-  {NULL,NULL,0}, /* reserved vector 40 */
-  {NULL,NULL,0}, /* reserved vector 41 */
-  {NULL,NULL,0}, /* reserved vector 42 */
-  {NULL,NULL,0}, /* reserved vector 43 */
-  {NULL,NULL,0}, /* reserved vector 44 */
-  {NULL,NULL,0}, /* reserved vector 45 */
-  {NULL,NULL,0}, /* reserved vector 46 */
-  {NULL,NULL,0}, /* reserved vector 47 */
-  /* vector 48: IRQ0 SExxR  , Bit  0 */
-  {&mpc83xx.ipic.sepnr   ,&mpc83xx.ipic.semsr   , 0},
-  {NULL,NULL,0}, /* reserved vector 49 */
-  {NULL,NULL,0}, /* reserved vector 50 */
-  {NULL,NULL,0}, /* reserved vector 51 */
-  {NULL,NULL,0}, /* reserved vector 52 */
-  {NULL,NULL,0}, /* reserved vector 53 */
-  {NULL,NULL,0}, /* reserved vector 54 */
-  {NULL,NULL,0}, /* reserved vector 55 */
-  {NULL,NULL,0}, /* reserved vector 56 */
-  {NULL,NULL,0}, /* reserved vector 57 */
-  {NULL,NULL,0}, /* reserved vector 58 */
-  {NULL,NULL,0}, /* reserved vector 59 */
-  {NULL,NULL,0}, /* reserved vector 60 */
-  {NULL,NULL,0}, /* reserved vector 61 */
-  {NULL,NULL,0}, /* reserved vector 62 */
-  {NULL,NULL,0}, /* reserved vector 63 */
-  /* vector 64: RTC SEC   SIxxR_L  , Bit  0 */
-  {&mpc83xx.ipic.sipnr[1],&mpc83xx.ipic.simsr[1], 0},
-  /* vector 65: PIT       SIxxR_L  , Bit  1 */
-  {&mpc83xx.ipic.sipnr[1],&mpc83xx.ipic.simsr[1], 1},
-  /* vector 66: PCI1      SIxxR_L  , Bit  2 */
-  {&mpc83xx.ipic.sipnr[1],&mpc83xx.ipic.simsr[1], 2},
-  /* vector 67: PCI2      SIxxR_L  , Bit  3 */
-  {&mpc83xx.ipic.sipnr[1],&mpc83xx.ipic.simsr[1], 3},
-  /* vector 68: RTC ALR   SIxxR_L  , Bit  4 */
-  {&mpc83xx.ipic.sipnr[1],&mpc83xx.ipic.simsr[1], 4},
-  /* vector 69: MU        SIxxR_L  , Bit  5 */
-  {&mpc83xx.ipic.sipnr[1],&mpc83xx.ipic.simsr[1], 5},
-  /* vector 70: SBA       SIxxR_L  , Bit  6 */
-  {&mpc83xx.ipic.sipnr[1],&mpc83xx.ipic.simsr[1], 6},
-  /* vector 71: DMA       SIxxR_L  , Bit  7 */
-  {&mpc83xx.ipic.sipnr[1],&mpc83xx.ipic.simsr[1], 7},
-  /* vector 72: GTM4      SIxxR_L  , Bit  8 */
-  {&mpc83xx.ipic.sipnr[1],&mpc83xx.ipic.simsr[1], 8},
-  /* vector 73: GTM8      SIxxR_L  , Bit  9 */
-  {&mpc83xx.ipic.sipnr[1],&mpc83xx.ipic.simsr[1], 9},
-  /* vector 74: GPIO1     SIxxR_L  , Bit 10 */
-  {&mpc83xx.ipic.sipnr[1],&mpc83xx.ipic.simsr[1],10},
-  /* vector 75: GPIO2     SIxxR_L  , Bit 11 */
-  {&mpc83xx.ipic.sipnr[1],&mpc83xx.ipic.simsr[1],11},
-  /* vector 76: DDR       SIxxR_L  , Bit 12 */
-  {&mpc83xx.ipic.sipnr[1],&mpc83xx.ipic.simsr[1],12},
-  /* vector 77: LBC       SIxxR_L  , Bit 13 */
-  {&mpc83xx.ipic.sipnr[1],&mpc83xx.ipic.simsr[1],13},
-  /* vector 78: GTM2      SIxxR_L  , Bit 14 */
-  {&mpc83xx.ipic.sipnr[1],&mpc83xx.ipic.simsr[1],14},
-  /* vector 79: GTM6      SIxxR_L  , Bit 15 */
-  {&mpc83xx.ipic.sipnr[1],&mpc83xx.ipic.simsr[1],15},
-  /* vector 80: PMC       SIxxR_L  , Bit 16 */
-  {&mpc83xx.ipic.sipnr[1],&mpc83xx.ipic.simsr[1],16},
-  {NULL,NULL,0}, /* reserved vector 81 */
-  {NULL,NULL,0}, /* reserved vector 82 */
-  {NULL,NULL,0}, /* reserved vector 63 */
-  /* vector 84: GTM3      SIxxR_L  , Bit 20 */
-  {&mpc83xx.ipic.sipnr[1],&mpc83xx.ipic.simsr[1],20},
-  /* vector 85: GTM7      SIxxR_L  , Bit 21 */
-  {&mpc83xx.ipic.sipnr[1],&mpc83xx.ipic.simsr[1],21},
-  {NULL,NULL,0}, /* reserved vector 81 */
-  {NULL,NULL,0}, /* reserved vector 82 */
-  {NULL,NULL,0}, /* reserved vector 63 */
-  {NULL,NULL,0}, /* reserved vector 63 */
-  /* vector 90: GTM1      SIxxR_L  , Bit 26 */
-  {&mpc83xx.ipic.sipnr[1],&mpc83xx.ipic.simsr[1],26},
-  /* vector 91: GTM5      SIxxR_L  , Bit 27 */
-  {&mpc83xx.ipic.sipnr[1],&mpc83xx.ipic.simsr[1],27}
-};
-
-/*
- * data structure to handle all mask registers in the IPIC
- */
-typedef struct {
-  uint32_t simsr_mask[2];
-  uint32_t semsr_mask;
-  uint32_t sermr_mask;
-} BSP_ipic_mask_t;
-
-/*
- * this array will be filled with mask values needed 
- * to temporarily disable all IRQ soures with lower or same
- * priority of the current source (whose vector is the array index)
- */
-BSP_ipic_mask_t BSP_ipic_prio2mask[BSP_ARRAY_CNT(BSP_ipic_isrc_rsc)];
-
-
-/*
- * functions to enable/disable a source at the ipic
- */
-void BSP_irq_enable_at_ipic (rtems_irq_number irqnum)
-{
-  uint32_t vecnum = irqnum - BSP_IPIC_IRQ_LOWEST_OFFSET;
-  const BSP_isrc_rsc_t *rsc_ptr;
-  
-  if ((vecnum >= 0) 
-      && (vecnum < BSP_ARRAY_CNT(BSP_ipic_isrc_rsc))) {
-    rsc_ptr = &BSP_ipic_isrc_rsc[vecnum];
-    if (rsc_ptr->mask_reg != NULL) {
-      *(rsc_ptr->mask_reg) |= 1 << (31-rsc_ptr->bit_num);
-    }
-  }
-}
-
-void BSP_irq_disable_at_ipic (rtems_irq_number irqnum)
-{
-  uint32_t vecnum = irqnum - BSP_IPIC_IRQ_LOWEST_OFFSET;
-  const BSP_isrc_rsc_t *rsc_ptr;
-  
-  if ((vecnum >= 0) 
-      && (vecnum < BSP_ARRAY_CNT(BSP_ipic_isrc_rsc))) {
-    rsc_ptr = &BSP_ipic_isrc_rsc[vecnum];
-    if (rsc_ptr->mask_reg != NULL) {
-      *(rsc_ptr->mask_reg) &= ~(1 << (31-rsc_ptr->bit_num));
-    }
-  }
-}
-
-
-/*
- *  IRQ Handler: this is called from the primary exception dispatcher
- */
-rtems_status_code BSP_irq_handle_at_ipic(uint32_t excNum)
-{
-  rtems_status_code rc = RTEMS_SUCCESSFUL;
-  rtems_irq_connect_data *tbl_entry;
-  int32_t vecnum;
-  uint32_t msr_value;
-  uint32_t msr_save;
-  uint32_t msr_enable = 0;
-  BSP_ipic_mask_t mask_save;
-  const BSP_ipic_mask_t *mask_ptr;
-  /*
-   * get vector
-   */
-  switch(excNum) {
-  case ASM_EXT_VECTOR:
-    vecnum = MPC83xx_VCR_TO_VEC(mpc83xx.ipic.sivcr);
-    msr_enable = PPC_MSR_EE;
-    break;
-  case ASM_60X_SYSMGMT_VECTOR:
-    vecnum = MPC83xx_VCR_TO_VEC(mpc83xx.ipic.smvcr);
-    msr_enable = PPC_MSR_EE;
-    break;
-#if defined(ASM_BOOKE_CRIT_VECTOR)
-  case ASM_BOOKE_CRIT_VECTOR:
-    vecnum = MPC83xx_VCR_TO_VEC(mpc83xx.ipic.scvcr);
-    break;
-#endif
-  default:
-    vecnum = -1;
-  }
-  /*
-   * check vector number
-   */
-  if ((vecnum >= 0) 
-      && (vecnum < BSP_ARRAY_CNT(BSP_ipic_isrc_rsc))) {
-    /*
-     * save current mask registers
-     */
-    mask_save.simsr_mask[0] = mpc83xx.ipic.simsr[0];
-    mask_save.simsr_mask[1] = mpc83xx.ipic.simsr[1];
-    mask_save.semsr_mask    = mpc83xx.ipic.semsr   ;
-    mask_save.sermr_mask    = mpc83xx.ipic.sermr   ;
-    /*
-     * mask all lower prio interrupts
-     */
-    mask_ptr = &BSP_ipic_prio2mask[vecnum];
-    mpc83xx.ipic.simsr[0] &= mask_ptr->simsr_mask[0];
-    mpc83xx.ipic.simsr[1] &= mask_ptr->simsr_mask[1];
-    mpc83xx.ipic.semsr    &= mask_ptr->semsr_mask   ;
-    mpc83xx.ipic.sermr    &= mask_ptr->sermr_mask   ;
-
-    /* 
-     * make sure, that the masking operations in 
-     * ICTL and MSR are executed in order
-     */
-    asm volatile("sync":::"memory");
-    
-    /*
-     * reenable msr_ee
-     */
-    _CPU_MSR_GET(msr_value);
-    msr_save   = msr_value;
-    msr_value |= msr_enable;
-    _CPU_MSR_SET(msr_value);
-    /*
-     * call handler
-     */
-    tbl_entry = &BSP_rtems_irq_tbl[vecnum+BSP_IPIC_IRQ_LOWEST_OFFSET];
-    if (tbl_entry->hdl != NULL) {
-      (tbl_entry->hdl) (tbl_entry->handle);
-    } else {
-      printk("IPIC: Spurious interrupt; excNum=0x%x, vector=0x%02x\n\r",
-	     excNum,vecnum);
-    }
-    /*
-     * disable msr_enable
-     */
-    _CPU_MSR_SET(msr_save);
-
-    /* 
-     * make sure, that the masking operations in 
-     * ICTL and MSR are executed in order
-     */
-    asm volatile("sync":::"memory");
-
-    /*
-     * restore initial masks
-     */
-    mpc83xx.ipic.simsr[0] = mask_save.simsr_mask[0];
-    mpc83xx.ipic.simsr[1] = mask_save.simsr_mask[1];
-    mpc83xx.ipic.semsr    = mask_save.semsr_mask   ;
-    mpc83xx.ipic.sermr    = mask_save.sermr_mask   ;
-  }
-  return rc;
-}
-
-
-/*
- * fill the array BSP_ipic_prio2mask to allow masking of lower prio sources
- * to implement nested interrupts
- */
-rtems_status_code BSP_ipic_calc_prio2mask(void)
-{
-  rtems_status_code rc = RTEMS_SUCCESSFUL;
-  /*
-   * FIXME: fill the array
-   */
-  return rc;
-}
-
-/*
- * activate the interrupt controller
- */
-rtems_status_code BSP_ipic_intc_init(void)
-{
-  uint32_t msr_value;
-  rtems_status_code rc = RTEMS_SUCCESSFUL;
-
-  /* 
-   * mask off all interrupts 
-   */
-  mpc83xx.ipic.simsr[0] = 0;
-  mpc83xx.ipic.simsr[1] = 0;
-  mpc83xx.ipic.semsr    = 0;
-  mpc83xx.ipic.sermr    = 0;
-  /*
-   * set desired configuration as defined in bspopts.h
-   * normally, the default values should be fine
-   */
-#if defined(BSP_SICFR_VAL) /* defined in bspopts.h ? */
-  mpc83xx.ipic.sicfr = BSP_SICFR_VAL;
-#endif
-
-  /*
-   * set desired priorities as defined in bspopts.h
-   * normally, the default values should be fine
-   */
-#if defined(BSP_SIPRR0_VAL) /* defined in bspopts.h ? */
-  mpc83xx.ipic.siprr[0] = BSP_SIPRR0_VAL;
-#endif
-
-#if defined(BSP_SIPRR1_VAL) /* defined in bspopts.h ? */
-  mpc83xx.ipic.siprr[1] = BSP_SIPRR1_VAL;
-#endif
-
-#if defined(BSP_SIPRR2_VAL) /* defined in bspopts.h ? */
-  mpc83xx.ipic.siprr[2] = BSP_SIPRR2_VAL;
-#endif
-
-#if defined(BSP_SIPRR3_VAL) /* defined in bspopts.h ? */
-  mpc83xx.ipic.siprr[3] = BSP_SIPRR3_VAL;
-#endif
-
-#if defined(BSP_SMPRR0_VAL) /* defined in bspopts.h ? */
-  mpc83xx.ipic.smprr[0] = BSP_SMPRR0_VAL;
-#endif
-
-#if defined(BSP_SMPRR1_VAL) /* defined in bspopts.h ? */
-  mpc83xx.ipic.smprr[1] = BSP_SMPRR1_VAL;
-#endif
-
-#if defined(BSP_SECNR_VAL) /* defined in bspopts.h ? */
-  mpc83xx.ipic.secnr    = BSP_SECNR_VAL;
-#endif
-
-  /*
-   * calculate priority masks
-   */
-  rc = BSP_ipic_calc_prio2mask();
-  if (rc == RTEMS_SUCCESSFUL) {
-    /*
-     * enable (non-critical) exceptions
-     */
-    
-    _CPU_MSR_GET(msr_value);
-    msr_value |= PPC_MSR_EE;
-    _CPU_MSR_SET(msr_value);
-    
-    /* install exit handler to close ipic when program atexit called */
-    /* atexit(ipic_intc_exit); */
-  }
-  return rc;
-}
-
Index: c/src/lib/libbsp/powerpc/gen83xx/irq/irq.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/irq/irq.c	(revision 574fb675105b77dfe9598915207f1f32790f905f)
+++ c/src/lib/libbsp/powerpc/gen83xx/irq/irq.c	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -0,0 +1,576 @@
+/*===============================================================*\
+| Project: RTEMS generic MPC83xx BSP                              |
++-----------------------------------------------------------------+
+|                    Copyright (c) 2007                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.com/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+| this file integrates the IPIC irq controller                    |
+\*===============================================================*/
+
+#include <mpc83xx/mpc83xx.h>
+
+#include <rtems.h>
+
+#include <libcpu/powerpc-utility.h>
+#include <libcpu/raw_exception.h>
+
+#include <bsp.h>
+#include <bsp/irq.h>
+#include <bsp/vectors.h>
+#include <bsp/ppc_exc_bspsupp.h>
+#include <bsp/irq-generic.h>
+
+#define MPC83XX_IPIC_VECTOR_NUMBER 92
+
+#define MPC83XX_IPIC_IS_VALID_VECTOR( vector) ((vector) >= 0 && (vector) < MPC83XX_IPIC_VECTOR_NUMBER)
+
+#define MPC83XX_IPIC_INVALID_MASK_POSITION 255
+
+typedef struct {
+	volatile uint32_t *pend_reg;
+	volatile uint32_t *mask_reg;
+	const uint32_t bit_num;
+} BSP_isrc_rsc_t;
+
+/*
+ * data structure to handle all mask registers in the IPIC
+ *
+ * Mask positions:
+ *   simsr [0] :  0 .. 31
+ *   simsr [1] : 32 .. 63
+ *   semsr     : 64 .. 95
+ *   sermr     : 96 .. 127
+ */
+typedef struct {
+	uint32_t simsr_mask [2];
+	uint32_t semsr_mask;
+	uint32_t sermr_mask;
+} mpc83xx_ipic_mask_t;
+
+static const BSP_isrc_rsc_t mpc83xx_ipic_isrc_rsc [MPC83XX_IPIC_VECTOR_NUMBER] = {
+	/* vector 0 */
+	{&mpc83xx.ipic.sersr, &mpc83xx.ipic.sermr, 31},
+	{NULL, NULL, 0},
+	{NULL, NULL, 0},
+	{NULL, NULL, 0},
+	{NULL, NULL, 0},
+	{NULL, NULL, 0},
+	{NULL, NULL, 0},
+	{NULL, NULL, 0},
+	/* vector  8 */
+	{NULL, NULL, 0},	/* reserved vector  8 */
+	/* vector  9: UART1 SIxxR_H, Bit 24 */
+	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 24},
+	/* vector 10: UART2 SIxxR_H, Bit 25 */
+	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 25},
+	/* vector 11: SEC   SIxxR_H, Bit 26 */
+	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 26},
+	{NULL, NULL, 0},	/* reserved vector 12 */
+	{NULL, NULL, 0},	/* reserved vector 13 */
+	/* vector 14: I2C1 SIxxR_H, Bit 29 */
+	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 29},
+	/* vector 15: I2C2 SIxxR_H, Bit 30 */
+	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 30},
+	/* vector 16: SPI  SIxxR_H, Bit 31 */
+	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 31},
+	/* vector 17: IRQ1 SExxR  , Bit  1 */
+	{&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 1},
+	/* vector 18: IRQ2 SExxR  , Bit  2 */
+	{&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 2},
+	/* vector 19: IRQ3 SExxR  , Bit  3 */
+	{&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 3},
+	/* vector 20: IRQ4 SExxR  , Bit  4 */
+	{&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 4},
+	/* vector 21: IRQ5 SExxR  , Bit  5 */
+	{&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 5},
+	/* vector 22: IRQ6 SExxR  , Bit  6 */
+	{&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 6},
+	/* vector 23: IRQ7 SExxR  , Bit  7 */
+	{&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 7},
+	{NULL, NULL, 0},	/* reserved vector 24 */
+	{NULL, NULL, 0},	/* reserved vector 25 */
+	{NULL, NULL, 0},	/* reserved vector 26 */
+	{NULL, NULL, 0},	/* reserved vector 27 */
+	{NULL, NULL, 0},	/* reserved vector 28 */
+	{NULL, NULL, 0},	/* reserved vector 29 */
+	{NULL, NULL, 0},	/* reserved vector 30 */
+	{NULL, NULL, 0},	/* reserved vector 31 */
+	/* vector 32: TSEC1 Tx  SIxxR_H  , Bit  0 */
+	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 0},
+	/* vector 33: TSEC1 Rx  SIxxR_H  , Bit  1 */
+	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 1},
+	/* vector 34: TSEC1 Err SIxxR_H  , Bit  2 */
+	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 2},
+	/* vector 35: TSEC2 Tx  SIxxR_H  , Bit  3 */
+	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 3},
+	/* vector 36: TSEC2 Rx  SIxxR_H  , Bit  4 */
+	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 4},
+	/* vector 37: TSEC2 Err SIxxR_H  , Bit  5 */
+	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 5},
+	/* vector 38: USB DR    SIxxR_H  , Bit  6 */
+	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 6},
+	/* vector 39: USB MPH   SIxxR_H  , Bit  7 */
+	{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 7},
+	{NULL, NULL, 0},	/* reserved vector 40 */
+	{NULL, NULL, 0},	/* reserved vector 41 */
+	{NULL, NULL, 0},	/* reserved vector 42 */
+	{NULL, NULL, 0},	/* reserved vector 43 */
+	{NULL, NULL, 0},	/* reserved vector 44 */
+	{NULL, NULL, 0},	/* reserved vector 45 */
+	{NULL, NULL, 0},	/* reserved vector 46 */
+	{NULL, NULL, 0},	/* reserved vector 47 */
+	/* vector 48: IRQ0 SExxR  , Bit  0 */
+	{&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 0},
+	{NULL, NULL, 0},	/* reserved vector 49 */
+	{NULL, NULL, 0},	/* reserved vector 50 */
+	{NULL, NULL, 0},	/* reserved vector 51 */
+	{NULL, NULL, 0},	/* reserved vector 52 */
+	{NULL, NULL, 0},	/* reserved vector 53 */
+	{NULL, NULL, 0},	/* reserved vector 54 */
+	{NULL, NULL, 0},	/* reserved vector 55 */
+	{NULL, NULL, 0},	/* reserved vector 56 */
+	{NULL, NULL, 0},	/* reserved vector 57 */
+	{NULL, NULL, 0},	/* reserved vector 58 */
+	{NULL, NULL, 0},	/* reserved vector 59 */
+	{NULL, NULL, 0},	/* reserved vector 60 */
+	{NULL, NULL, 0},	/* reserved vector 61 */
+	{NULL, NULL, 0},	/* reserved vector 62 */
+	{NULL, NULL, 0},	/* reserved vector 63 */
+	/* vector 64: RTC SEC   SIxxR_L  , Bit  0 */
+	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 0},
+	/* vector 65: PIT       SIxxR_L  , Bit  1 */
+	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 1},
+	/* vector 66: PCI1      SIxxR_L  , Bit  2 */
+	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 2},
+	/* vector 67: PCI2      SIxxR_L  , Bit  3 */
+	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 3},
+	/* vector 68: RTC ALR   SIxxR_L  , Bit  4 */
+	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 4},
+	/* vector 69: MU        SIxxR_L  , Bit  5 */
+	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 5},
+	/* vector 70: SBA       SIxxR_L  , Bit  6 */
+	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 6},
+	/* vector 71: DMA       SIxxR_L  , Bit  7 */
+	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 7},
+	/* vector 72: GTM4      SIxxR_L  , Bit  8 */
+	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 8},
+	/* vector 73: GTM8      SIxxR_L  , Bit  9 */
+	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 9},
+	/* vector 74: GPIO1     SIxxR_L  , Bit 10 */
+	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 10},
+	/* vector 75: GPIO2     SIxxR_L  , Bit 11 */
+	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 11},
+	/* vector 76: DDR       SIxxR_L  , Bit 12 */
+	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 12},
+	/* vector 77: LBC       SIxxR_L  , Bit 13 */
+	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 13},
+	/* vector 78: GTM2      SIxxR_L  , Bit 14 */
+	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 14},
+	/* vector 79: GTM6      SIxxR_L  , Bit 15 */
+	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 15},
+	/* vector 80: PMC       SIxxR_L  , Bit 16 */
+	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 16},
+	{NULL, NULL, 0},	/* reserved vector 81 */
+	{NULL, NULL, 0},	/* reserved vector 82 */
+	{NULL, NULL, 0},	/* reserved vector 63 */
+	/* vector 84: GTM3      SIxxR_L  , Bit 20 */
+	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 20},
+	/* vector 85: GTM7      SIxxR_L  , Bit 21 */
+	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 21},
+	{NULL, NULL, 0},	/* reserved vector 81 */
+	{NULL, NULL, 0},	/* reserved vector 82 */
+	{NULL, NULL, 0},	/* reserved vector 63 */
+	{NULL, NULL, 0},	/* reserved vector 63 */
+	/* vector 90: GTM1      SIxxR_L  , Bit 26 */
+	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 26},
+	/* vector 91: GTM5      SIxxR_L  , Bit 27 */
+	{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 27}
+};
+
+static const uint8_t mpc83xx_ipic_mask_position_table [MPC83XX_IPIC_VECTOR_NUMBER] = {
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	7,
+	6,
+	5,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	2,
+	1,
+	0,
+	94,
+	93,
+	92,
+	91,
+	90,
+	89,
+	88,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	31,
+	30,
+	29,
+	28,
+	27,
+	26,
+	25,
+	24,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	95,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	63,
+	62,
+	61,
+	60,
+	59,
+	58,
+	57,
+	56,
+	55,
+	54,
+	53,
+	52,
+	51,
+	50,
+	49,
+	48,
+	47,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	43,
+	42,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	MPC83XX_IPIC_INVALID_MASK_POSITION,
+	37,
+	36
+};
+
+/*
+ * this array will be filled with mask values needed 
+ * to temporarily disable all IRQ soures with lower or same
+ * priority of the current source (whose vector is the array index)
+ */
+static mpc83xx_ipic_mask_t mpc83xx_ipic_prio2mask [MPC83XX_IPIC_VECTOR_NUMBER];
+
+rtems_status_code mpc83xx_ipic_set_mask( rtems_vector_number vector, rtems_vector_number mask_vector, bool mask)
+{
+	uint8_t pos = 0;
+	mpc83xx_ipic_mask_t *mask_entry;
+	uint32_t *mask_reg;
+	rtems_interrupt_level level;
+
+	/* Parameter check */
+	if (!MPC83XX_IPIC_IS_VALID_VECTOR( vector) || !MPC83XX_IPIC_IS_VALID_VECTOR( mask_vector)) {
+		return RTEMS_INVALID_NUMBER;
+	} else if (vector == mask_vector) {
+		return RTEMS_RESOURCE_IN_USE;
+	}
+
+	/* Position and mask entry */
+	pos = mpc83xx_ipic_mask_position_table [mask_vector];
+	mask_entry = &mpc83xx_ipic_prio2mask [vector];
+
+	/* Mask register and position */
+	if (pos < 32) {
+		mask_reg = &mask_entry->simsr_mask [0];
+	} else if (pos < 64) {
+		pos -= 32;
+		mask_reg = &mask_entry->simsr_mask [1];
+	} else if (pos < 96) {
+		pos -= 64;
+		mask_reg = &mask_entry->semsr_mask;
+	} else if (pos < 128) {
+		pos -= 96;
+		mask_reg = &mask_entry->sermr_mask;
+	} else {
+		return RTEMS_NOT_IMPLEMENTED;
+	}
+
+	/* Mask or unmask */
+	if (mask) {
+		rtems_interrupt_disable( level);
+		*mask_reg &= ~(1 << pos);
+		rtems_interrupt_enable( level);
+	} else {
+		rtems_interrupt_disable( level);
+		*mask_reg |= 1 << pos;
+		rtems_interrupt_enable( level);
+	}
+
+	return RTEMS_SUCCESSFUL;
+}
+
+rtems_status_code mpc83xx_ipic_set_highest_priority_interrupt( rtems_vector_number vector, int type)
+{
+	rtems_interrupt_level level;
+	uint32_t reg = 0;
+
+	if (!MPC83XX_IPIC_IS_VALID_VECTOR( vector)) {
+		return RTEMS_INVALID_NUMBER;
+	} else if (type < 0 || type > MPC83XX_IPIC_INTERRUPT_CRITICAL) {
+		return RTEMS_INVALID_NUMBER;
+	}
+
+	rtems_interrupt_disable( level);
+	reg = mpc83xx.ipic.sicfr;
+	mpc83xx.ipic.sicfr = (reg & ~0x7f000300) | (vector << 24) | (type << 8);
+	rtems_interrupt_enable( level);
+
+	return RTEMS_SUCCESSFUL;
+}
+
+/*
+ * functions to enable/disable a source at the ipic
+ */
+rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number irqnum)
+{
+	rtems_vector_number vecnum = irqnum - BSP_IPIC_IRQ_LOWEST_OFFSET;
+	const BSP_isrc_rsc_t *rsc_ptr;
+
+	if (MPC83XX_IPIC_IS_VALID_VECTOR( vecnum)) {
+		rsc_ptr = &mpc83xx_ipic_isrc_rsc [vecnum];
+		if (rsc_ptr->mask_reg != NULL) {
+			*(rsc_ptr->mask_reg) |= 1 << (31 - rsc_ptr->bit_num);
+		}
+	}
+
+	return RTEMS_SUCCESSFUL;
+}
+
+rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number irqnum)
+{
+	rtems_vector_number vecnum = irqnum - BSP_IPIC_IRQ_LOWEST_OFFSET;
+	const BSP_isrc_rsc_t *rsc_ptr;
+
+	if (MPC83XX_IPIC_IS_VALID_VECTOR( vecnum)) {
+		rsc_ptr = &mpc83xx_ipic_isrc_rsc [vecnum];
+		if (rsc_ptr->mask_reg != NULL) {
+			*(rsc_ptr->mask_reg) &= ~(1 << (31 - rsc_ptr->bit_num));
+		}
+	}
+
+	return RTEMS_SUCCESSFUL;
+}
+
+
+/*
+ *  IRQ Handler: this is called from the primary exception dispatcher
+ */
+static int BSP_irq_handle_at_ipic( unsigned excNum)
+{
+	int32_t vecnum;
+	mpc83xx_ipic_mask_t mask_save;
+	const mpc83xx_ipic_mask_t *mask_ptr;
+	uint32_t msr;
+	rtems_interrupt_level level;
+
+	/* Get vector number */
+	switch (excNum) {
+		case ASM_EXT_VECTOR:
+			vecnum = MPC83xx_VCR_TO_VEC( mpc83xx.ipic.sivcr);
+			break;
+		case ASM_E300_SYSMGMT_VECTOR:
+			vecnum = MPC83xx_VCR_TO_VEC( mpc83xx.ipic.smvcr);
+			break;
+		case ASM_E300_CRIT_VECTOR:
+			vecnum = MPC83xx_VCR_TO_VEC( mpc83xx.ipic.scvcr);
+			break;
+		default:
+			return 1;
+	}
+
+	/*
+	 * Check the vector number, mask lower priority interrupts, enable
+	 * exceptions and dispatch the handler.
+	 */
+	if (MPC83XX_IPIC_IS_VALID_VECTOR( vecnum)) {
+		mask_ptr = &mpc83xx_ipic_prio2mask [vecnum];
+
+		rtems_interrupt_disable( level);
+
+		/* Save current mask registers */
+		mask_save.simsr_mask [0] = mpc83xx.ipic.simsr [0];
+		mask_save.simsr_mask [1] = mpc83xx.ipic.simsr [1];
+		mask_save.semsr_mask = mpc83xx.ipic.semsr;
+		mask_save.sermr_mask = mpc83xx.ipic.sermr;
+
+		/* Mask all lower priority interrupts */
+		mpc83xx.ipic.simsr [0] &= mask_ptr->simsr_mask [0];
+		mpc83xx.ipic.simsr [1] &= mask_ptr->simsr_mask [1];
+		mpc83xx.ipic.semsr &= mask_ptr->semsr_mask;
+		mpc83xx.ipic.sermr &= mask_ptr->sermr_mask;
+
+		rtems_interrupt_enable( level);
+
+		/* Enable all interrupts */
+		if (excNum != ASM_E300_CRIT_VECTOR) {
+			msr = ppc_external_exceptions_enable();
+		}
+
+		/* Dispatch interrupt handlers */
+		bsp_interrupt_handler_dispatch( vecnum + BSP_IPIC_IRQ_LOWEST_OFFSET);
+
+		/* Restore machine state */
+		if (excNum != ASM_E300_CRIT_VECTOR) {
+			ppc_external_exceptions_disable( msr);
+		}
+
+		/* Restore initial masks */
+		rtems_interrupt_disable( level);
+		mpc83xx.ipic.simsr [0] = mask_save.simsr_mask [0];
+		mpc83xx.ipic.simsr [1] = mask_save.simsr_mask [1];
+		mpc83xx.ipic.semsr = mask_save.semsr_mask;
+		mpc83xx.ipic.sermr = mask_save.sermr_mask;
+		rtems_interrupt_enable( level);
+	} else {
+		bsp_interrupt_handler_default( vecnum);
+	}
+
+	return 0;
+}
+
+/*
+ * Fill the array mpc83xx_ipic_prio2mask to allow masking of lower prio sources
+ * to implement nested interrupts.
+ */
+rtems_status_code mpc83xx_ipic_calc_prio2mask( void)
+{
+	rtems_status_code rc = RTEMS_SUCCESSFUL;
+
+	/*
+	 * FIXME: fill the array
+	 */
+	return rc;
+}
+
+/*
+ * Activate the interrupt controller
+ */
+rtems_status_code mpc83xx_ipic_initialize( void)
+{
+	/* 
+	 * mask off all interrupts 
+	 */
+	mpc83xx.ipic.simsr [0] = 0;
+	mpc83xx.ipic.simsr [1] = 0;
+	mpc83xx.ipic.semsr = 0;
+	mpc83xx.ipic.sermr = 0;
+	/*
+	 * set desired configuration as defined in bspopts.h
+	 * normally, the default values should be fine
+	 */
+#if defined( BSP_SICFR_VAL)	/* defined in bspopts.h ? */
+	mpc83xx.ipic.sicfr = BSP_SICFR_VAL;
+#endif
+
+	/*
+	 * set desired priorities as defined in bspopts.h
+	 * normally, the default values should be fine
+	 */
+#if defined( BSP_SIPRR0_VAL)	/* defined in bspopts.h ? */
+	mpc83xx.ipic.siprr [0] = BSP_SIPRR0_VAL;
+#endif
+
+#if defined( BSP_SIPRR1_VAL)	/* defined in bspopts.h ? */
+	mpc83xx.ipic.siprr [1] = BSP_SIPRR1_VAL;
+#endif
+
+#if defined( BSP_SIPRR2_VAL)	/* defined in bspopts.h ? */
+	mpc83xx.ipic.siprr [2] = BSP_SIPRR2_VAL;
+#endif
+
+#if defined( BSP_SIPRR3_VAL)	/* defined in bspopts.h ? */
+	mpc83xx.ipic.siprr [3] = BSP_SIPRR3_VAL;
+#endif
+
+#if defined( BSP_SMPRR0_VAL)	/* defined in bspopts.h ? */
+	mpc83xx.ipic.smprr [0] = BSP_SMPRR0_VAL;
+#endif
+
+#if defined( BSP_SMPRR1_VAL)	/* defined in bspopts.h ? */
+	mpc83xx.ipic.smprr [1] = BSP_SMPRR1_VAL;
+#endif
+
+#if defined( BSP_SECNR_VAL)	/* defined in bspopts.h ? */
+	mpc83xx.ipic.secnr = BSP_SECNR_VAL;
+#endif
+
+	/*
+	 * calculate priority masks
+	 */
+	return mpc83xx_ipic_calc_prio2mask();
+}
+
+int mpc83xx_exception_handler( BSP_Exception_frame *frame, unsigned exception_number)
+{
+	return BSP_irq_handle_at_ipic( exception_number);
+}
+
+rtems_status_code bsp_interrupt_facility_initialize()
+{
+	/* Install exception handler */
+	if (ppc_exc_set_handler( ASM_EXT_VECTOR, mpc83xx_exception_handler)) {
+		return RTEMS_IO_ERROR;
+	}
+	if (ppc_exc_set_handler( ASM_E300_SYSMGMT_VECTOR, mpc83xx_exception_handler)) {
+		return RTEMS_IO_ERROR;
+	}
+	if (ppc_exc_set_handler( ASM_E300_CRIT_VECTOR, mpc83xx_exception_handler)) {
+		return RTEMS_IO_ERROR;
+	}
+
+	/* Initialize the interrupt controller */
+	return mpc83xx_ipic_initialize();
+}
+
+void bsp_interrupt_handler_default( rtems_vector_number vector)
+{
+	printk( "Spurious interrupt: 0x%08x\n", vector);
+}
Index: c/src/lib/libbsp/powerpc/gen83xx/irq/irq.h
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/irq/irq.h	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ 	(revision )
@@ -1,143 +1,0 @@
-/*===============================================================*\
-| Project: RTEMS generic MPC83xx BSP                              |
-+-----------------------------------------------------------------+
-|                    Copyright (c) 2007                           |
-|                    Embedded Brains GmbH                         |
-|                    Obere Lagerstr. 30                           |
-|                    D-82178 Puchheim                             |
-|                    Germany                                      |
-|                    rtems@embedded-brains.de                     |
-+-----------------------------------------------------------------+
-| The license and distribution terms for this file may be         |
-| found in the file LICENSE in this distribution or at            |
-|                                                                 |
-| http://www.rtems.com/license/LICENSE.                           |
-|                                                                 |
-+-----------------------------------------------------------------+
-| this file declares constants of the interrupt controller        |
-\*===============================================================*/
-#ifndef GEN83xx_IRQ_IRQ_H
-#define GEN83xx_IRQ_IRQ_H
-
-#include <rtems.h>
-#include <rtems/irq.h>
-
-/*
- * the following definitions specify the indices used 
- * to interface the interrupt handler API
- */
-
-/*
- * Peripheral IRQ handlers related definitions
- */
-#define BSP_IPIC_PER_IRQ_NUMBER	        128
-#define BSP_IPIC_IRQ_LOWEST_OFFSET        0
-#define BSP_IPIC_IRQ_MAX_OFFSET      (BSP_IPIC_IRQ_LOWEST_OFFSET\
-                                         +BSP_IPIC_PER_IRQ_NUMBER-1)
-
-#define BSP_IS_IPIC_IRQ(irqnum)				\
-          (((irqnum) >= BSP_IPIC_IRQ_LOWEST_OFFSET) &&	\
-	   ((irqnum) <= BSP_IPIC_IRQ_MAX_OFFSET))
-/*
- * Processor IRQ handlers related definitions
- */
-#define BSP_PROCESSOR_IRQ_NUMBER        1
-#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET	(BSP_IPIC_IRQ_MAX_OFFSET+1)
-#define BSP_PROCESSOR_IRQ_MAX_OFFSET	(BSP_PROCESSOR_IRQ_LOWEST_OFFSET\
-                                         +BSP_PROCESSOR_IRQ_NUMBER-1)
-
-#define BSP_IS_PROCESSOR_IRQ(irqnum)				\
-          (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) &&	\
-	   ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET))
-/*
- * Summary
- */
-#define BSP_IRQ_NUMBER                  (BSP_PROCESSOR_IRQ_MAX_OFFSET+1)
-#define BSP_LOWEST_OFFSET		BSP_IPIC_IRQ_LOWEST_OFFSET
-#define BSP_MAX_OFFSET                  BSP_PROCESSOR_IRQ_MAX_OFFSET
-
-#define BSP_IS_VALID_IRQ(irqnum) 	\
-          (BSP_IS_PROCESSOR_IRQ(irqnum)	\
-           || BSP_IS_IPIC_IRQ(irqnum))
-
-#ifndef ASM
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * index table for the module specific handlers, a few entries are only placeholders
- */
-  typedef enum {
-    BSP_IPIC_IRQ_FIRST	   = BSP_IPIC_IRQ_LOWEST_OFFSET,
-    BSP_IPIC_IRQ_ERROR	   = BSP_IPIC_IRQ_LOWEST_OFFSET +  0,
-    /* reserved irqs  1- 8 */
-    BSP_IPIC_IRQ_UART1	   = BSP_IPIC_IRQ_LOWEST_OFFSET +  9,
-    BSP_IPIC_IRQ_UART2 	   = BSP_IPIC_IRQ_LOWEST_OFFSET + 10,
-    BSP_IPIC_IRQ_SEC  	   = BSP_IPIC_IRQ_LOWEST_OFFSET + 11,
-    /* reserved irqs 12-13 */
-    BSP_IPIC_IRQ_I2C1      = BSP_IPIC_IRQ_LOWEST_OFFSET + 14,
-    BSP_IPIC_IRQ_I2C2      = BSP_IPIC_IRQ_LOWEST_OFFSET + 15,
-    BSP_IPIC_IRQ_SPI       = BSP_IPIC_IRQ_LOWEST_OFFSET + 16,
-    BSP_IPIC_IRQ_IRQ1      = BSP_IPIC_IRQ_LOWEST_OFFSET + 17,
-    BSP_IPIC_IRQ_IRQ2      = BSP_IPIC_IRQ_LOWEST_OFFSET + 18,
-    BSP_IPIC_IRQ_IRQ3      = BSP_IPIC_IRQ_LOWEST_OFFSET + 19,
-    BSP_IPIC_IRQ_IRQ4      = BSP_IPIC_IRQ_LOWEST_OFFSET + 20,
-    BSP_IPIC_IRQ_IRQ5      = BSP_IPIC_IRQ_LOWEST_OFFSET + 21,
-    BSP_IPIC_IRQ_IRQ6      = BSP_IPIC_IRQ_LOWEST_OFFSET + 22,
-    BSP_IPIC_IRQ_IRQ7      = BSP_IPIC_IRQ_LOWEST_OFFSET + 23,
-    /* reserved irqs 24-31 */
-    BSP_IPIC_IRQ_TSEC1_TX  = BSP_IPIC_IRQ_LOWEST_OFFSET + 32,
-    BSP_IPIC_IRQ_TSEC1_RX  = BSP_IPIC_IRQ_LOWEST_OFFSET + 33,
-    BSP_IPIC_IRQ_TSEC1_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 34,
-    BSP_IPIC_IRQ_TSEC2_TX  = BSP_IPIC_IRQ_LOWEST_OFFSET + 35,
-    BSP_IPIC_IRQ_TSEC2_RX  = BSP_IPIC_IRQ_LOWEST_OFFSET + 36,
-    BSP_IPIC_IRQ_TSEC2_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 37,
-    BSP_IPIC_IRQ_USB_DR    = BSP_IPIC_IRQ_LOWEST_OFFSET + 38,
-    BSP_IPIC_IRQ_USB_MPH   = BSP_IPIC_IRQ_LOWEST_OFFSET + 39,
-    /* reserved irqs 40-47 */
-    BSP_IPIC_IRQ_IRQ0      = BSP_IPIC_IRQ_LOWEST_OFFSET + 48,
-    /* reserved irqs 49-63 */
-    BSP_IPIC_IRQ_RTC_SEC   = BSP_IPIC_IRQ_LOWEST_OFFSET + 64,
-    BSP_IPIC_IRQ_PIT       = BSP_IPIC_IRQ_LOWEST_OFFSET + 65,
-    BSP_IPIC_IRQ_PCI1      = BSP_IPIC_IRQ_LOWEST_OFFSET + 66,
-    BSP_IPIC_IRQ_PCI2      = BSP_IPIC_IRQ_LOWEST_OFFSET + 67,
-    BSP_IPIC_IRQ_RTC_ALR   = BSP_IPIC_IRQ_LOWEST_OFFSET + 68,
-    BSP_IPIC_IRQ_MU        = BSP_IPIC_IRQ_LOWEST_OFFSET + 69,
-    BSP_IPIC_IRQ_SBA       = BSP_IPIC_IRQ_LOWEST_OFFSET + 70,
-    BSP_IPIC_IRQ_DMA       = BSP_IPIC_IRQ_LOWEST_OFFSET + 71,
-    BSP_IPIC_IRQ_GTM4      = BSP_IPIC_IRQ_LOWEST_OFFSET + 72,
-    BSP_IPIC_IRQ_GTM8      = BSP_IPIC_IRQ_LOWEST_OFFSET + 73,
-    BSP_IPIC_IRQ_GPIO1     = BSP_IPIC_IRQ_LOWEST_OFFSET + 74,
-    BSP_IPIC_IRQ_GPIO2     = BSP_IPIC_IRQ_LOWEST_OFFSET + 75,
-    BSP_IPIC_IRQ_DDR       = BSP_IPIC_IRQ_LOWEST_OFFSET + 76,
-    BSP_IPIC_IRQ_LBC       = BSP_IPIC_IRQ_LOWEST_OFFSET + 77,
-    BSP_IPIC_IRQ_GTM2      = BSP_IPIC_IRQ_LOWEST_OFFSET + 78,
-    BSP_IPIC_IRQ_GTM6      = BSP_IPIC_IRQ_LOWEST_OFFSET + 79,
-    BSP_IPIC_IRQ_PMC       = BSP_IPIC_IRQ_LOWEST_OFFSET + 80,
-    /* reserved irqs 81-83 */
-    BSP_IPIC_IRQ_GTM3      = BSP_IPIC_IRQ_LOWEST_OFFSET + 84,
-    BSP_IPIC_IRQ_GTM7      = BSP_IPIC_IRQ_LOWEST_OFFSET + 85,
-    /* reserved irqs 86-89 */
-    BSP_IPIC_IRQ_GTM1      = BSP_IPIC_IRQ_LOWEST_OFFSET + 90,
-    BSP_IPIC_IRQ_GTM5      = BSP_IPIC_IRQ_LOWEST_OFFSET + 91,
-    /* reserved irqs 92-127 */
-
-    BSP_IPIC_IRQ_LAST     = BSP_IPIC_IRQ_MAX_OFFSET,
-    BSP_DECREMENTER       = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0
-  } rtems_irq_symbolic_name;
-
-  extern rtems_irq_connect_data *BSP_rtems_irq_tbl;
-  void BSP_rtems_irq_mng_init(unsigned cpuId);
-
-  /* ipic.c */
-  rtems_status_code BSP_irq_handle_at_ipic(uint32_t excNum);
-  void BSP_irq_enable_at_ipic (rtems_irq_number irqnum);
-  void BSP_irq_disable_at_ipic (rtems_irq_number irqnum);
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* ASM */
-
-#endif /* GEN83XX_IRQ_IRQ_H */
Index: c/src/lib/libbsp/powerpc/gen83xx/irq/irq_init.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/irq/irq_init.c	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ 	(revision )
@@ -1,417 +1,0 @@
-/*===============================================================*\
-| Project: RTEMS generic MPC83xx BSP                              |
-+-----------------------------------------------------------------+
-|                    Copyright (c) 2007                           |
-|                    Embedded Brains GmbH                         |
-|                    Obere Lagerstr. 30                           |
-|                    D-82178 Puchheim                             |
-|                    Germany                                      |
-|                    rtems@embedded-brains.de                     |
-+-----------------------------------------------------------------+
-| The license and distribution terms for this file may be         |
-| found in the file LICENSE in this distribution or at            |
-|                                                                 |
-| http://www.rtems.com/license/LICENSE.                           |
-|                                                                 |
-+-----------------------------------------------------------------+
-| this file contains the irq controller init code                 |
-+-----------------------------------------------------------------+
-| derived from the virtex BSP                                     |
-\*===============================================================*/
-#include <libcpu/spr.h>
-#include <bsp/irq.h>
-#include <bsp.h>
-#include <libcpu/raw_exception.h>
-#include <rtems/bspIo.h>
-#include <rtems/powerpc/powerpc.h>
-#include <rtems/score/apiext.h>
-#include <bsp/vectors.h>
-
-
-static rtems_irq_connect_data rtemsIrqTbl[BSP_IRQ_NUMBER];
-rtems_irq_connect_data *BSP_rtems_irq_tbl;
-rtems_irq_global_settings* BSP_rtems_irq_config;
-
-/***********************************************************
- * dummy functions for on/off/isOn calls
- * these functions just do nothing fulfill the semantic
- * requirements to enable/disable a certain interrupt or exception
- */
-void BSP_irq_nop_func(const rtems_irq_connect_data *unused)
-{
-  /*
-   * nothing to do
-   */
-}
-
-void BSP_irq_nop_hdl(void *hdl)
-{
-  /*
-   * nothing to do
-   */
-}
-
-int BSP_irq_true_func(const rtems_irq_connect_data *unused)
-{
-  /*
-   * nothing to do
-   */
-  return TRUE;
-}
-
-/***********************************************************
- * interrupt handler and its enable/disable functions
- ***********************************************************/
-
-/***********************************************************
- * functions to enable/disable/query external/critical interrupts
- */
-void BSP_irqexc_on_fnc(rtems_irq_connect_data *conn_data)
-{
-  uint32_t msr_value;
-  /*
-   * get current MSR value
-   */
-  _CPU_MSR_GET(msr_value);
-
-
-   msr_value |= PPC_MSR_EE;
-   _CPU_MSR_SET(msr_value);
-}
-
-void BSP_irqexc_off_fnc(rtems_irq_connect_data *unused)
-{
-  /*
-   * nothing to do
-   */
-}
-
-/***********************************************************
- * High level IRQ handler called from shared_raw_irq_code_entry
- */
-int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
-{
-  uint32_t msr_value,new_msr;
-
-  /*
-   * Handle interrupt
-   */
-  switch(excNum) {
-  case ASM_DEC_VECTOR:
-    _CPU_MSR_GET(msr_value);
-    new_msr = msr_value | MSR_EE;
-    _CPU_MSR_SET(new_msr);
-    
-    BSP_rtems_irq_tbl[BSP_DECREMENTER].hdl
-      (BSP_rtems_irq_tbl[BSP_DECREMENTER].handle);
-    
-    _CPU_MSR_SET(msr_value);
-    
-    break;
-#if 0 /* Critical interrupts not yet supported */
-  case ASM_BOOKE_CRIT_VECTOR:
-#endif
-  case ASM_60X_SYSMGMT_VECTOR:
-  case ASM_EXT_VECTOR:
-    BSP_irq_handle_at_ipic(excNum);
-    break;
-  }
-  return 0;
-}
-  
-void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
-{
-  /*
-   * Process pending signals that have not already been
-   * processed by _Thread_Displatch. This happens quite
-   * unfrequently : the ISR must have posted an action
-   * to the current running thread.
-   */
-  if ( _Thread_Do_post_task_switch_extension ||
-       _Thread_Executing->do_post_task_switch_extension ) {
-    _Thread_Executing->do_post_task_switch_extension = FALSE;
-    _API_extensions_Run_postswitch();
-  }
-}
-
-/***********************************************************
- * functions to set/get/remove interrupt handlers
- ***********************************************************/
-int BSP_install_rtems_irq_handler  (const rtems_irq_connect_data* irq)
-{
-  rtems_interrupt_level level;
-
-  /*
-   * check for valid irq name
-   * if invalid, print error and return 0
-   */
-  if (!BSP_IS_VALID_IRQ(irq->name)) {
-    printk("Invalid interrupt vector %d\n",irq->name);
-    return 0;
-  }
-
-  /*
-   * disable interrupts
-   */
-  rtems_interrupt_disable(level);
-  /*
-   * check, that default handler is installed now
-   */
-  if (rtemsIrqTbl[irq->name].hdl != BSP_rtems_irq_config->defaultEntry.hdl) {
-    rtems_interrupt_enable(level);
-    printk("IRQ vector %d already connected\n",irq->name);
-    return 0;
-  }
-  /*
-   * store new handler data
-   */
-  rtemsIrqTbl[irq->name] = *irq;
-
-  /*
-   * enable irq at interrupt controller
-   */
-  if (BSP_IS_IPIC_IRQ(irq->name)) {
-    BSP_irq_enable_at_ipic(irq->name);
-  }
-  /*
-   * call "on" function to enable interrupt at device
-   */
-  irq->on(irq);
-  /*
-   * reenable interrupts
-   */
-  rtems_interrupt_enable(level);
-
-  return 1;
-}
-
-int BSP_get_current_rtems_irq_handler	(rtems_irq_connect_data* irq)
-{
-  rtems_interrupt_level level;
-  
-  /*
-   * check for valid IRQ name
-   */
-  if (!BSP_IS_VALID_IRQ(irq->name)) {
-    return 0;
-  }
-  rtems_interrupt_disable(level);
-  /*
-   * return current IRQ entry
-   */
-  *irq = rtemsIrqTbl[irq->name];
-  rtems_interrupt_enable(level);
-  return 1;
-}
-
-int BSP_remove_rtems_irq_handler  (const rtems_irq_connect_data* irq)
-{
-  rtems_interrupt_level level;
-  
-  /*
-   * check for valid IRQ name
-   */
-  if (!BSP_IS_VALID_IRQ(irq->name)) {
-    return 0;
-  }
-  rtems_interrupt_disable(level);
-  /*
-   * check, that specified handler is really connected now
-   */
-  if (rtemsIrqTbl[irq->name].hdl != irq->hdl) {
-    rtems_interrupt_enable(level);
-    return 0;
-  }
-  /*
-   * disable interrupt at interrupt controller
-   */
-  if (BSP_IS_IPIC_IRQ(irq->name)) {
-    BSP_irq_disable_at_ipic(irq->name);
-  }
-  /*
-   * disable interrupt at source
-   */
-  irq->off(irq);
-  /*
-   * restore default interrupt handler
-   */
-  rtemsIrqTbl[irq->name] = BSP_rtems_irq_config->defaultEntry;
-
-  /*
-   * reenable interrupts
-   */
-  rtems_interrupt_enable(level);
-
-  return 1;
-}
-
-/***********************************************************
- * functions to set/get the basic interrupt management setup
- ***********************************************************/
-/*
- * (Re) get info on current RTEMS interrupt management.
- */
-int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** ret_ptr)
-{
-  *ret_ptr = BSP_rtems_irq_config;
-  return 0;
-}
-
-
-/*
- * set management stuff
- */
-int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
-{
-  int                    i;
-  rtems_interrupt_level  level;
-
-  rtems_interrupt_disable(level);
-  /*
-   * store given configuration
-   */
-  BSP_rtems_irq_config = config;
-  BSP_rtems_irq_tbl    = BSP_rtems_irq_config->irqHdlTbl;
-  /*
-   * enable any non-empty IRQ entries at OPBINTC
-   */
-  for (i =  BSP_IPIC_IRQ_LOWEST_OFFSET;
-       i <= BSP_IPIC_IRQ_MAX_OFFSET;
-       i++) {
-    if (BSP_rtems_irq_tbl[i].hdl != config->defaultEntry.hdl) {
-      BSP_irq_enable_at_ipic(i);
-      BSP_rtems_irq_tbl[i].on((&BSP_rtems_irq_tbl[i]));
-    }
-    else {
-      BSP_rtems_irq_tbl[i].off(&(BSP_rtems_irq_tbl[i]));
-      BSP_irq_disable_at_ipic(i);
-    }
-  }
-  /*
-   * store any irq-like processor exceptions
-   */
-  for (i = BSP_PROCESSOR_IRQ_LOWEST_OFFSET; 
-       i < BSP_PROCESSOR_IRQ_MAX_OFFSET;
-       i++) {
-    if (BSP_rtems_irq_tbl[i].hdl != config->defaultEntry.hdl) {
-      if (BSP_rtems_irq_tbl[i].on != NULL) {
-	BSP_rtems_irq_tbl[i].on
-	  (&(BSP_rtems_irq_tbl[i]));
-      }
-    }
-    else {
-      if (BSP_rtems_irq_tbl[i].off != NULL) {
-	BSP_rtems_irq_tbl[i].off
-	  (&(BSP_rtems_irq_tbl[i]));
-      }
-    }
-  }
-  rtems_interrupt_enable(level);
-  return 1;
-}
-/**********************************************
- * list of exception vectors to tap for interrupt handlers
- */
-static rtems_raw_except_connect_data BSP_vec_desc[] = {
-#if defined(ASM_DEC_VECTOR) 
-  {ASM_DEC_VECTOR,
-   {ASM_DEC_VECTOR,
-    decrementer_exception_vector_prolog_code,
-    (size_t)decrementer_exception_vector_prolog_code_size
-   },
-   exception_nop_enable,
-   exception_nop_enable,
-   exception_always_enabled
-  },
-#endif
-#if defined(ASM_60X_SYSMGMT_VECTOR) 
-  {ASM_60X_SYSMGMT_VECTOR,
-   {ASM_60X_SYSMGMT_VECTOR,
-    sysmgmt_exception_vector_prolog_code,
-    (size_t)sysmgmt_exception_vector_prolog_code_size
-   },
-   exception_nop_enable,
-   exception_nop_enable,
-   exception_always_enabled
-  },
-#endif
-  {ASM_EXT_VECTOR,
-   {ASM_EXT_VECTOR,
-    external_exception_vector_prolog_code,
-    (size_t)&external_exception_vector_prolog_code_size
-   },
-   exception_nop_enable,
-   exception_nop_enable,
-   exception_always_enabled
-  }
-#if 0 /* Critical interrupts not yet supported */
-  ,{ASM_BOOKE_CRIT_VECTOR,
-   {ASM_BOOKE_CRIT_VECTOR,
-    critical_exception_vector_prolog_code,
-    critical_exception_vector_prolog_code_size
-   }
-   BSP_irq_nop_func,
-   BSP_irq_nop_func,
-   BSP_irq_true_func
-  }
-#endif
-};
-
-/*
- * dummy for an empty IRQ handler entry
- */ 
-static rtems_irq_connect_data emptyIrq = {
-  0, 		         /* Irq Name                 */
-  BSP_irq_nop_hdl,       /* handler function         */
-  NULL,                  /* handle passed to handler */
-  BSP_irq_nop_func,      /* on function              */
-  BSP_irq_nop_func,      /* off function             */
-  BSP_irq_true_func      /* isOn function            */
-};
-
-static rtems_irq_global_settings initialConfig = {
-  BSP_IRQ_NUMBER,    /* irqNb */
-  {  0, 		         /* Irq Name                 */
-     BSP_irq_nop_hdl,       /* handler function         */
-     NULL,                  /* handle passed to handler */
-     BSP_irq_nop_func,      /* on function              */
-     BSP_irq_nop_func,      /* off function             */
-     BSP_irq_true_func      /* isOn function            */
-  }, /* emptyIrq */
-  rtemsIrqTbl, /* irqHdlTbl  */
-  0,           /* irqBase    */
-  NULL         /* irqPrioTbl */
-};
-
-void BSP_rtems_irq_mng_init(unsigned cpuId)
-{
-  int i;
-  /*
-   * connect all exception vectors needed
-   */
-  for (i = 0;
-       i < (sizeof(BSP_vec_desc) / 
-	    sizeof(BSP_vec_desc[0]));
-       i++) {
-    if (!ppc_set_exception (&BSP_vec_desc[i])) {
-      BSP_panic("Unable to initialize RTEMS raw exception\n");
-    }
-  }
-  /*
-   * setup interrupt handlers table
-   */
-  for (i = 0;
-       i < BSP_IRQ_NUMBER;
-       i++) {
-    rtemsIrqTbl[i]      = emptyIrq;
-    rtemsIrqTbl[i].name = i;
-  }
-
-  /*
-   * initialize interrupt management
-   */
-  if (!BSP_rtems_irq_mngt_set(&initialConfig)) {
-    BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n");
-  }  
-}
-
Index: c/src/lib/libbsp/powerpc/gen83xx/network/network.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/network/network.c	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ c/src/lib/libbsp/powerpc/gen83xx/network/network.c	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -30,10 +30,20 @@
 #define TSEC_IFMODE_GMII  1
 
-#if defined(MPC8349EAMDS)
+#if defined( MPC8313ERDB)
+
 #define TSEC_IFMODE TSEC_IFMODE_RGMII
-#endif
 
-#if defined(HSC_CM01)
+#elif defined( MPC8349EAMDS)
+
 #define TSEC_IFMODE TSEC_IFMODE_RGMII
+
+#elif defined( HSC_CM01)
+
+#define TSEC_IFMODE TSEC_IFMODE_RGMII
+
+#else
+
+#warning No TSEC configuration available
+
 #endif
 
@@ -57,5 +67,4 @@
 \*=========================================================================*/
 {
-  char hw_addr[6] = {0x00,0x04,0x9F,0x00,0x2f,0xcb};
   int    unitNumber;
   char   *unitName;
@@ -101,5 +110,42 @@
    */
   if (config->hardware_address == NULL) {
+
+#ifdef HAS_UBOOT
+
+    switch (unitNumber) {
+      case 1:
+        config->hardware_address = mpc83xx_uboot_board_info.bi_enetaddr;
+        break;
+
+#ifdef CONFIG_HAS_ETH1
+      case 2:
+        config->hardware_address = mpc83xx_uboot_board_info.bi_enet1addr;
+        break;
+#endif /* CONFIG_HAS_ETH1 */
+
+#ifdef CONFIG_HAS_ETH2
+      case 3:
+        config->hardware_address = mpc83xx_uboot_board_info.bi_enet2addr;
+        break;
+#endif /* CONFIG_HAS_ETH2 */
+
+#ifdef CONFIG_HAS_ETH3
+      case 4:
+        config->hardware_address = mpc83xx_uboot_board_info.bi_enet3addr;
+        break;
+#endif /* CONFIG_HAS_ETH3 */
+
+      default:
+        return 0;
+    }
+
+#else /* HAS_UBOOT */
+
+    char hw_addr [6] = { 0x00, 0x04, 0x9f, 0x00, 0x2f, 0xcb};
+
     config->hardware_address = hw_addr;
+
+#endif /* HAS_UBOOT */
+
   }
   /*
Index: c/src/lib/libbsp/powerpc/gen83xx/preinstall.am
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/preinstall.am	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ c/src/lib/libbsp/powerpc/gen83xx/preinstall.am	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -41,4 +41,9 @@
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
 
+../../../libcpu/@RTEMS_CPU@/$(dirstamp):
+	@$(MKDIR_P) ../../../libcpu/@RTEMS_CPU@
+	@: > ../../../libcpu/@RTEMS_CPU@/$(dirstamp)
+PREINSTALL_DIRS += ../../../libcpu/@RTEMS_CPU@/$(dirstamp)
+
 $(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
@@ -66,7 +71,11 @@
 TMPINSTALL_FILES += $(PROJECT_LIB)/rtems_crti.$(OBJEXT)
 
-$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
-PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds
+$(PROJECT_LIB)/linkcmds.base: startup/linkcmds.base $(PROJECT_LIB)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.base
+PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.base
+
+$(PROJECT_LIB)/linkcmds.mpc8313erdb: startup/linkcmds.mpc8313erdb $(PROJECT_LIB)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.mpc8313erdb
+PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.mpc8313erdb
 
 $(PROJECT_LIB)/linkcmds.mpc8349eamds: startup/linkcmds.mpc8349eamds $(PROJECT_LIB)/$(dirstamp)
@@ -78,14 +87,26 @@
 PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.hsc_cm01
 
-$(PROJECT_INCLUDE)/bsp/irq.h: ./irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
 
-$(PROJECT_INCLUDE)/bsp/hwreg_vals.h: ./include/hwreg_vals.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+$(PROJECT_INCLUDE)/bsp/irq-config.h: include/irq-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-config.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-config.h
+
+$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
+
+$(PROJECT_INCLUDE)/bsp/hwreg_vals.h: include/hwreg_vals.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/hwreg_vals.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/hwreg_vals.h
 
-$(PROJECT_INCLUDE)/bsp/vectors.h: ../../powerpc/shared/vectors/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h
+$(PROJECT_INCLUDE)/bsp/u-boot.h: ../shared/include/u-boot.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/u-boot.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/u-boot.h
 
+$(PROJECT_INCLUDE)/bsp/tictac.h: ../shared/include/tictac.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tictac.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tictac.h
+
Index: c/src/lib/libbsp/powerpc/gen83xx/spi/spi_init.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/spi/spi_init.c	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ c/src/lib/libbsp/powerpc/gen83xx/spi/spi_init.c	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -21,9 +21,21 @@
 #include <bsp/irq.h>
 #include <bsp.h>
-#if defined(MPC8349EAMDS)
+
+#if defined( MPC8313ERDB)
+
+#include <libchip/spi-sd-card.h>
+
+#elif defined( MPC8349EAMDS)
+
 #include <libchip/spi-flash-m25p40.h>
-#endif
-#if defined(HSC_CM01)
+
+#elif defined( HSC_CM01)
+
 #include <libchip/spi-fram-fm25l256.h>
+
+#else
+
+#warning No SPI configuration available
+
 #endif
 
@@ -52,5 +64,17 @@
 \*=========================================================================*/
 {
-#if defined(MPC8349EAMDS)
+
+#if defined( MPC8313ERDB)
+
+  /* Check address */
+  if (addr > 0) {
+    return RTEMS_INVALID_NUMBER;
+  }
+
+  /* SCS (active low) */
+  mpc83xx.gpio [0].gpdat &= ~0x20000000;
+
+#elif defined( MPC8349EAMDS)
+
   /*
    * check device address for valid range
@@ -65,6 +89,7 @@
    */
   mpc83xx.gpio[0].gpdat &= ~(1 << (31- 0));
-#endif
-#if defined(HSC_CM01)
+
+#elif defined( HSC_CM01)
+
   /*
    * check device address for valid range
@@ -89,5 +114,7 @@
    */
   mpc83xx.gpio[0].gpdat |= (1 << (31- 27));
-#endif
+
+#endif
+
   return  RTEMS_SUCCESSFUL;
 }
@@ -111,5 +138,12 @@
 \*=========================================================================*/
 {
-#if defined(MPC8349EAMDS)
+
+#if defined( MPC8313ERDB)
+
+  /* SCS (inactive high) */
+  mpc83xx.gpio [0].gpdat |= 0x20000000;
+
+#elif defined( MPC8349EAMDS)
+
   /*
    * GPIO1[0] is nSEL_SPI for M25P40
@@ -117,6 +151,7 @@
    */
   mpc83xx.gpio[0].gpdat |=  (1 << (31- 0));
-#endif
-#if defined(HSC_CM01)
+
+#elif defined( HSC_CM01)
+
   /*
    * GPIO1[27] is high-active strobe 
@@ -124,5 +159,7 @@
    */
   mpc83xx.gpio[0].gpdat &= ~(0x1 << (31-27));
-#endif
+
+#endif
+
   return 0;
 }
@@ -149,5 +186,12 @@
   printk("bsp_spi_send_stop called... ");
 #endif
-#if defined(MPC8349EAMDS)
+
+#if defined( MPC8313ERDB)
+
+  /* SCS (inactive high) */
+  mpc83xx.gpio [0].gpdat |= 0x20000000;
+
+#elif defined( MPC8349EAMDS)
+
   /*
    * deselect given device
@@ -156,6 +200,7 @@
    */
   mpc83xx.gpio[0].gpdat |=  (1 << (31- 0));
-#endif
-#if defined(HSC_CM01)
+
+#elif defined( HSC_CM01)
+
   /*
    * deselect device
@@ -163,5 +208,7 @@
    */
   mpc83xx.gpio[0].gpdat &= ~(1 << (31- 27));
-#endif
+
+#endif
+
 #if defined(DEBUG)
   printk("... exit OK\r\n");
@@ -175,25 +222,55 @@
 
 rtems_libi2c_bus_ops_t bsp_spi_ops = {
-  init:             mpc83xx_spi_init,
-  send_start:       bsp_spi_send_start_dummy,
-  send_stop:        bsp_spi_send_stop,
-  send_addr:        bsp_spi_sel_addr,
-  read_bytes:       mpc83xx_spi_read_bytes,
-  write_bytes:      mpc83xx_spi_write_bytes,
-  ioctl:            mpc83xx_spi_ioctl
+  .init = mpc83xx_spi_init,
+  .send_start = bsp_spi_send_start_dummy,
+  .send_stop = bsp_spi_send_stop,
+  .send_addr = bsp_spi_sel_addr,
+  .read_bytes = mpc83xx_spi_read_bytes,
+  .write_bytes = mpc83xx_spi_write_bytes,
+  .ioctl = mpc83xx_spi_ioctl
 };
 
 static mpc83xx_spi_desc_t bsp_spi_bus_desc = {
   {/* public fields */
-    ops:	&bsp_spi_ops,
-    size:	sizeof(bsp_spi_bus_desc),
+    .ops = &bsp_spi_ops,
+    .size = sizeof(bsp_spi_bus_desc)
   },
   { /* our private fields */
-    reg_ptr:	 &mpc83xx.spi,
-    initialized: FALSE,
-    irq_number:  BSP_IPIC_IRQ_SPI,
-    base_frq  :  0 /* filled in during init */
+    .reg_ptr =&mpc83xx.spi,
+    .initialized = FALSE,
+    .irq_number = BSP_IPIC_IRQ_SPI,
+    .base_frq = 0 /* filled in during init */
   }
 };
+
+#ifdef MPC8313ERDB
+
+#include <libchip/spi-sd-card.h>
+
+sd_card_driver_entry sd_card_driver_table [1] = { {
+                .driver = {
+                        .ops = &sd_card_driver_ops,
+                        .size = sizeof( sd_card_driver_entry)
+                },
+                .table_index = 0,
+                .minor = 0,
+                .device_name = "sd-card-a",
+                .disk_device_name = "/dev/sd-card-a",
+                .transfer_mode = SD_CARD_TRANSFER_MODE_DEFAULT,
+                .command = SD_CARD_COMMAND_DEFAULT,
+                /* .response = whatever, */
+                .response_index = SD_CARD_COMMAND_SIZE,
+                .n_ac_max = SD_CARD_N_AC_MAX_DEFAULT,
+                .block_number = 0,
+                .block_size = 0,
+                .block_size_shift = 0,
+                .busy = 1,
+                .verbose = 1,
+                .schedule_if_busy = 0
+        }
+};
+
+#endif /* MPC8313ERDB */
+
 
 /*=========================================================================*\
@@ -230,5 +307,31 @@
    * init port pins used to address/select SPI devices
    */
-#if defined(MPC8349EAMDS)
+
+#if defined( MPC8313ERDB)
+
+  /*
+   * Configured as master (direct connection to SD card)
+   *
+   * GPIO[28] : SOUT
+   * GPIO[29] : SIN
+   * GPIO[30] : SCLK
+   * GPIO[02] : SCS (inactive high), GPIO[02] is normally connected to U43 at
+   * pin 15 of MC74LCX244DT.
+   */
+
+  /* Function */
+  mpc83xx.syscon.sicrl = (mpc83xx.syscon.sicrl & ~0x03fc0000) | 0x30000000;
+
+  /* Direction */
+  mpc83xx.gpio [0].gpdir = (mpc83xx.gpio [0].gpdir & ~0x0000000f) | 0x2000000b;
+
+  /* Data */
+  mpc83xx.gpio [0].gpdat |= 0x20000000;
+
+  /* Open Drain */
+  /* mpc83xx.gpio [0].gpdr  |= 0x0000000f; */
+
+#elif defined( MPC8349EAMDS)
+
   /*
    * GPIO1[0] is nSEL_SPI for M25P40
@@ -238,6 +341,7 @@
   mpc83xx.gpio[0].gpdir |=  (1 << (31- 0));
   mpc83xx.gpio[0].gpdr  &= ~(1 << (31- 0));
-#endif
-#if defined(HSC_CM01)
+
+#elif defined( HSC_CM01)
+
   /*
    * GPIO1[24] is SPI_A0
@@ -250,5 +354,7 @@
   mpc83xx.gpio[0].gpdir |=  (0xf << (31-27));
   mpc83xx.gpio[0].gpdr  &= ~(0xf << (31-27));
-#endif
+
+#endif
+
   /*
    * update base frequency in spi descriptor
@@ -265,5 +371,17 @@
   }
   spi_busno = ret_code;
-#if defined(MPC8349EAMDS)
+
+#if defined( MPC8313ERDB)
+
+  /* Register SD Card driver */
+  ret_code = rtems_libi2c_register_drv(
+    sd_card_driver_table [0].device_name,
+    (rtems_libi2c_drv_t *) &sd_card_driver_table [0],
+    spi_busno,
+    0
+  );
+
+#elif defined( MPC8349EAMDS)
+
   /*
    * register M25P40 Flash
@@ -272,9 +390,6 @@
 				       spi_flash_m25p40_rw_driver_descriptor,
 				       spi_busno,0x00);
-  if (ret_code < 0) {
-    return -ret_code;
-  }
-#endif
-#if defined(HSC_CM01)
+#elif defined(HSC_CM01)
+
   /*
    * register FM25L256 FRAM
@@ -283,8 +398,11 @@
 				       spi_fram_fm25l256_rw_driver_descriptor,
 				       spi_busno,0x02);
+
+#endif
+
   if (ret_code < 0) {
     return -ret_code;
   }
-#endif
+
   /*
    * FIXME: further drivers, when available
Index: c/src/lib/libbsp/powerpc/gen83xx/start/start.S
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/start/start.S	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ c/src/lib/libbsp/powerpc/gen83xx/start/start.S	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -19,27 +19,8 @@
 /* $Id$ */   
 
-#include <rtems/asm.h> 
+#include <libcpu/powerpc-utility.h> 
 #include <rtems/powerpc/cache.h>
-#include <rtems/powerpc/registers.h>
+#include <bsp.h>
 #include <mpc83xx/mpc83xx.h>
-#include <bsp.h>
-
-/* Macro definitions to load a register with a 32-bit address.
-   Both functions identically.  Sometimes one mnemonic is more
-   appropriate than the other.
-   reg 		-> register to load
-   value 	-> value to be loaded
-   LA  reg,value    ("Load Address")
-   LWI reg,value    ("Load Word Immediate") */
-
-.macro LA reg, value
-	lis \reg , \value@h
-	ori \reg , \reg, \value@l
-.endm
-
-.macro LWI reg, value
-	lis \reg , (\value)@h
-	ori \reg , \reg, (\value)@l
-.endm 
 
 .macro SET_IMM_REGW base, reg2, offset, value
@@ -48,41 +29,8 @@
 .endm 
 
-/* Macro definitions to test, set or clear a single 
-   bit or bit pattern in a given 32bit GPR. 
-   reg1		-> register content to be tested
-   reg2		-> 2nd register only needed for computation
-   mask		-> any bit pattern */
-
-.macro	TSTBITS	reg1, reg2, reg3, mask	/* Match is indicated by EQ=0 (CR) */ 
-	LWI 	\reg3, \mask		/* Unmatch is indicated by EQ=1 (CR) */
-	and	\reg1, \reg1, \reg3
-	and	\reg2, \reg2, \reg3
-	cmplw	\reg1, \reg2
-	sync
-.endm	
-	
-.macro 	SETBITS reg1, reg2, mask
-	LWI 	\reg2, \mask
-	or	\reg1, \reg1, \reg2 
-	sync
-.endm
-
-.macro 	CLRBITS reg1, reg2, mask
-	LWI 	\reg2, \mask
-	andc	\reg1, \reg1, \reg2
-	sync
-.endm
-
 #define REP8(l) l ; l; l; l; l; l; l; l;
 
-.extern	_bss_start
-.extern	_bss_size
-.extern	_data_start
-.extern	_data_size
-.extern	_text_start
-.extern	_text_size
-/*.extern _s_got*/
 .extern boot_card
-.extern MBAR   
+.extern MBAR
 
 #if defined(RESET_CONF_WRD_L)
@@ -109,4 +57,30 @@
 PUBLIC_VAR (start)
 start:
+
+#ifdef HAS_UBOOT
+
+.extern mpc83xx_uboot_board_info
+.extern mpc83xx_uboot_board_info_size
+
+	/* Reset time base */
+	li	r0, 0
+	mtspr	TBWU, r0
+	mtspr	TBWL, r0
+
+	/* Copy board info */
+	LA	r6, mpc83xx_uboot_board_info
+	LW	r5, mpc83xx_uboot_board_info_size
+        mtctr   r5
+
+copy_uboot_board_info:
+
+	lwz     r5, 0(r3)
+        addi    r3, r3, 4
+        stw     r5, 0(r6)
+        addi    r6, r6, 4
+        bdnz    copy_uboot_board_info
+
+#endif /* HAS_UBOOT */
+
 	/*
 	 * basic CPU setup:	
@@ -117,4 +91,5 @@
 	CLRBITS r30, r29, MSR_IP|MSR_EE
 	mtmsr	r30 				/* Set RI/ME, Clr EE in MSR */
+
 	b start_rom_skip
 	
@@ -166,5 +141,5 @@
 	 * ROM startup: jump to code final ROM location
 	 */
-	LA	r20, ROM_START /* ROM-RAM reloc in r20 */
+	LA	r20, bsp_rom_start /* ROM-RAM reloc in r20 */
 	LA	r29, start_code_in_rom /* get compile time addr of label */
 	add	r29,r20,r29    /* compute exec address */
@@ -381,10 +356,10 @@
 	 */
 	/* get start address of text section in RAM */
-	LA	r29, _text_start  
+	LA	r29, bsp_section_text_start  
 	/* get start address of text section in ROM (add reloc offset) */
 	add	r30, r20, r29    
 	/* get size of startup code */
 	LA	r28, end_reloc_startup
-	LA	r31, _text_start
+	LA	r31, bsp_section_text_start
 	sub	28,r28,r31
 	/* copy startup code from ROM to RAM location */
@@ -410,6 +385,6 @@
 	add	r30, r20, r29    
 	/* get size of rest of code */
-	LA	r28, _text_start
-	LA	r31, _text_size
+	LA	r28, bsp_section_text_start
+	LA	r31, bsp_section_text_size
 	add	r28,r28,r31
 	sub	r28,r28,r29
@@ -420,9 +395,9 @@
 	 */
 	/* get start address of data section in RAM */
-	LA	r29, _data_start 
+	LA	r29, bsp_section_data_start 
 	/* get start address of data section in ROM (add reloc offset) */
 	add	r30, r20, r29    
 	/* get size of RAM image */
-	LA	r28, _data_size  
+	LA	r28, bsp_section_data_size  
 	/* copy initialized data section from ROM to RAM location */
 	bl	copy_image       
@@ -433,13 +408,30 @@
 	 * ROM/RAM startup: clear bss in SDRAM
 	 */
-	LWI	r30, _bss_start  /* get start address of bss section */
-        LWI	r29, _bss_size   /* get size of bss section */
-        bl      clr_mem          /* Clear the bss section */
+	LA	r3, bsp_section_bss_start  /* get start address of bss section */
+	LWI	r4, bsp_section_bss_size   /* get size of bss section */
+	bl	mpc83xx_zero_4          /* Clear the bss section */
 	/*
 	 * call boot_card
 	 */
-/* set stack pointer (common for RAM/ROM startup) */
-	LA	r1, _text_start  
+
+	/* Set stack pointer (common for RAM/ROM startup) */
+	LA	r1, bsp_section_text_start  
         addi    r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */     
+
+	/* Create NULL */
+	li r0, 0
+
+	/* Return address */
+	stw r0, 4(r1)
+
+	/* Back chain */
+	stw r0, 0(r1)
+
+	/* Read-only small data */
+	LA r2, _SDA2_BASE_
+
+	/* Read-write small data */
+	LA r13, _SDA_BASE_
+
 /* clear arguments and do further init. in C (common for RAM/ROM startup) */
         xor     r3, r3, r3
@@ -487,32 +479,57 @@
 	blr
 
-clr_mem:
-	mr 	r28, r29		
-	srwi	r29, r29, 2
-        mtctr   r29				/* set ctr reg */
-        
-        
-        slwi	r29, r29, 2
-        sub     r28, r28, r29			/* maybe some residual bytes */
-        xor     r29, r29, r29		
-	
-	
-clr_mem_word:
-        stswi   r29, r30, 0x04			/* store r29 (word) to r30 memory location */
-        addi    r30, r30, 0x04			/* increment r30 */
-        
-        bdnz    clr_mem_word			/* dec counter and loop */
-	
-	
-	cmpwi	r28, 0x00			/* clear mem. finished ? */
-	beq	clr_mem_end;
-        mtctr   r28				/* reload counter for residual bytes */
-clr_mem_byte:
-	stswi   r29, r30, 0x01			/* store r29 (byte) to r30 memory location  */
-	addi    r30, r30, 0x01			/* update r30 */
-        
-        bdnz    clr_mem_byte			/* dec counter and loop */
-        
-clr_mem_end:
-        blr					/* return */
+	
+/**
+ * @fn int mpc83xx_zero_4( void *dest, size_t n)
+ *
+ * @brief Zero all @a n bytes starting at @a dest with 4 byte writes.
+ *
+ * The address @a dest has to be aligned on 4 byte boundaries.  The size @a n
+ * must be evenly divisible by 4.
+ */
+GLOBAL_FUNCTION mpc83xx_zero_4
+	/* Create zero */
+	xor	r0, r0, r0
+
+	/* Set offset */
+	xor	r5, r5, r5
+
+	/* Loop counter for the first bytes up to 16 bytes */
+	rlwinm.	r9, r4, 30, 30, 31
+	beq	mpc83xx_zero_4_more
+	mtctr	r9
+
+mpc83xx_zero_4_head:
+
+	stwx	r0, r3, r5
+	addi	r5, r5, 8
+	bdnz	mpc83xx_zero_4_head
+
+mpc83xx_zero_4_more:
+
+	/* More than 16 bytes? */
+	srwi.	r9, r4, 4
+	beqlr
+	mtctr	r9
+
+	/* Set offsets */
+	addi	r6, r5, 4
+	addi	r7, r5, 8
+	addi	r8, r5, 12
+
+mpc83xx_zero_4_tail:
+
+	stwx	r0, r3, r5
+	addi	r5, r5, 16
+	stwx	r0, r3, r6
+	addi	r6, r6, 16
+	stwx	r0, r3, r7
+	addi	r7, r7, 16
+	stwx	r0, r3, r8
+	addi	r8, r8, 16
+	bdnz	mpc83xx_zero_4_tail
+	
+	/* Return */
+	blr
+
 end_reloc_startup:
Index: c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -1,59 +1,56 @@
-/*===============================================================*\
-| Project: RTEMS generic MPC83xx BSP                              |
-+-----------------------------------------------------------------+
-|                    Copyright (c) 2007                           |
-|                    Embedded Brains GmbH                         |
-|                    Obere Lagerstr. 30                           |
-|                    D-82178 Puchheim                             |
-|                    Germany                                      |
-|                    rtems@embedded-brains.de                     |
-+-----------------------------------------------------------------+
-| The license and distribution terms for this file may be         |
-| found in the file LICENSE in this distribution or at            |
-|                                                                 |
-| http://www.rtems.com/license/LICENSE.                           |
-|                                                                 |
-+-----------------------------------------------------------------+
-| this file contains the BSP startup code                         |
-\*===============================================================*/
+/**
+ * @file
+ *
+ * @ingroup mpc83xx
+ *
+ * @brief Source for BSP startup code.
+ */
 
 /*
- *  $Id$
- */
-
-#include <bsp.h>
+ * Copyright (c) 2008
+ * Embedded Brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * rtems@embedded-brains.de
+ *
+ * The license and distribution terms for this file may be found in the file
+ * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
+ *
+ * $Id$
+ */
+
+#include <string.h>
 
 #include <rtems/libio.h>
 #include <rtems/libcsupport.h>
-#include <rtems/powerpc/powerpc.h>
 #include <rtems/score/thread.h>
 
-#include <rtems/bspIo.h>
-#include <libcpu/cpuIdent.h>
-#include <libcpu/spr.h>
-#include <bsp/irq.h>
-
-#include <string.h>
-
-SPR_RW(SPRG0)
-SPR_RW(SPRG1)
-
-extern unsigned long intrStackPtr;
+#include <libcpu/powerpc-utility.h>
+
+#include <bsp.h>
+#include <bsp/irq-generic.h>
+#include <bsp/ppc_exc_bspsupp.h>
+
+#ifdef HAS_UBOOT
+
+/*
+ * We want this in the data section, because the startup code clears the BSS
+ * section after the initialization of the board info.
+ */
+bd_t mpc83xx_uboot_board_info = { .bi_baudrate = 123 };
+
+/* Size in words */
+const size_t mpc83xx_uboot_board_info_size = (sizeof( bd_t) + 3) / 4;
+
+#endif /* HAS_UBOOT */
+
+/* Configuration parameters for console driver, ... */
+unsigned int BSP_bus_frequency;
+
+/* Configuration parameters for clock driver, ... */
+uint32_t bsp_clicks_per_usec;
+
 static char *BSP_heap_start, *BSP_heap_end;
-
-/*
- * constants for c_clock driver:
- * system bus frequency (for timebase etc)
- * and 
- * Time base divisior: scaling value:
- * BSP_time_base_divisor = TB ticks per millisecond/BSP_bus_frequency
- */
-unsigned int BSP_bus_frequency;
-unsigned int BSP_time_base_divisor = 4000;  /* 4 bus clicks per TB click */
-
-/*
- *  Driver configuration parameters
- */
-uint32_t   bsp_clicks_per_usec;
 
 /*
@@ -61,183 +58,147 @@
  *  Look in rtems/c/src/lib/libbsp/shared/bsplibc.c.
  */
-void bsp_libc_init( void *, uint32_t, int );
-extern void initialize_exceptions(void);
-extern void cpu_init(void);
-
-void BSP_panic(char *s)
-  {
-  printk("%s PANIC %s\n",_RTEMS_version, s);
-  /*
-   * FIXME: hang/restart system
-   */
-  __asm__ __volatile ("sc");
-  }
-
-void _BSP_Fatal_error(unsigned int v)
-  {
-  printk("%s PANIC ERROR %x\n",_RTEMS_version, v);
-  /*
-   * FIXME: hang/restart system
-   */
-  __asm__ __volatile ("sc");
-  }
-
-/*
- *  Function:   bsp_pretasking_hook
- *  Created:    95/03/10
- *
- *  Description:
- *      BSP pretasking hook.  Called just before drivers are initialized.
- *      Used to setup libc and install any BSP extensions.
- *
- *  NOTES:
- *      Must not use libc (to do io) from here, since drivers are
- *      not yet initialized.
- *
- */
-
-void
-bsp_pretasking_hook(void)
-{
-
-  /*
-   * initialize libc including the heap
-   */
-  bsp_libc_init( BSP_heap_start, 
-		 BSP_heap_end - BSP_heap_start,
-		 0);
+extern void cpu_init( void);
+
+void BSP_panic( char *s)
+{
+	rtems_interrupt_level level;
+
+	rtems_interrupt_disable( level);
+
+	printk( "%s PANIC %s\n", _RTEMS_version, s);
+
+	while (1) {
+		/* Do nothing */
+	}
+}
+
+void _BSP_Fatal_error( unsigned n)
+{
+	rtems_interrupt_level level;
+
+	rtems_interrupt_disable( level);
+
+	printk( "%s PANIC ERROR %u\n", _RTEMS_version, n);
+
+	while (1) {
+		/* Do nothing */
+	}
+}
+
+void bsp_pretasking_hook( void)
+{
+	/* Initialize libc including the heap */
+	bsp_libc_init( BSP_heap_start, BSP_heap_end - BSP_heap_start, 0);
 }
 
 void bsp_calc_mem_layout()
 {
-  /*
-   * these labels (!) are defined in the linker command file
-   * or when the linker is invoked
-   * NOTE: the information(size) is the address of the object,
-   * not the object otself
-   */
-  extern unsigned char TopRamReserved;
-  extern unsigned char _WorkspaceBase[];
-
-  /*
-   * compute the memory layout:
-   * - first unused address is Workspace start
-   * - Heap starts at end of workspace
-   * - Heap ends at end of memory - reserved memory area
-   */
-  Configuration.work_space_start = _WorkspaceBase;
-
-  BSP_heap_start = ((char *)Configuration.work_space_start +
-                    rtems_configuration_get_work_space_size());
-
-#if defined(HAS_UBOOT)
-  BSP_heap_end = (uboot_bdinfo_ptr->bi_memstart 
-		  + uboot_bdinfo_ptr->bi_memsize
-		  - (uint32_t)&TopRamReserved);
-#else
-  BSP_heap_end = (void *)(RAM_END - (uint32_t)&TopRamReserved);
+	size_t workspace_size = rtems_configuration_get_work_space_size();
+
+	/* We clear the workspace here */
+	Configuration.do_zero_of_workspace = 0;
+	/*
+	TODO
+	mpc83xx_zero_4( bsp_workspace_start, workspace_size);
+	 */
+	mpc83xx_zero_4( bsp_interrupt_stack_start, bsp_ram_end - bsp_interrupt_stack_start);
+
+	Configuration.work_space_start = bsp_workspace_start;
+
+	BSP_heap_start = (char *) Configuration.work_space_start + workspace_size;
+
+#ifdef HAS_UBOOT
+	BSP_heap_end = mpc83xx_uboot_board_info.bi_memstart + mpc83xx_uboot_board_info.bi_memsize;
+#else /* HAS_UBOOT */
+	BSP_heap_end = bsp_ram_end;
+#endif /* HAS_UBOOT */
+}
+
+void bsp_start( void)
+{
+	ppc_cpu_id_t myCpu;
+	ppc_cpu_revision_t myCpuRevision;
+
+	uint32_t interrupt_stack_start = (uint32_t) bsp_interrupt_stack_start;
+	uint32_t interrupt_stack_size = (uint32_t) bsp_interrupt_stack_size;
+
+	/*
+	 * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
+	 * store the result in global variables so that it can be used latter...
+	 */
+	myCpu = get_ppc_cpu_type();
+	myCpuRevision = get_ppc_cpu_revision();
+
+	/* Determine heap and workspace placement */
+	bsp_calc_mem_layout();
+
+	cpu_init();
+
+	/*
+	 * This is evaluated during runtime, so it should be ok to set it
+	 * before we initialize the drivers.
+	 */
+
+	/* Initialize some device driver parameters */
+
+#ifdef HAS_UBOOT
+	BSP_bus_frequency = mpc83xx_uboot_board_info.bi_busfreq;
+#else /* HAS_UBOOT */
+	BSP_bus_frequency = BSP_CLKIN_FRQ * BSP_SYSPLL_MF / BSP_SYSPLL_CKID;
+#endif /* HAS_UBOOT */
+
+	bsp_clicks_per_usec = BSP_bus_frequency / 4000000;
+
+	/*
+	 * Enable instruction and data caches. Do not force writethrough mode.
+	 */
+
+#if INSTRUCTION_CACHE_ENABLE
+	rtems_cache_enable_instruction();
 #endif
 
-}
-
-
-void bsp_start(void)
-{
-  ppc_cpu_id_t myCpu;
-  ppc_cpu_revision_t myCpuRevision;
-  register unsigned char* intrStack;
-
-  /*
-   * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
-   * store the result in global variables so that it can be used latter...
-   */
-  myCpu 	    = get_ppc_cpu_type();
-  myCpuRevision = get_ppc_cpu_revision();
-  /*
-   * determine heap and workspace placement
-   */
-  bsp_calc_mem_layout();
-
-  cpu_init();
-
-  /*
-   * Initialize some SPRG registers related to irq handling
-   */
-
-  intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE);
-
-  _write_SPRG1((unsigned int)intrStack);
-
-  /* Signal them that this BSP has fixed PR288 - eventually, this should
-   * go away
-   */
-  _write_SPRG0(PPC_BSP_HAS_FIXED_PR288);
-
-  /*
-   * this is evaluated during runtime, so it should be ok to set it 
-   * before we initialize the drivers
-   */
-  BSP_bus_frequency   = BSP_CLKIN_FRQ * BSP_SYSPLL_MF / BSP_SYSPLL_CKID;
-  /*
-   *  initialize the device driver parameters
-   */
-  bsp_clicks_per_usec = (BSP_bus_frequency/1000000);
-
-  /*
-   * Install our own set of exception vectors
-   */
-
-  initialize_exceptions();
-
-  /*
-   * Enable instruction and data caches. Do not force writethrough mode.
-   */
-#if INSTRUCTION_CACHE_ENABLE
-  rtems_cache_enable_instruction();
+#if DATA_CACHE_ENABLE
+	rtems_cache_enable_data();
 #endif
-#if DATA_CACHE_ENABLE
-  rtems_cache_enable_data();
+
+	/* Initialize exception handler */
+	ppc_exc_initialize(
+		PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
+		interrupt_stack_start,
+		interrupt_stack_size
+	);
+
+	/* Initalize interrupt support */
+	if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) {
+		BSP_panic("Cannot intitialize interrupt support\n");
+	}
+
+#ifdef SHOW_MORE_INIT_SETTINGS
+	printk("Exit from bspstart\n");
 #endif
-
-  /*
-   *  Allocate the memory for the RTEMS Work Space.  This can come from
-   *  a variety of places: hard coded address, malloc'ed from outside
-   *  RTEMS world (e.g. simulator or primitive memory manager), or (as
-   *  typically done by stock BSPs) by subtracting the required amount
-   *  of work space from the last physical address on the CPU board.
-   */
-
-  /*
-   * Initalize RTEMS IRQ system
-   */
-  BSP_rtems_irq_mng_init(0);
-
-#ifdef SHOW_MORE_INIT_SETTINGS
-  printk("Exit from bspstart\n");
-#endif
-
-  }
-
-/*
- *
- *  _Thread_Idle_body
- *
- *  Replaces the one in c/src/exec/score/src/threadidlebody.c
- *  The MSR[POW] bit is set to put the CPU into the low power mode
- *  defined in HID0.  HID0 is set during starup in start.S.
- *
- */
-Thread _Thread_Idle_body(uint32_t ignored )
-  {
-
-  for(;;)
-    {
-
-    asm volatile("mfmsr 3; oris 3,3,4; sync; mtmsr 3; isync; ori 3,3,0; ori 3,3,0");
-
-    }
-
-  return 0;
-
-  }
-
+}
+
+/**
+ * @brief Idle thread body.
+ *
+ * Replaces the one in c/src/exec/score/src/threadidlebody.c
+ * The MSR[POW] bit is set to put the CPU into the low power mode
+ * defined in HID0.  HID0 is set during starup in start.S.
+ */
+Thread _Thread_Idle_body( uint32_t ignored)
+{
+
+	while (1) {
+		asm volatile (
+			"mfmsr 3;"
+			"oris 3, 3, 4;"
+			"sync;"
+			"mtmsr 3;"
+			"isync;"
+			"ori 3, 3, 0;"
+			"ori 3, 3, 0"
+		);
+	}
+
+	return NULL;
+}
Index: c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -156,5 +156,5 @@
    */
   GET_HID0(reg);
-  reg |=  (HID0_ICFI | HID0_DCI);
+  reg = (reg & ~(HID0_ILOCK | HID0_DLOCK)) | HID0_ICFI | HID0_DCI;
   SET_HID0(reg);
   reg &= ~(HID0_ICFI | HID0_DCI);
@@ -171,8 +171,18 @@
   SET_IBAT(6,ibat.batu,ibat.batl);
   SET_IBAT(7,ibat.batu,ibat.batl);
-
-  calc_dbat_regvals(&ibat,RAM_START,RAM_SIZE,0,0,0,0,BPP_RX);
+#ifdef HAS_UBOOT
+  calc_dbat_regvals(&ibat,mpc83xx_uboot_board_info.bi_memstart,mpc83xx_uboot_board_info.bi_memsize,0,0,0,0,BPP_RX);
+#else /* HAS_UBOOT */
+  calc_dbat_regvals(&ibat,(uint32_t) bsp_ram_start,(uint32_t) bsp_ram_size,0,0,0,0,BPP_RX);
+#endif /* HAS_UBOOT */
+
   SET_IBAT(0,ibat.batu,ibat.batl);
-  calc_dbat_regvals(&ibat,ROM_START,ROM_SIZE,0,0,0,0,BPP_RX);
+
+#ifdef HAS_UBOOT
+  calc_dbat_regvals(&ibat,mpc83xx_uboot_board_info.bi_flashstart,mpc83xx_uboot_board_info.bi_flashsize,0,0,0,0,BPP_RX);
+#else /* HAS_UBOOT */
+  calc_dbat_regvals(&ibat,(uint32_t) bsp_rom_start,(uint32_t) bsp_rom_size,0,0,0,0,BPP_RX);
+#endif /* HAS_UBOOT */
+
   SET_IBAT(1,ibat.batu,ibat.batl);
 
@@ -187,11 +197,26 @@
   SET_DBAT(7,dbat.batu,dbat.batl);
 
-  calc_dbat_regvals(&dbat,RAM_START,RAM_SIZE,1,0,1,0,BPP_RW);
+#ifdef HAS_UBOOT
+  calc_dbat_regvals(&dbat,mpc83xx_uboot_board_info.bi_memstart,mpc83xx_uboot_board_info.bi_memsize,0,0,0,0,BPP_RW);
+#else /* HAS_UBOOT */
+  calc_dbat_regvals(&dbat,(uint32_t) bsp_ram_start,(uint32_t) bsp_ram_size,0,0,0,0,BPP_RW);
+#endif /* HAS_UBOOT */
+
   SET_DBAT(0,dbat.batu,dbat.batl);
 
-  calc_dbat_regvals(&dbat,ROM_START,ROM_SIZE,1,0,1,0,BPP_RX);
+#ifdef HAS_UBOOT
+  calc_dbat_regvals(&dbat,mpc83xx_uboot_board_info.bi_flashstart,mpc83xx_uboot_board_info.bi_flashsize,0,0,0,0,BPP_RX);
+#else /* HAS_UBOOT */
+  calc_dbat_regvals(&dbat,(uint32_t) bsp_rom_start,(uint32_t) bsp_rom_size,0,0,0,0,BPP_RX);
+#endif /* HAS_UBOOT */
+
   SET_DBAT(1,dbat.batu,dbat.batl);
 
-  calc_dbat_regvals(&dbat,IMMRBAR,1024*1024,1,1,1,1,BPP_RW);
+#ifdef HAS_UBOOT
+  calc_dbat_regvals(&dbat,mpc83xx_uboot_board_info.bi_immrbar,1024*1024,0,1,0,1,BPP_RW);
+#else /* HAS_UBOOT */
+  calc_dbat_regvals(&dbat,(uint32_t) IMMRBAR,1024*1024,0,1,0,1,BPP_RW);
+#endif /* HAS_UBOOT */
+
   SET_DBAT(2,dbat.batu,dbat.batl);
 
Index: c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ 	(revision )
@@ -1,318 +1,0 @@
-/*
- *  This file contains directives for the GNU linker which are specific
- *  to a gen8349eamds board.
- *
- *  You MUST have a linker script named linkcmds autoconf tests which
- *  use the "-B... -specs bsp_specs -qrtems" arguments work.
- *
- *  $Id$
- */
-
-OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc",
-              "elf32-powerpc")
-OUTPUT_ARCH(powerpc)
- 
-ENTRY(start)
-
-/*
- * Declare some sizes.
- * XXX: The assignment of ". += XyzSize;" fails in older gld's if the
- *      number used there is not constant.  If this happens to you, edit
- *      the lines marked XXX below to use a constant value.
- */
-HeapSize = DEFINED(HeapSize) ? HeapSize    : 0x6800000;  /* 104M  Heap */
-StackSize = DEFINED(StackSize) ? StackSize :   0x80000;  /* 512 kB   */
-WorkSpaceSize = DEFINED(WorkSpaceSize) ? WorkSpaceSize : 0x80000; /* 512k */
-RamDiskSize = DEFINED(RamDiskSize) ? RamDiskSize : 0x80000; /* 512 ram disk */
-
-/* 
- * optionally reserve additional space 
- */
-TopRamReserved = DEFINED(TopRamReserved) ? TopRamReserved : 0;
- 
-MEMORY
-	{
-	ram          : org = 0x0,        l = 256M
-	mpc83xx_regs : org = 0xE0000000, l = 256k
-	}
-
-
-SECTIONS
-{
-
-    mpc83xx_regs (NOLOAD) :
-    { 
-    IMMRBAR = .;
-    mpc83xx_regs*(.text)
-    mpc83xx_regs*(.data)
-    mpc83xx_regs*(.bss)
-    mpc83xx_regs*(*COM*)
-    } > mpc83xx_regs
-
-   .resconf 0x000 :
-    {
-    *(.resconf)
-    } > ram
-
-   .vectors 0x100 :
-    {
-    *(.vectors)
-    }   
-    > ram
-
-    /* 
-     * The stack will live in this area - between the vectors and
-     * the text section.
-     */
-	
-    .text 0x10000:
-    {
-    _textbase = .;
-
-
-    text.start = .;
-
-    /* Entry point is the .entry section */
-    *(.entry)
-    *(.entry2)
-
-    /* Actual Code */
-    *(.text*)
-
-    *(.rodata*)
-    *(.rodata1)
-
-
-    /*
-     * Special FreeBSD sysctl sections.
-     */
-    . = ALIGN (16);
-    __start_set_sysctl_set = .;
-    *(set_sysctl_*);
-    __stop_set_sysctl_set = ABSOLUTE(.);
-    *(set_domain_*);
-    *(set_pseudo_*);
-
-    /* C++ constructors/destructors */
-    *(.gnu.linkonce.t*)
-
-    /*  Initialization and finalization code.
-     *
-     *  Various files can provide initialization and finalization functions.
-     *  The bodies of these functions are in .init and .fini sections. We
-     *  accumulate the bodies here, and prepend function prologues from
-     *  ecrti.o and function epilogues from ecrtn.o. ecrti.o must be linked
-     *  first; ecrtn.o must be linked last. Because these are wildcards, it
-     *  doesn't matter if the user does not actually link against ecrti.o and
-     *  ecrtn.o; the linker won't look for a file to match a wildcard.  The
-     *  wildcard also means that it doesn't matter which directory ecrti.o
-     *  and ecrtn.o are in. 
-     */
-    PROVIDE (_init = .);
-    *ecrti.o(.init)
-    *(.init)
-    *ecrtn.o(.init)
-    
-    PROVIDE (_fini = .);
-    *ecrti.o(.fini)
-    *(.fini)
-    *ecrtn.o(.init)
-
-    /* 
-     *  C++ constructors and destructors for static objects.
-     *  PowerPC EABI does not use crtstuff yet, so we build "old-style"
-     *  constructor and destructor lists that begin with the list lenght
-     *  end terminate with a NULL entry.
-     */
-     
-    PROVIDE (__CTOR_LIST__ = .);	     
-    *crtbegin.o(.ctors)
-    *(.ctors)
-    *crtend.o(.ctors)
-    LONG(0)
-    PROVIDE (__CTOR_END__ = .);
-	
-    PROVIDE (__DTOR_LIST__ = .);
-    *crtbegin.o(.dtors)
-    *(.dtors)
-    *crtend.o(.dtors)
-    LONG(0)
-    PROVIDE (__DTOR_END__ = .);
-	
-    /* Exception frame info */
-    *(.eh_frame)
-
-    /* Miscellaneous read-only data */
-    _rodata_start = . ;
-    *(.gnu.linkonce.r*)
-    *(.lit)
-    *(.shdata)
-    *(.rodata)
-    *(.rodata1)
-    *(.descriptors)
-    *(rom_ver)
-    _erodata = .;
-
-    PROVIDE (__EXCEPT_START__ = .);
-    *(.gcc_except_table*)
-    PROVIDE (__EXCEPT_END__ = .);
-    __GOT_START__ = .;
-    s.got = .;
-    *(.got.plt) 
-    *(.got)
-    *(.got1)
-    PROVIDE (__GOT2_START__ = .);
-    PROVIDE (_GOT2_START_ = .);
-    *(.got2)
-    PROVIDE (__GOT2_END__ = .);
-    PROVIDE (_GOT2_END_ = .);
-    
-    PROVIDE (__FIXUP_START__ = .);
-    PROVIDE (_FIXUP_START_ = .);
-    *(.fixup)
-    PROVIDE (_FIXUP_END_ = .);
-    PROVIDE (__FIXUP_END__ = .);
-    
-
-    /* Various possible names for the end of the .text section */
-    etext = ALIGN(0x10);
-    _etext = .;
-    _endtext = .;
-    text.end = .;
-    PROVIDE (etext = .);
-    PROVIDE (__etext = .);
- 
-    } > ram
-
-  .jcr : { KEEP (*(.jcr)) } > ram
-
-    .rel.dyn : {
-      *(.rel.init)
-      *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
-      *(.rel.fini)
-      *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
-      *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*)
-      *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
-      *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
-      *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
-      *(.rel.ctors)
-      *(.rel.dtors)
-      *(.rel.got)
-      *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)
-      *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)
-      *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)
-      *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)
-      *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
-    } >ram
-    .rela.dyn : {
-      *(.rela.init)
-      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
-      *(.rela.fini)
-      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
-      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
-      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
-      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
-      *(.rela.ctors)
-      *(.rela.dtors)
-      *(.rela.got)
-      *(.rela.got1)
-      *(.rela.got2)
-      *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
-      *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
-      *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
-      *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
-      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
-    } >ram
-
-    PROVIDE (__SDATA2_START__ = .);
-  .sdata2   	  : { *(.sdata2) *(.gnu.linkonce.s2.*)	} >ram
-  .sbss2   	  : { *(.sbss2) *(.gnu.linkonce.sb2.*)	} >ram
-    PROVIDE (__SBSS2_END__ = .);
-	
-    .sbss2   	  : { *(.sbss2) 	} >ram
-    PROVIDE (__SBSS2_END__ = .);
-	
-    /* R/W Data */
-    .data ( . ) :
-    {
-      . = ALIGN (4);
-
-      data.start = .;
-
-      *(.data)
-      *(.data1)
-      *(.data.* .gnu.linkonce.d.*)
-      PROVIDE (__SDATA_START__ = .);
-      *(.sdata*)
-      *(.gnu.linkonce.s.*)
-      data.end = .;
-    } > ram
-
-    __SBSS_START__ = .;
-    .bss :
-    {
-      bss.start = .;
-      *(.bss .bss* .gnu.linkonce.b*)
-      *(.sbss*) *(COMMON)
-      . = ALIGN(4);
-      bss.end = .;
-    } > ram
-    __SBSS_END__ = .;
-
-    PROVIDE(_bss_start   = ADDR(.bss));
-    PROVIDE(_bss_size    = SIZEOF(.bss));
-    PROVIDE(_data_start  = ADDR(.data));
-    PROVIDE(_data_size   = SIZEOF(.data));
-    PROVIDE(_text_start  = ADDR(.text));
-    PROVIDE(_text_size   = SIZEOF(.text));
-    PROVIDE(_end = data.end);
-
-    .gzipmalloc : {
-	. = ALIGN (16);
-        _startmalloc = .;
-     } >ram
-          	
-    clear_end = .;
-
-    /*
-     * Interrupt stack setup
-     */
-    IntrStack_start = ALIGN(0x10);
-    . += 0x4000;
-    intrStack = .;
-    PROVIDE(intrStackPtr = intrStack);
-
-    _WorkspaceBase = .;
-    __WorkspaceBase = .;
-
-
-    /* Sections for compressed .text and .data         */
-    /* after the .datarom section is an int specifying */
-    /* the length of the following compressed image    */
-    /* Executes once then could get overwritten        */
-    .textrom 0x100000 :
-    {
-    	*(.textrom)
-    	_endloader = .;
-    } > ram
-
-    .datarom :
-    {
-    	_dr_start = .;
-    	*(.datarom)
-    	_dr_end = .;
-    } > ram
-    dr_len = _dr_end - _dr_start;
-
-
-    .line 0 : { *(.line) }
-    .debug 0 : { *(.debug) }
-    .debug_sfnames 0 : { *(.debug_sfnames) }
-    .debug_srcinfo 0 : { *(.debug_srcinfo) }
-    .debug_pubnames 0 : { *(.debug_pubnames) }
-    .debug_aranges 0 : { *(.debug_aranges) }
-    .debug_aregion 0 : { *(.debug_aregion) }
-    .debug_macinfo 0 : { *(.debug_macinfo) }
-    .stab 0 : { *(.stab) }
-    .stabstr 0 : { *(.stabstr) }
-}
Index: c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.base
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.base	(revision 574fb675105b77dfe9598915207f1f32790f905f)
+++ c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.base	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -0,0 +1,327 @@
+/**
+ * @file
+ *
+ * Derived from internal linker script of GNU ld (GNU Binutils) 2.18 for elf32ppc emulation.
+ */
+
+OUTPUT_FORMAT ("elf32-powerpc", "elf32-powerpc", "elf32-powerpc")
+OUTPUT_ARCH (powerpc)
+ENTRY (start)
+
+bsp_ram_start = ORIGIN (RAM);
+bsp_ram_end = ORIGIN (RAM) + LENGTH (RAM);
+bsp_ram_size = LENGTH (RAM);
+
+bsp_rom_start = ORIGIN (ROM);
+bsp_rom_end = ORIGIN (ROM) + LENGTH (ROM);
+bsp_rom_size = LENGTH (ROM);
+
+bsp_section_align = 32;
+
+SECTIONS {
+	/*
+	 * BSP: MPC83XX registers
+	 */
+	.mpc83xx_regs (NOLOAD) : { 
+		IMMRBAR = .;
+		mpc83xx_regs*(.text)
+		mpc83xx_regs*(.data)
+		mpc83xx_regs*(.bss)
+		mpc83xx_regs*(COMMON)
+	} > MPC83XX_REGS
+
+	/*
+	 * BSP: Reset configuration
+	 */
+	.resconf 0x0 : {
+		*(.resconf)
+	} > RAM
+
+	/*
+	 * BSP: Exception vectors
+	 */
+	.vectors 0x100 : {
+		*(.vectors)
+	} > RAM
+
+	/* 
+	 * BSP: The initial stack will live in this area - between the vectors
+	 * and the text section.
+	 */
+
+	.text 0x10000 : {
+		/*
+		 * BSP: Start of text section
+		 */
+		bsp_section_text_start = .;
+
+		/*
+		 * BSP: System startup entry
+		 */
+		KEEP (*(.entry))
+
+		/*
+		 * BSP: Moved into .text from .init
+		 */
+		KEEP (*(.init))
+
+		*(.text .stub .text.* .gnu.linkonce.t.*)
+		KEEP (*(.text.*personality*))
+		/* .gnu.warning sections are handled specially by elf32.em.  */
+		*(.gnu.warning)
+		*(.glink)
+		
+		/*
+		 * BSP: Special FreeBSD sysctl sections
+		 */
+		. = ALIGN (16);
+		__start_set_sysctl_set = .;
+		*(set_sysctl_*);
+		__stop_set_sysctl_set = ABSOLUTE(.);
+		*(set_domain_*);
+		*(set_pseudo_*);
+
+		/*
+		 * BSP: Moved into .text from .*
+		 */
+		*(.rodata .rodata.* .gnu.linkonce.r.*)
+		*(.rodata1)
+		*(.interp)
+		*(.note.gnu.build-id)
+		*(.hash)
+		*(.gnu.hash)
+		*(.dynsym)
+		*(.dynstr)
+		*(.gnu.version)
+		*(.gnu.version_d)
+		*(.gnu.version_r)
+		*(.eh_frame_hdr)
+
+		/*
+		 * BSP: Magic PPC stuff
+		 */
+		*(.PPC.*)
+
+		/*
+		 * BSP: Required by cpukit/score/src/threadhandler.c
+		 */
+		PROVIDE (_fini = .);
+
+		/*
+		 * BSP: Moved into .text from .fini
+		 */
+		KEEP (*(.fini))
+
+		. = ALIGN (bsp_section_align);
+
+		PROVIDE (__etext = .);
+		PROVIDE (_etext = .);
+		PROVIDE (etext = .);
+	} > RAM
+
+	.sdata2 : {
+		PROVIDE (_SDA2_BASE_ = 32768);
+
+		*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
+
+		. = ALIGN (bsp_section_align);
+	} > RAM
+
+	.sbss2 : {
+		*(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)
+
+		. = ALIGN (bsp_section_align);
+
+		/*
+		 * BSP: End and size of text section
+		 */
+		bsp_section_text_end = .;
+		bsp_section_text_size = bsp_section_text_end - bsp_section_text_start;
+	} > RAM
+
+	.data : {
+		/*
+		 * BSP: Start of data section
+		 */
+		bsp_section_data_start = .;
+
+		/*
+		 * BSP: Moved into .data from .ctors
+		 */
+		/* gcc uses crtbegin.o to find the start of
+		   the constructors, so we make sure it is
+		   first.  Because this is a wildcard, it
+		   doesn't matter if the user does not
+		   actually link against crtbegin.o; the
+		   linker won't look for a file to match a
+		   wildcard.  The wildcard also means that it
+		   doesn't matter which directory crtbegin.o
+		   is in.  */
+		KEEP (*crtbegin.o(.ctors))
+		KEEP (*crtbegin?.o(.ctors))
+		/* We don't want to include the .ctor section from
+		   the crtend.o file until after the sorted ctors.
+		   The .ctor section from the crtend file contains the
+		   end of ctors marker and it must be last */
+		KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+		KEEP (*(SORT(.ctors.*)))
+		KEEP (*(.ctors))
+
+		/*
+		 * BSP: Moved into .data from .dtors
+		 */
+		KEEP (*crtbegin.o(.dtors))
+		KEEP (*crtbegin?.o(.dtors))
+		KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+		KEEP (*(SORT(.dtors.*)))
+		KEEP (*(.dtors))
+
+		/*
+		 * BSP: Moved into .data from .*
+		 */
+		*(.tdata .tdata.* .gnu.linkonce.td.*)
+		*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+		*(.data1)
+		KEEP (*(.eh_frame))
+		*(.gcc_except_table .gcc_except_table.*)
+		KEEP (*(.jcr))
+		*(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*)
+		*(.fixup)
+		*(.got1)
+		*(.got2)
+		*(.dynamic)
+		*(.got)
+		*(.plt)
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP (*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP (*(SORT(.init_array.*)))
+		KEEP (*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP (*(.fini_array))
+		KEEP (*(SORT(.fini_array.*)))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		*(.data .data.* .gnu.linkonce.d.*)
+		KEEP (*(.gnu.linkonce.d.*personality*))
+		SORT(CONSTRUCTORS)
+
+		. = ALIGN (bsp_section_align);
+	} > RAM
+
+	.sdata : {
+		PROVIDE (_SDA_BASE_ = 32768);
+		*(.sdata .sdata.* .gnu.linkonce.s.*)
+
+		. = ALIGN (bsp_section_align);
+
+		_edata = .;
+		PROVIDE (edata = .);
+
+		/*
+		 * BSP: End and size of data section
+		 */
+		bsp_section_data_end = .;
+		bsp_section_data_size = bsp_section_data_end - bsp_section_data_start;
+	} > RAM
+
+	.sbss : {
+		/*
+		 * BSP: Start of bss section
+		 */
+		bsp_section_bss_start = .;
+
+		__bss_start = .;
+
+		PROVIDE (__sbss_start = .); PROVIDE (___sbss_start = .);
+		*(.scommon)
+		*(.dynsbss)
+		*(.sbss .sbss.* .gnu.linkonce.sb.*)
+		PROVIDE (__sbss_end = .); PROVIDE (___sbss_end = .);
+
+		. = ALIGN (bsp_section_align);
+	} > RAM
+
+	.bss : {
+		*(COMMON)
+		*(.dynbss)
+		*(.bss .bss.* .gnu.linkonce.b.*)
+
+		. = ALIGN (bsp_section_align);
+
+		__end = .;
+		_end = .;
+		PROVIDE (end = .);
+
+		/*
+		 * BSP: End and size of bss section
+		 */
+		bsp_section_bss_end = .;
+		bsp_section_bss_size = bsp_section_bss_end - bsp_section_bss_start;
+	} > RAM
+
+	/*
+	 * BSP: Interrupt stack
+	 */
+	bsp_interrupt_stack_start = .;
+	bsp_interrupt_stack_end = bsp_interrupt_stack_start + 32k;
+	bsp_interrupt_stack_size = bsp_interrupt_stack_end - bsp_interrupt_stack_start;
+	bsp_interrupt_stack_pointer = bsp_interrupt_stack_end - 16;
+	. = bsp_interrupt_stack_end;
+
+	/*
+	 * BSP: Workspace start
+	 */
+	bsp_workspace_start = .;
+	
+	/* Stabs debugging sections.  */
+	.stab          0 : { *(.stab) }
+	.stabstr       0 : { *(.stabstr) }
+	.stab.excl     0 : { *(.stab.excl) }
+	.stab.exclstr  0 : { *(.stab.exclstr) }
+	.stab.index    0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment       0 : { *(.comment) }
+	/* DWARF debug sections.
+	   Symbols in the DWARF debugging sections are relative to the beginning
+	   of the section so we begin them at 0.  */
+	/* DWARF 1 */
+	.debug          0 : { *(.debug) }
+	.line           0 : { *(.line) }
+	/* GNU DWARF 1 extensions */
+	.debug_srcinfo  0 : { *(.debug_srcinfo) }
+	.debug_sfnames  0 : { *(.debug_sfnames) }
+	/* DWARF 1.1 and DWARF 2 */
+	.debug_aranges  0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	/* DWARF 2 */
+	.debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+	.debug_abbrev   0 : { *(.debug_abbrev) }
+	.debug_line     0 : { *(.debug_line) }
+	.debug_frame    0 : { *(.debug_frame) }
+	.debug_str      0 : { *(.debug_str) }
+	.debug_loc      0 : { *(.debug_loc) }
+	.debug_macinfo  0 : { *(.debug_macinfo) }
+	/* SGI/MIPS DWARF 2 extensions */
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames  0 : { *(.debug_varnames) }
+	/* DWARF 3 */
+	.debug_pubtypes 0 : { *(.debug_pubtypes) }
+	.debug_ranges   0 : { *(.debug_ranges) }
+	.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
+
+	/DISCARD/ : {
+		*(.note.GNU-stack) *(.gnu_debuglink)
+	}
+
+	/*
+	 * BSP: Catch all unknown sections
+	 */
+	.nirvana : {
+		*(*)
+	} > NIRVANA
+}
Index: c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.hsc_cm01
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.hsc_cm01	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.hsc_cm01	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -1,332 +1,14 @@
-/*
- *  This file contains directives for the GNU linker which are specific
- *  to a hsc_cm01 board
+/**
+ * @file
  *
- *  $Id$
+ * HSC_CM01 Board.
  */
 
-OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc",
-              "elf32-powerpc")
-OUTPUT_ARCH(powerpc)
- 
-ENTRY(start)
+MEMORY {
+	RAM : ORIGIN = 0x0, LENGTH = 256M
+	ROM : ORIGIN = 0xfe000000, LENGTH = 8M
+	MPC83XX_REGS : ORIGIN = 0xe0000000, LENGTH = 256k
+	NIRVANA : ORIGIN = 0x0, LENGTH = 0
+}
 
-/*
- * Declare some sizes.
- * XXX: The assignment of ". += XyzSize;" fails in older gld's if the
- *      number used there is not constant.  If this happens to you, edit
- *      the lines marked XXX below to use a constant value.
- */
-HeapSize = DEFINED(HeapSize) ? HeapSize    : 0x6800000;  /* 104M  Heap */
-StackSize = DEFINED(StackSize) ? StackSize :   0x80000;  /* 512 kB   */
-WorkSpaceSize = DEFINED(WorkSpaceSize) ? WorkSpaceSize : 0x80000; /* 512k */
-RamDiskSize = DEFINED(RamDiskSize) ? RamDiskSize : 0x80000; /* 512 ram disk */
-
-/* 
- * optionally reserve additional space 
- */
-TopRamReserved = DEFINED(TopRamReserved) ? TopRamReserved : 0;
- 
-MEMORY
-	{
-	ram          : org = 0x0,        l = 256M
-	mpc83xx_regs : org = 0xE0000000, l = 256k
-	}
-
-
-SECTIONS
-{
-
-    .mpc83xx_regs (NOLOAD) :
-    { 
-    IMMRBAR = .;
-    mpc83xx_regs*(.text)
-    mpc83xx_regs*(.data)
-    mpc83xx_regs*(.bss)
-    mpc83xx_regs*(*COM*)
-    } > mpc83xx_regs
-
-   .resconf 0x000 :
-    {
-    *(.resconf)
-    } > ram
-
-   .vectors 0x100 :
-    {
-    *(.vectors)
-    }   
-    > ram
-
-    /* 
-     * The stack will live in this area - between the vectors and
-     * the text section.
-     */
-	
-    .text 0x10000:
-    {
-    _textbase = .;
-
-
-    text.start = .;
-
-    /* Entry point is the .entry section */
-    *(.entry)
-    *(.entry2)
-
-    /* Actual Code */
-    *(.text*)
-
-    *(.rodata*)
-    *(.rodata1)
-
-
-    /*
-     * Special FreeBSD sysctl sections.
-     */
-    . = ALIGN (16);
-    __start_set_sysctl_set = .;
-    *(set_sysctl_*);
-    __stop_set_sysctl_set = ABSOLUTE(.);
-    *(set_domain_*);
-    *(set_pseudo_*);
-
-    /* C++ constructors/destructors */
-    *(.gnu.linkonce.t*)
-
-    /*  Initialization and finalization code.
-     *
-     *  Various files can provide initialization and finalization functions.
-     *  The bodies of these functions are in .init and .fini sections. We
-     *  accumulate the bodies here, and prepend function prologues from
-     *  ecrti.o and function epilogues from ecrtn.o. ecrti.o must be linked
-     *  first; ecrtn.o must be linked last. Because these are wildcards, it
-     *  doesn't matter if the user does not actually link against ecrti.o and
-     *  ecrtn.o; the linker won't look for a file to match a wildcard.  The
-     *  wildcard also means that it doesn't matter which directory ecrti.o
-     *  and ecrtn.o are in. 
-     */
-    PROVIDE (_init = .);
-    *ecrti.o(.init)
-    *(.init)
-    *ecrtn.o(.init)
-    
-    PROVIDE (_fini = .);
-    *ecrti.o(.fini)
-    *(.fini)
-    *ecrtn.o(.init)
-
-    /* 
-     *  C++ constructors and destructors for static objects.
-     *  PowerPC EABI does not use crtstuff yet, so we build "old-style"
-     *  constructor and destructor lists that begin with the list lenght
-     *  end terminate with a NULL entry.
-     */
-     
-    PROVIDE (__CTOR_LIST__ = .);	     
-    *crtbegin.o(.ctors)
-    *(.ctors)
-    *crtend.o(.ctors)
-    LONG(0)
-    PROVIDE (__CTOR_END__ = .);
-	
-    PROVIDE (__DTOR_LIST__ = .);
-    *crtbegin.o(.dtors)
-    *(.dtors)
-    *crtend.o(.dtors)
-    LONG(0)
-    PROVIDE (__DTOR_END__ = .);
-	
-    /* Exception frame info */
-    *(.eh_frame)
-
-    /* Miscellaneous read-only data */
-    _rodata_start = . ;
-    *(.gnu.linkonce.r*)
-    *(.lit)
-    *(.shdata)
-    *(.rodata)
-    *(.rodata1)
-    *(.descriptors)
-    *(rom_ver)
-    _erodata = .;
-
-    PROVIDE (__EXCEPT_START__ = .);
-    *(.gcc_except_table*)
-    PROVIDE (__EXCEPT_END__ = .);
-    __GOT_START__ = .;
-    s.got = .;
-    *(.got.plt) 
-    *(.got)
-    *(.got1)
-    PROVIDE (__GOT2_START__ = .);
-    PROVIDE (_GOT2_START_ = .);
-    *(.got2)
-    PROVIDE (__GOT2_END__ = .);
-    PROVIDE (_GOT2_END_ = .);
-    
-    PROVIDE (__FIXUP_START__ = .);
-    PROVIDE (_FIXUP_START_ = .);
-    *(.fixup)
-    PROVIDE (_FIXUP_END_ = .);
-    PROVIDE (__FIXUP_END__ = .);
-    
-
-    /* Various possible names for the end of the .text section */
-    etext = ALIGN(0x10);
-    _etext = .;
-    _endtext = .;
-    text.end = .;
-    PROVIDE (etext = .);
-    PROVIDE (__etext = .);
- 
-    } > ram
-
-  .jcr : { KEEP (*(.jcr)) } > ram
-
-    .rel.dyn : {
-      *(.rel.init)
-      *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
-      *(.rel.fini)
-      *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
-      *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*)
-      *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
-      *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
-      *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
-      *(.rel.ctors)
-      *(.rel.dtors)
-      *(.rel.got)
-      *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)
-      *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)
-      *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)
-      *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)
-      *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
-    } >ram
-    .rela.dyn : {
-      *(.rela.init)
-      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
-      *(.rela.fini)
-      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
-      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
-      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
-      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
-      *(.rela.ctors)
-      *(.rela.dtors)
-      *(.rela.got)
-      *(.rela.got1)
-      *(.rela.got2)
-      *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
-      *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
-      *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
-      *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
-      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
-    } >ram
-
-    PROVIDE (__SDATA2_START__ = .);
-  .sdata2   	  : { *(.sdata2) *(.gnu.linkonce.s2.*)	} >ram
-  .sbss2   	  : { *(.sbss2) *(.gnu.linkonce.sb2.*)	} >ram
-    PROVIDE (__SBSS2_END__ = .);
-	
-    .sbss2   	  : { *(.sbss2) 	} >ram
-    PROVIDE (__SBSS2_END__ = .);
-	
-    /* R/W Data */
-    .data ( . ) :
-    {
-      . = ALIGN (4);
-
-      data.start = .;
-
-      *(.data)
-      *(.data1)
-      *(.data.* .gnu.linkonce.d.*)
-      PROVIDE (__SDATA_START__ = .);
-      *(.sdata*)
-      *(.gnu.linkonce.s.*)
-      data.end = .;
-    } > ram
-
-    __SBSS_START__ = .;
-    .bss :
-    {
-      bss.start = .;
-      *(.bss .bss* .gnu.linkonce.b*)
-      *(.sbss*) *(COMMON)
-      . = ALIGN(4);
-      bss.end = .;
-    } > ram
-    __SBSS_END__ = .;
-
-    PROVIDE(_bss_start   = ADDR(.bss));
-    PROVIDE(_bss_size    = SIZEOF(.bss));
-    PROVIDE(_data_start  = ADDR(.data));
-    PROVIDE(_data_size   = SIZEOF(.data));
-    PROVIDE(_text_start  = ADDR(.text));
-    PROVIDE(_text_size   = SIZEOF(.text));
-    PROVIDE(_end = data.end);
-
-    .gzipmalloc : {
-	. = ALIGN (16);
-        _startmalloc = .;
-     } >ram
-          	
-
-    /*
-     * Interrupt stack setup
-     */
-    IntrStack_start = ALIGN(0x10);
-    . += 0x4000;
-    intrStack = .;
-    PROVIDE(intrStackPtr = intrStack);
-
-
-
-
-    _WorkspaceBase = .;
-    __WorkspaceBase = .;
-    . += WorkSpaceSize;
-
-    _RamDiskBase = .;
-    __RamDiskBase = .;
-    . += RamDiskSize;
-    _RamDiskEnd  = .;
-    __RamDiskEnd = .;
-    PROVIDE( _RamDiskSize = _RamDiskEnd - _RamDiskBase );
-
-    _HeapStart = .;
-    __HeapStart = .;
-    . += HeapSize;
-    _HeapEnd = .;
-    __HeapEnd = .;
-
-    clear_end = .;
-
-    /* Sections for compressed .text and .data         */
-    /* after the .datarom section is an int specifying */
-    /* the length of the following compressed image    */
-    /* Executes once then could get overwritten        */
-    .textrom 0x100000 :
-    {
-    	*(.textrom)
-    	_endloader = .;
-    } > ram
-
-    .datarom :
-    {
-    	_dr_start = .;
-    	*(.datarom)
-    	_dr_end = .;
-    } > ram
-    dr_len = _dr_end - _dr_start;
-
-
-    .line 0 : { *(.line) }
-    .debug 0 : { *(.debug) }
-    .debug_sfnames 0 : { *(.debug_sfnames) }
-    .debug_srcinfo 0 : { *(.debug_srcinfo) }
-    .debug_pubnames 0 : { *(.debug_pubnames) }
-    .debug_aranges 0 : { *(.debug_aranges) }
-    .debug_aregion 0 : { *(.debug_aregion) }
-    .debug_macinfo 0 : { *(.debug_macinfo) }
-    .stab 0 : { *(.stab) }
-    .stabstr 0 : { *(.stabstr) }
-}
+INCLUDE linkcmds.base
Index: c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.mpc8313erdb
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.mpc8313erdb	(revision 574fb675105b77dfe9598915207f1f32790f905f)
+++ c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.mpc8313erdb	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -0,0 +1,14 @@
+/**
+ * @file
+ *
+ * MPC8313E Reference Design Board.
+ */
+
+MEMORY {
+	RAM : ORIGIN = 0x0, LENGTH = 128M
+	ROM : ORIGIN = 0xfe000000, LENGTH = 8M
+	MPC83XX_REGS : ORIGIN = 0xe0000000, LENGTH = 256k
+	NIRVANA : ORIGIN = 0x0, LENGTH = 0
+}
+
+INCLUDE linkcmds.base
Index: c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.mpc8349eamds
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.mpc8349eamds	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.mpc8349eamds	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -1,332 +1,14 @@
-/*
- *  This file contains directives for the GNU linker which are specific
- *  to a gen8349eamds board
+/**
+ * @file
  *
- *  $Id$
+ * MPC8349EAMDS Board.
  */
 
-OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc",
-              "elf32-powerpc")
-OUTPUT_ARCH(powerpc)
- 
-ENTRY(start)
+MEMORY {
+	RAM : ORIGIN = 0x0, LENGTH = 256M
+	ROM : ORIGIN = 0xfe000000, LENGTH = 8M
+	MPC83XX_REGS : ORIGIN = 0xe0000000, LENGTH = 256k
+	NIRVANA : ORIGIN = 0x0, LENGTH = 0
+}
 
-/*
- * Declare some sizes.
- * XXX: The assignment of ". += XyzSize;" fails in older gld's if the
- *      number used there is not constant.  If this happens to you, edit
- *      the lines marked XXX below to use a constant value.
- */
-HeapSize = DEFINED(HeapSize) ? HeapSize    : 0x6800000;  /* 104M  Heap */
-StackSize = DEFINED(StackSize) ? StackSize :   0x80000;  /* 512 kB   */
-WorkSpaceSize = DEFINED(WorkSpaceSize) ? WorkSpaceSize : 0x80000; /* 512k */
-RamDiskSize = DEFINED(RamDiskSize) ? RamDiskSize : 0x80000; /* 512 ram disk */
-
-/* 
- * optionally reserve additional space 
- */
-TopRamReserved = DEFINED(TopRamReserved) ? TopRamReserved : 0;
- 
-MEMORY
-	{
-	ram          : org = 0x0,        l = 256M
-	mpc83xx_regs : org = 0xE0000000, l = 256k
-	}
-
-
-SECTIONS
-{
-
-    mpc83xx_regs (NOLOAD) :
-    { 
-    IMMRBAR = .;
-    mpc83xx_regs*(.text)
-    mpc83xx_regs*(.data)
-    mpc83xx_regs*(.bss)
-    mpc83xx_regs*(*COM*)
-    } > mpc83xx_regs
-
-   .resconf 0x000 :
-    {
-    *(.resconf)
-    } > ram
-
-   .vectors 0x100 :
-    {
-    *(.vectors)
-    }   
-    > ram
-
-    /* 
-     * The stack will live in this area - between the vectors and
-     * the text section.
-     */
-	
-    .text 0x10000:
-    {
-    _textbase = .;
-
-
-    text.start = .;
-
-    /* Entry point is the .entry section */
-    *(.entry)
-    *(.entry2)
-
-    /* Actual Code */
-    *(.text*)
-
-    *(.rodata*)
-    *(.rodata1)
-
-
-    /*
-     * Special FreeBSD sysctl sections.
-     */
-    . = ALIGN (16);
-    __start_set_sysctl_set = .;
-    *(set_sysctl_*);
-    __stop_set_sysctl_set = ABSOLUTE(.);
-    *(set_domain_*);
-    *(set_pseudo_*);
-
-    /* C++ constructors/destructors */
-    *(.gnu.linkonce.t*)
-
-    /*  Initialization and finalization code.
-     *
-     *  Various files can provide initialization and finalization functions.
-     *  The bodies of these functions are in .init and .fini sections. We
-     *  accumulate the bodies here, and prepend function prologues from
-     *  ecrti.o and function epilogues from ecrtn.o. ecrti.o must be linked
-     *  first; ecrtn.o must be linked last. Because these are wildcards, it
-     *  doesn't matter if the user does not actually link against ecrti.o and
-     *  ecrtn.o; the linker won't look for a file to match a wildcard.  The
-     *  wildcard also means that it doesn't matter which directory ecrti.o
-     *  and ecrtn.o are in. 
-     */
-    PROVIDE (_init = .);
-    *ecrti.o(.init)
-    *(.init)
-    *ecrtn.o(.init)
-    
-    PROVIDE (_fini = .);
-    *ecrti.o(.fini)
-    *(.fini)
-    *ecrtn.o(.init)
-
-    /* 
-     *  C++ constructors and destructors for static objects.
-     *  PowerPC EABI does not use crtstuff yet, so we build "old-style"
-     *  constructor and destructor lists that begin with the list lenght
-     *  end terminate with a NULL entry.
-     */
-     
-    PROVIDE (__CTOR_LIST__ = .);	     
-    *crtbegin.o(.ctors)
-    *(.ctors)
-    *crtend.o(.ctors)
-    LONG(0)
-    PROVIDE (__CTOR_END__ = .);
-	
-    PROVIDE (__DTOR_LIST__ = .);
-    *crtbegin.o(.dtors)
-    *(.dtors)
-    *crtend.o(.dtors)
-    LONG(0)
-    PROVIDE (__DTOR_END__ = .);
-	
-    /* Exception frame info */
-    *(.eh_frame)
-
-    /* Miscellaneous read-only data */
-    _rodata_start = . ;
-    *(.gnu.linkonce.r*)
-    *(.lit)
-    *(.shdata)
-    *(.rodata)
-    *(.rodata1)
-    *(.descriptors)
-    *(rom_ver)
-    _erodata = .;
-
-    PROVIDE (__EXCEPT_START__ = .);
-    *(.gcc_except_table*)
-    PROVIDE (__EXCEPT_END__ = .);
-    __GOT_START__ = .;
-    s.got = .;
-    *(.got.plt) 
-    *(.got)
-    *(.got1)
-    PROVIDE (__GOT2_START__ = .);
-    PROVIDE (_GOT2_START_ = .);
-    *(.got2)
-    PROVIDE (__GOT2_END__ = .);
-    PROVIDE (_GOT2_END_ = .);
-    
-    PROVIDE (__FIXUP_START__ = .);
-    PROVIDE (_FIXUP_START_ = .);
-    *(.fixup)
-    PROVIDE (_FIXUP_END_ = .);
-    PROVIDE (__FIXUP_END__ = .);
-    
-
-    /* Various possible names for the end of the .text section */
-    etext = ALIGN(0x10);
-    _etext = .;
-    _endtext = .;
-    text.end = .;
-    PROVIDE (etext = .);
-    PROVIDE (__etext = .);
- 
-    } > ram
-
-  .jcr : { KEEP (*(.jcr)) } > ram
-
-    .rel.dyn : {
-      *(.rel.init)
-      *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
-      *(.rel.fini)
-      *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
-      *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*)
-      *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
-      *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
-      *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
-      *(.rel.ctors)
-      *(.rel.dtors)
-      *(.rel.got)
-      *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)
-      *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)
-      *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)
-      *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)
-      *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
-    } >ram
-    .rela.dyn : {
-      *(.rela.init)
-      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
-      *(.rela.fini)
-      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
-      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
-      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
-      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
-      *(.rela.ctors)
-      *(.rela.dtors)
-      *(.rela.got)
-      *(.rela.got1)
-      *(.rela.got2)
-      *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
-      *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
-      *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
-      *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
-      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
-    } >ram
-
-    PROVIDE (__SDATA2_START__ = .);
-  .sdata2   	  : { *(.sdata2) *(.gnu.linkonce.s2.*)	} >ram
-  .sbss2   	  : { *(.sbss2) *(.gnu.linkonce.sb2.*)	} >ram
-    PROVIDE (__SBSS2_END__ = .);
-	
-    .sbss2   	  : { *(.sbss2) 	} >ram
-    PROVIDE (__SBSS2_END__ = .);
-	
-    /* R/W Data */
-    .data ( . ) :
-    {
-      . = ALIGN (4);
-
-      data.start = .;
-
-      *(.data)
-      *(.data1)
-      *(.data.* .gnu.linkonce.d.*)
-      PROVIDE (__SDATA_START__ = .);
-      *(.sdata*)
-      *(.gnu.linkonce.s.*)
-      data.end = .;
-    } > ram
-
-    __SBSS_START__ = .;
-    .bss :
-    {
-      bss.start = .;
-      *(.bss .bss* .gnu.linkonce.b*)
-      *(.sbss*) *(COMMON)
-      . = ALIGN(4);
-      bss.end = .;
-    } > ram
-    __SBSS_END__ = .;
-
-    PROVIDE(_bss_start   = ADDR(.bss));
-    PROVIDE(_bss_size    = SIZEOF(.bss));
-    PROVIDE(_data_start  = ADDR(.data));
-    PROVIDE(_data_size   = SIZEOF(.data));
-    PROVIDE(_text_start  = ADDR(.text));
-    PROVIDE(_text_size   = SIZEOF(.text));
-    PROVIDE(_end = data.end);
-
-    .gzipmalloc : {
-	. = ALIGN (16);
-        _startmalloc = .;
-     } >ram
-          	
-
-    /*
-     * Interrupt stack setup
-     */
-    IntrStack_start = ALIGN(0x10);
-    . += 0x4000;
-    intrStack = .;
-    PROVIDE(intrStackPtr = intrStack);
-
-
-
-
-    _WorkspaceBase = .;
-    __WorkspaceBase = .;
-    . += WorkSpaceSize;
-
-    _RamDiskBase = .;
-    __RamDiskBase = .;
-    . += RamDiskSize;
-    _RamDiskEnd  = .;
-    __RamDiskEnd = .;
-    PROVIDE( _RamDiskSize = _RamDiskEnd - _RamDiskBase );
-
-    _HeapStart = .;
-    __HeapStart = .;
-    . += HeapSize;
-    _HeapEnd = .;
-    __HeapEnd = .;
-
-    clear_end = .;
-
-    /* Sections for compressed .text and .data         */
-    /* after the .datarom section is an int specifying */
-    /* the length of the following compressed image    */
-    /* Executes once then could get overwritten        */
-    .textrom 0x100000 :
-    {
-    	*(.textrom)
-    	_endloader = .;
-    } > ram
-
-    .datarom :
-    {
-    	_dr_start = .;
-    	*(.datarom)
-    	_dr_end = .;
-    } > ram
-    dr_len = _dr_end - _dr_start;
-
-
-    .line 0 : { *(.line) }
-    .debug 0 : { *(.debug) }
-    .debug_sfnames 0 : { *(.debug_sfnames) }
-    .debug_srcinfo 0 : { *(.debug_srcinfo) }
-    .debug_pubnames 0 : { *(.debug_pubnames) }
-    .debug_aranges 0 : { *(.debug_aranges) }
-    .debug_aregion 0 : { *(.debug_aregion) }
-    .debug_macinfo 0 : { *(.debug_macinfo) }
-    .stab 0 : { *(.stab) }
-    .stabstr 0 : { *(.stabstr) }
-}
+INCLUDE linkcmds.base
Index: c/src/lib/libbsp/powerpc/haleakala/ChangeLog
===================================================================
--- c/src/lib/libbsp/powerpc/haleakala/ChangeLog	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ c/src/lib/libbsp/powerpc/haleakala/ChangeLog	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -1,2 +1,9 @@
+2008-07-14	Thomas Doerfler <thomas.doerfler@embedded-brains.de>
+
+	* irq/irq.c: adapted DCR access syntax
+	
+	* startup/linkcmds, startup/bspstartup.c, Makefile.am: 
+	adapted to exception support code
+
 2008-07-14	Thomas Doerfler <thomas.doerfler@embedded-brains.de>
 
Index: c/src/lib/libbsp/powerpc/haleakala/Makefile.am
===================================================================
--- c/src/lib/libbsp/powerpc/haleakala/Makefile.am	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ c/src/lib/libbsp/powerpc/haleakala/Makefile.am	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -57,5 +57,5 @@
 	../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h \
 	../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h
-	
+
 noinst_PROGRAMS += irq.rel
 irq_rel_SOURCES = irq/irq_init.c irq/irq.c
@@ -64,11 +64,11 @@
 
 
-if HAS_NETWORKING
-network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__
-noinst_PROGRAMS += network.rel
-network_rel_SOURCES = network/network.c
-network_rel_CPPFLAGS = $(AM_CPPFLAGS) $(network_CPPFLAGS)
-network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
-endif
+## if HAS_NETWORKING
+## network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__
+## noinst_PROGRAMS += network.rel
+## network_rel_SOURCES = network/network.c
+## network_rel_CPPFLAGS = $(AM_CPPFLAGS) $(network_CPPFLAGS)
+## network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+## endif
 
 
@@ -78,15 +78,15 @@
 libbsp_a_LIBADD = startup.rel dlentry.rel console.rel irq.rel
 
-if HAS_NETWORKING
-libbsp_a_LIBADD += network.rel
-endif
+## if HAS_NETWORKING
+## libbsp_a_LIBADD += network.rel
+## endif
 
 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
-    ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
- 	../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
+	../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
+	../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
 	../../../libcpu/@RTEMS_CPU@/@exceptions@/irq_bspsupport.rel \
-    ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
+	../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
 	../../../libcpu/@RTEMS_CPU@/ppc403/clock.rel \
-    ../../../libcpu/@RTEMS_CPU@/ppc403/timer.rel 
+	../../../libcpu/@RTEMS_CPU@/ppc403/timer.rel 
 
 
Index: c/src/lib/libbsp/powerpc/haleakala/irq/irq.c
===================================================================
--- c/src/lib/libbsp/powerpc/haleakala/irq/irq.c	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ c/src/lib/libbsp/powerpc/haleakala/irq/irq.c	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -70,7 +70,10 @@
 /* Write the gEnabledInts state masked by gIntInhibited to the hardware */
 {
-	mtdcr(UIC0_ER, gEnabledInts[0] & ~gIntInhibited[0]);
-	mtdcr(UIC1_ER, gEnabledInts[1] & ~gIntInhibited[1]);
-	mtdcr(UIC2_ER, gEnabledInts[2] & ~gIntInhibited[2]);
+	PPC_SET_DEVICE_CONTROL_REGISTER(UIC0_ER, 
+					gEnabledInts[0] & ~gIntInhibited[0]);
+	PPC_SET_DEVICE_CONTROL_REGISTER(UIC1_ER, 
+					gEnabledInts[1] & ~gIntInhibited[1]);
+	PPC_SET_DEVICE_CONTROL_REGISTER(UIC2_ER, 
+					gEnabledInts[2] & ~gIntInhibited[2]);
 }
 
@@ -113,24 +116,42 @@
 		gIntInhibited[i] = 0;
 		
-	mtdcr (UIC2_ER, 0x00000000);	/* disable all interrupts */
-	mtdcr (UIC2_CR, 0x00000000);	/* Set Critical / Non Critical interrupts */
-	mtdcr (UIC2_PR, 0xf7ffffff);	/* Set Interrupt Polarities */
-	mtdcr (UIC2_TR, 0x01e1fff8);	/* Set Interrupt Trigger Levels */
-	mtdcr (UIC2_VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (UIC2_SR, 0xffffffff);	/* clear all interrupts */
-
-	mtdcr (UIC1_ER, 0x00000000);	/* disable all interrupts */
-	mtdcr (UIC1_CR, 0x00000000);	/* Set Critical / Non Critical interrupts */
-	mtdcr (UIC1_PR, 0xfffac785);	/* Set Interrupt Polarities */
-	mtdcr (UIC1_TR, 0x001d0040);	/* Set Interrupt Trigger Levels */
-	mtdcr (UIC1_VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (UIC1_SR, 0xffffffff);	/* clear all interrupts */
-
-	mtdcr (UIC0_ER, 0x0000000a);	/* Disable all interrupts except cascade UIC0 and UIC1 */
-	mtdcr (UIC0_CR, 0x00000000);	/* Set Critical / Non Critical interrupts */
-	mtdcr (UIC0_PR, 0xffbfefef);	/* Set Interrupt Polarities */
-	mtdcr (UIC0_TR, 0x00007000);	/* Set Interrupt Trigger Levels */
-	mtdcr (UIC0_VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (UIC0_SR, 0xffffffff);	/* clear all interrupts */
+	/* disable all interrupts */
+	PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_ER, 0x00000000);	
+	/* Set Critical / Non Critical interrupts */
+	PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_CR, 0x00000000);
+	/* Set Interrupt Polarities */
+	PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_PR, 0xf7ffffff);
+	/* Set Interrupt Trigger Levels */
+	PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_TR, 0x01e1fff8);
+	/* Set Vect base=0,INT31 Highest priority */
+	PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_VR, 0x00000001);
+	/* clear all interrupts */
+	PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_SR, 0xffffffff);
+
+	/* disable all interrupts */
+	PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_ER, 0x00000000);
+	/* Set Critical / Non Critical interrupts */
+	PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_CR, 0x00000000);
+	/* Set Interrupt Polarities */
+	PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_PR, 0xfffac785);
+	/* Set Interrupt Trigger Levels */
+	PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_TR, 0x001d0040);
+	/* Set Vect base=0,INT31 Highest priority */
+	PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_VR, 0x00000001);
+	/* clear all interrupts */
+	PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_SR, 0xffffffff);
+
+	/* Disable all interrupts except cascade UIC0 and UIC1 */
+	PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_ER, 0x0000000a);
+	/* Set Critical / Non Critical interrupts */
+	PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_CR, 0x00000000);
+	/* Set Interrupt Polarities */
+	PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_PR, 0xffbfefef);
+	/* Set Interrupt Trigger Levels */
+	PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_TR, 0x00007000);
+	/* Set Vect base=0,INT31 Highest priority */
+	PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_VR, 0x00000001);
+	/* clear all interrupts */
+	PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_SR, 0xffffffff);
 	
 	return 1;
@@ -154,7 +175,7 @@
 		   Likely to be only one, but we need to handle more than one,
 		   OR the flags into gIntInhibited */
-		active[0] = mfdcr(UIC0_MSR);
-		active[1] = mfdcr(UIC1_MSR);
-		active[2] = mfdcr(UIC2_MSR);
+		active[0] = PPC_DEVICE_CONTROL_REGISTER(UIC0_MSR);
+		active[1] = PPC_DEVICE_CONTROL_REGISTER(UIC1_MSR);
+		active[2] = PPC_DEVICE_CONTROL_REGISTER(UIC2_MSR);
 		gIntInhibited[0] |= active[0];
 		gIntInhibited[1] |= active[1];
@@ -181,7 +202,13 @@
 			bmask = 0x80000000 >> bit;
 			switch (index) {
-				case 0: mtdcr(UIC0_SR, bmask); break;
-				case 1: mtdcr(UIC1_SR, bmask); break;
-				case 2: mtdcr(UIC2_SR, bmask); break;
+			case 0: 
+			  PPC_SET_DEVICE_CONTROL_REGISTER(UIC0_SR, bmask);
+			  break;
+			case 1: 
+			  PPC_SET_DEVICE_CONTROL_REGISTER(UIC1_SR, bmask);
+			  break;
+			case 2: 
+			  PPC_SET_DEVICE_CONTROL_REGISTER(UIC2_SR, bmask);
+			  break;
 			}
 			
Index: c/src/lib/libbsp/powerpc/haleakala/startup/bspstart.c
===================================================================
--- c/src/lib/libbsp/powerpc/haleakala/startup/bspstart.c	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ c/src/lib/libbsp/powerpc/haleakala/startup/bspstart.c	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -69,11 +69,8 @@
 #include <rtems/bspIo.h>
 #include <libcpu/cpuIdent.h>
-#include <libcpu/spr.h>
 #include <rtems/powerpc/powerpc.h>
+#include <bsp/ppc_exc_bspsupp.h>
 #include <ppc4xx/ppc405gp.h>
 #include <ppc4xx/ppc405ex.h>
-
-SPR_RW(SPRG0)
-SPR_RW(SPRG1)
 
 #include <stdio.h>
@@ -233,6 +230,6 @@
 void bsp_start( void )
 {
-	extern unsigned long *intrStackPtr;
-	register unsigned char* intrStack;
+	LINKER_SYMBOL(intrStack_start);
+	LINKER_SYMBOL(intrStack_size);
 	ppc_cpu_id_t myCpu;
 	ppc_cpu_revision_t myCpuRevision;
@@ -263,14 +260,10 @@
 	
 	/*
-	* Initialize some SPRG registers related to irq handling
-	*/
-
-	intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE);
-	_write_SPRG1((unsigned int)intrStack);
-	/* signal them that we have fixed PR288 - eventually, this should go away */
-	/*
 	* Initialize default raw exception handlers. 
 	*/
-	initialize_exceptions();
+	ppc_exc_initialize(
+		PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
+			   (uint32_t) intrStack_start,
+			   (uint32_t) intrStack_size);
 
 	/*
Index: c/src/lib/libbsp/powerpc/haleakala/startup/linkcmds
===================================================================
--- c/src/lib/libbsp/powerpc/haleakala/startup/linkcmds	(revision 3c6fe2e7f95f6bff53123df9377b114cadeac874)
+++ c/src/lib/libbsp/powerpc/haleakala/startup/linkcmds	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -230,4 +230,6 @@
     intrStack = .;
     PROVIDE(intrStackPtr = intrStack);
+    PROVIDE(intrStack_start = IntrStack_start);
+    PROVIDE(intrStack_size = kIntrStackSize);
 
  	/* Main stack: align to a cache-line boundary */
Index: c/src/lib/libbsp/powerpc/mpc55xxevb/ChangeLog
===================================================================
--- c/src/lib/libbsp/powerpc/mpc55xxevb/ChangeLog	(revision 574fb675105b77dfe9598915207f1f32790f905f)
+++ c/src/lib/libbsp/powerpc/mpc55xxevb/ChangeLog	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -0,0 +1,7 @@
+2008-07-14     Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+	* bsp_specs, configure.ac, include/bsp.h, include/irq-config.h,
+	include/mpc55xxevb.h, Makefile.am, network/network.c, preinstall.am,
+	README, startup/bspclean.c, startup/bspstart.c, startup/linkcmds,
+	startup/linkcmds.memory, startup/sd-card-init.c, startup/start.S,
+	tests/tests.c: New files.
Index: c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am
===================================================================
--- c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am	(revision 574fb675105b77dfe9598915207f1f32790f905f)
+++ c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -0,0 +1,104 @@
+##
+#
+# @file
+#
+# @ingroup mpc55xx_config
+#
+# @brief Makefile of LibBSP for the MPC55xx evaluation boards.
+#
+
+ACLOCAL_AMFLAGS = -I ../../../../aclocal
+
+include $(top_srcdir)/../../../../automake/compile.am
+include $(top_srcdir)/../../bsp.am
+
+libcpudir = ../../../libcpu/@RTEMS_CPU@
+
+DISTCLEANFILES = include/bspopts.h
+
+# Compiler specs
+dist_project_lib_DATA = bsp_specs
+
+# Object files
+EXTRA_DIST = startup/start.S
+start.$(OBJEXT): startup/start.S
+	$(CPPASCOMPILE) -o $@ -c $<
+project_lib_DATA = start.$(OBJEXT)
+
+EXTRA_DIST += ../shared/start/rtems_crti.S
+rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S
+	$(CPPASCOMPILE) -o $@ -c $<
+project_lib_DATA += rtems_crti.$(OBJEXT)
+
+# Link commands
+dist_project_lib_DATA += startup/linkcmds startup/linkcmds.memory
+
+# Includes
+include_HEADERS = include/bsp.h
+
+nodist_include_HEADERS = include/bspopts.h ../../shared/tod.h
+include_bspdir = $(includedir)/bsp
+include_bsp_HEADERS = include/mpc55xxevb.h \
+	include/irq-config.h \
+	../../shared/include/irq-generic.h \
+	../shared/include/tictac.h
+
+# BSP library
+noinst_LIBRARIES = libbsp.a
+libbsp_a_SOURCES =
+libbsp_a_LIBADD = $(libcpudir)/shared/cpuIdent.rel \
+	$(libcpudir)/shared/cache.rel \
+	$(libcpudir)/shared/stack.rel \
+	$(libcpudir)/@RTEMS_CPU_MODEL@/misc.rel \
+	$(libcpudir)/@RTEMS_CPU_MODEL@/irq.rel \
+	$(libcpudir)/@RTEMS_CPU_MODEL@/edma.rel \
+	$(libcpudir)/@RTEMS_CPU_MODEL@/dspi.rel \
+	$(libcpudir)/@RTEMS_CPU_MODEL@/esci.rel \
+	$(libcpudir)/@exceptions@/rtems-cpu.rel \
+	$(libcpudir)/@exceptions@/raw_exception.rel \
+	$(libcpudir)/@exceptions@/exc_bspsupport.rel
+
+# Startup
+noinst_PROGRAMS = startup.rel
+startup_rel_SOURCES = ../../shared/bsplibc.c \
+	../../shared/bsppost.c \
+	../../shared/bootcard.c \
+	../shared/src/tictac.c \
+	startup/bspclean.c \
+	startup/bspstart.c
+startup_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+libbsp_a_LIBADD += startup.rel
+
+# Clock
+noinst_PROGRAMS += clock.rel
+clock_rel_SOURCES = ../shared/clock/clock.c
+clock_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+libbsp_a_LIBADD += clock.rel
+
+# IRQ
+noinst_PROGRAMS += irq-generic.rel
+irq_generic_rel_SOURCES = ../../shared/src/irq-generic.c \
+	../../shared/src/irq-legacy.c
+irq_generic_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+libbsp_a_LIBADD += irq-generic.rel
+
+# Tests
+noinst_PROGRAMS += tests.rel
+tests_rel_SOURCES = tests/tests.c \
+	startup/sd-card-init.c
+tests_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+libbsp_a_LIBADD += tests.rel
+
+# Network
+if HAS_NETWORKING
+noinst_PROGRAMS += network.rel
+network_rel_SOURCES = network/network.c
+network_rel_CPPFLAGS = $(AM_CPPFLAGS) -D__INSIDE_RTEMS_BSD_TCPIP_STACK__ -D__BSD_VISIBLE
+network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+libbsp_a_LIBADD += network.rel
+endif
+
+include $(srcdir)/preinstall.am
+include $(top_srcdir)/../../../../automake/local.am
+
+BUILT_SOURCES = preinstall
Index: c/src/lib/libbsp/powerpc/mpc55xxevb/README
===================================================================
--- c/src/lib/libbsp/powerpc/mpc55xxevb/README	(revision 574fb675105b77dfe9598915207f1f32790f905f)
+++ c/src/lib/libbsp/powerpc/mpc55xxevb/README	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -0,0 +1,64 @@
+OVERVIEW
+========
+
+BSP NAME:           mpc55xxevb
+BOARD:              Freescale MPC5566 evaluation board MPC5566EVB
+BUS:                N/A
+CPU FAMILY:         ppc
+CPU:                PowerPC e200z6
+COPROCESSORS:       N/A
+MODE:               32 bit mode
+DEBUG MONITOR:      BAM
+
+PERIPHERALS
+===========
+
+TIMERS:             not yet supported
+  RESOLUTION:       not yet supported
+SERIAL PORTS:       2 internal eSCI
+REAL-TIME CLOCK:    N/A
+DMA:                eDMA
+VIDEO:              N/A
+SCSI:               N/A
+NETWORKING:         FEC (not yet supported)
+SPI:                DSPI
+
+DRIVER INFORMATION
+==================
+
+CLOCK DRIVER:       Book E decrementer
+IOSUPP DRIVER:      N/A
+SHMSUPP:            N/A
+TIMER DRIVER:       not yet supported
+TTY DRIVER:         BSP
+
+STDIO
+=====
+
+PORT:               ESCI A
+ELECTRICAL:         N/A
+BAUD:               115200
+BITS PER CHARACTER: 8
+PARITY:             N
+STOP BITS:          1
+
+NOTES
+=====
+
+BUS WIDTH:          32 bit Flash, 32 bit SDRAM
+FLASH:              3 MByte
+RAM:                128 kByte SDRAM 
+EXTERNAL RAM:       512 kByte SDRAM 
+
+
+DEBUGGING / CODE LOADING
+========================
+
+Tested using the Lauterbach TRACE32 ICD debugger.
+
+ISSUES
+======
+
+The memory blocks allocated by LibBlock are in general not cache aligned so we
+cannot use DMA transfers.  This is suboptimal in combination with a SD Card and
+SPI.
Index: c/src/lib/libbsp/powerpc/mpc55xxevb/bsp_specs
===================================================================
--- c/src/lib/libbsp/powerpc/mpc55xxevb/bsp_specs	(revision 574fb675105b77dfe9598915207f1f32790f905f)
+++ c/src/lib/libbsp/powerpc/mpc55xxevb/bsp_specs	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -0,0 +1,14 @@
+%rename endfile old_endfile
+%rename startfile old_startfile
+%rename link old_link
+
+*startfile:
+%{!qrtems: %(old_startfile)} %{!nostdlib: %{qrtems:  ecrti%O%s rtems_crti%O%s \
+%{!qrtems_debug: start.o%s} \
+%{qrtems_debug: start_g.o%s}}}
+
+*endfile:
+%{!qrtems: %(old_endfile)} %{qrtems: ecrtn.o%s}
+
+*link:
+%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N -u start -e start}
Index: c/src/lib/libbsp/powerpc/mpc55xxevb/configure.ac
===================================================================
--- c/src/lib/libbsp/powerpc/mpc55xxevb/configure.ac	(revision 574fb675105b77dfe9598915207f1f32790f905f)
+++ c/src/lib/libbsp/powerpc/mpc55xxevb/configure.ac	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -0,0 +1,53 @@
+##
+#
+# @file
+#
+# @ingroup mpc55xx_config
+#
+# @brief Configure script of LibBSP for the MPC55xx evaluation boards.
+#
+
+AC_PREREQ(2.60)
+AC_INIT([rtems-c-src-lib-libbsp-powerpc-mpc55xxevb],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla])
+AC_CONFIG_SRCDIR([bsp_specs])
+RTEMS_TOP(../../../../../..)
+
+RTEMS_CANONICAL_TARGET_CPU
+AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.10])
+RTEMS_BSP_CONFIGURE
+
+RTEMS_AMPOLISH3
+RTEMS_PROG_CC_FOR_TARGET([-fasm])
+RTEMS_CANONICALIZE_TOOLS
+RTEMS_PROG_CCAS
+
+RTEMS_CHECK_NETWORKING
+AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
+
+RTEMS_BSPOPTS_SET([UARTS_USE_TERMIOS],[*],[0])
+RTEMS_BSPOPTS_HELP([UARTS_USE_TERMIOS],
+[Define to 1 if you want termios support for every port.
+ Termios support is independent of the choice of UART I/O mode.])
+
+RTEMS_BSPOPTS_SET([CONSOLE_MINOR],[*],[MPC55XX_ESCI_A_MINOR])
+RTEMS_BSPOPTS_HELP([CONSOLE_MINOR],
+[Must be defined to be one of MPC55XX_ESCI_A_MINOR or MPC55XX_ESCI_B_MINOR.  Determines which
+ device will be registered as /dev/console.])
+
+RTEMS_BSPOPTS_SET([UARTS_IO_MODE],[*],[0])
+RTEMS_BSPOPTS_HELP([UARTS_IO_MODE],
+[Define to 1 if you want interrupt-driven I/O for the SCI ports.])
+
+RTEMS_BSPOPTS_SET([PRINTK_MINOR],[*],[MPC55XX_ESCI_B_MINOR])
+RTEMS_BSPOPTS_HELP([PRINTK_MINOR],
+[Must be defined to be one of MPC55XX_ESCI_A_MINOR or MPC55XX_ESCI_B_MINOR.  Determines which
+ device is used for output by printk().  The printk port always uses polled
+ I/O.  Don't open the printk port from RTEMS unless also using polled I/O
+ for the SCI ports.])
+
+AC_CONFIG_FILES([Makefile
+include/bspopts.h])
+
+RTEMS_PPC_EXCEPTIONS
+
+AC_OUTPUT
Index: c/src/lib/libbsp/powerpc/mpc55xxevb/include/bsp.h
===================================================================
--- c/src/lib/libbsp/powerpc/mpc55xxevb/include/bsp.h	(revision 574fb675105b77dfe9598915207f1f32790f905f)
+++ c/src/lib/libbsp/powerpc/mpc55xxevb/include/bsp.h	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -0,0 +1,54 @@
+/**
+ * @file
+ *
+ * @ingroup mpc55xx
+ *
+ * @brief Global BSP variables and functions
+ */
+
+/*
+ * Copyright (c) 2008
+ * Embedded Brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * rtems@embedded-brains.de
+ *
+ * The license and distribution terms for this file may be found in the file
+ * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_POWERPC_BSP_H
+#define LIBBSP_POWERPC_BSP_H
+
+#include <stdint.h>
+
+#include <rtems.h>
+#include <rtems/console.h>
+#include <rtems/clockdrv.h>
+
+#include <bspopts.h>
+
+#include <bsp/tictac.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#ifndef ASM
+
+/** @brief System clock frequency */
+extern unsigned int bsp_clock_speed;
+
+/** @brief Time base clicks per micro second */
+extern uint32_t bsp_clicks_per_usec;
+
+rtems_status_code mpc55xx_sd_card_init();
+
+#endif /* ASM */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_POWERPC_BSP_H */
Index: c/src/lib/libbsp/powerpc/mpc55xxevb/include/irq-config.h
===================================================================
--- c/src/lib/libbsp/powerpc/mpc55xxevb/include/irq-config.h	(revision 574fb675105b77dfe9598915207f1f32790f905f)
+++ c/src/lib/libbsp/powerpc/mpc55xxevb/include/irq-config.h	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -0,0 +1,76 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief BSP interrupt support configuration.
+ */
+
+/*
+ * Copyright (c) 2008
+ * Embedded Brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * rtems@embedded-brains.de
+ *
+ * The license and distribution terms for this file may be found in the file
+ * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_POWERPC_MPC55XXEVB_IRQ_CONFIG_H
+#define LIBBSP_POWERPC_MPC55XXEVB_IRQ_CONFIG_H
+
+#include <stdint.h>
+
+/**
+ * @addtogroup bsp_interrupt
+ *
+ * @{
+ */
+
+/**
+ * @brief Minimum vector number.
+ */
+#define BSP_INTERRUPT_VECTOR_MIN 0
+
+/**
+ * @brief Maximum vector number.
+ */
+#define BSP_INTERRUPT_VECTOR_MAX 328
+
+/**
+ * @brief Enables the index table.
+ *
+ * If you enable the index table, you have to define a size for the handler
+ * table (@ref BSP_INTERRUPT_HANDLER_TABLE_SIZE) and must provide an integer
+ * type capable to index the complete handler table (@ref
+ * bsp_interrupt_handler_index_type).
+ */
+#define BSP_INTERRUPT_USE_INDEX_TABLE
+
+/**
+ * @brief Disables usage of the heap.
+ *
+ * If you define this, you have to define @ref BSP_INTERRUPT_USE_INDEX_TABLE as
+ * well.
+ */
+#define BSP_INTERRUPT_NO_HEAP_USAGE
+
+#ifdef BSP_INTERRUPT_USE_INDEX_TABLE
+
+/**
+ * @brief Size of the handler table.
+ */
+#define BSP_INTERRUPT_HANDLER_TABLE_SIZE 63
+
+/**
+ * @brief Integer type capable to index the complete handler table.
+ */
+typedef uint8_t bsp_interrupt_handler_index_type;
+
+#endif /* BSP_INTERRUPT_USE_INDEX_TABLE */
+
+/** @} */
+
+#endif /* LIBBSP_POWERPC_MPC55XXEVB_IRQ_CONFIG_H */
Index: c/src/lib/libbsp/powerpc/mpc55xxevb/include/mpc55xxevb.h
===================================================================
--- c/src/lib/libbsp/powerpc/mpc55xxevb/include/mpc55xxevb.h	(revision 574fb675105b77dfe9598915207f1f32790f905f)
+++ c/src/lib/libbsp/powerpc/mpc55xxevb/include/mpc55xxevb.h	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -0,0 +1,28 @@
+/**
+ * @file
+ *
+ * @ingroup mpc55xx
+ *
+ * @brief Documentation for this file
+ *
+ * More details.
+ * 
+ * @par Copyright
+ * Copyright (c) 2008<br>
+ * Embedded Brains GmbH<br>
+ * Obere Lagerstr. 30<br>
+ * D-82178 Puchheim<br>
+ * Germany<br>
+ * rtems@embedded-brains.de<br>
+ *
+ * @par License
+ * The license and distribution terms for this file may be found in the file
+ * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_POWERPC_MPC55XXEVB_H
+#define LIBBSP_POWERPC_MPC55XXEVB_H
+
+/* TODO */
+
+#endif /* LIBBSP_POWERPC_MPC55XXEVB_H */
Index: c/src/lib/libbsp/powerpc/mpc55xxevb/network/network.c
===================================================================
--- c/src/lib/libbsp/powerpc/mpc55xxevb/network/network.c	(revision 574fb675105b77dfe9598915207f1f32790f905f)
+++ c/src/lib/libbsp/powerpc/mpc55xxevb/network/network.c	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -0,0 +1,21 @@
+/**
+ * @file
+ *
+ * @ingroup mpc55xx
+ *
+ * @brief Documentation for this file
+ *
+ * More details.
+ * 
+ * @par Copyright
+ * Copyright (c) 2008<br>
+ * Embedded Brains GmbH<br>
+ * Obere Lagerstr. 30<br>
+ * D-82178 Puchheim<br>
+ * Germany<br>
+ * rtems@embedded-brains.de<br>
+ *
+ * @par License
+ * The license and distribution terms for this file may be found in the file
+ * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
+ */
Index: c/src/lib/libbsp/powerpc/mpc55xxevb/startup/bspclean.c
===================================================================
--- c/src/lib/libbsp/powerpc/mpc55xxevb/startup/bspclean.c	(revision 574fb675105b77dfe9598915207f1f32790f905f)
+++ c/src/lib/libbsp/powerpc/mpc55xxevb/startup/bspclean.c	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -0,0 +1,24 @@
+/**
+ * @file
+ *
+ * @ingroup mpc55xx
+ *
+ * @brief BSP cleanup code
+ */
+
+/*
+ * Copyright (c) 2008
+ * Embedded Brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * rtems@embedded-brains.de
+ *
+ * The license and distribution terms for this file may be found in the file
+ * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
+ */
+
+void bsp_cleanup()
+{
+	// TODO
+}
Index: c/src/lib/libbsp/powerpc/mpc55xxevb/startup/bspstart.c
===================================================================
--- c/src/lib/libbsp/powerpc/mpc55xxevb/startup/bspstart.c	(revision 574fb675105b77dfe9598915207f1f32790f905f)
+++ c/src/lib/libbsp/powerpc/mpc55xxevb/startup/bspstart.c	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -0,0 +1,263 @@
+/**
+ * @file
+ *
+ * @ingroup mpc55xx
+ *
+ * @brief BSP startup code.
+ */
+
+/*
+ * Copyright (c) 2008
+ * Embedded Brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * rtems@embedded-brains.de
+ *
+ * The license and distribution terms for this file may be found in the file
+ * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
+ */
+
+#include <mpc55xx/mpc55xx.h>
+#include <mpc55xx/regs.h>
+#include <mpc55xx/edma.h>
+
+#include <rtems.h>
+#include <rtems/bspIo.h>
+#include <rtems/libcsupport.h>
+
+#include <libcpu/powerpc-utility.h>
+
+#include <bsp.h>
+#include <bsp/irq.h>
+#include <bsp/irq-generic.h>
+#include <bsp/ppc_exc_bspsupp.h>
+
+#define RTEMS_STATUS_CHECKS_USE_PRINTK
+
+#include <rtems/status-checks.h>
+
+#define DEBUG_DONE() DEBUG_PRINT( "Done\n")
+
+#define MPC55XX_INTERRUPT_STACK_SIZE 0x1000
+
+/* Symbols defined in linker command file */
+LINKER_SYMBOL( bsp_ram_start);
+LINKER_SYMBOL( bsp_ram_end);
+LINKER_SYMBOL( bsp_external_ram_start);
+LINKER_SYMBOL( bsp_external_ram_size);
+LINKER_SYMBOL( bsp_section_bss_end);
+
+unsigned int bsp_clock_speed = 0;
+
+uint32_t bsp_clicks_per_usec = 0;
+
+void BSP_panic( char *s)
+{
+	rtems_interrupt_level level;
+
+	rtems_interrupt_disable( level);
+
+	printk( "%s PANIC %s\n", _RTEMS_version, s);
+
+	while (1) {
+		/* Do nothing */
+	}
+}
+
+void _BSP_Fatal_error( unsigned n)
+{
+	rtems_interrupt_level level;
+
+	rtems_interrupt_disable( level);
+
+	printk( "%s PANIC ERROR %u\n", _RTEMS_version, n);
+
+	while (1) {
+		/* Do nothing */
+	}
+}
+
+void bsp_pretasking_hook()
+{
+	uint32_t heap_start = bsp_external_ram_start;
+	uint32_t heap_size = bsp_external_ram_size;
+
+	bsp_libc_init( heap_start, heap_size, 0);
+
+#ifdef STACK_CHECKER_ON
+	Stack_check_Initialize();
+#endif
+
+#ifdef RTEMS_DEBUG
+	rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
+#endif
+}
+
+void bsp_predriver_hook()
+{
+	rtems_status_code sc = RTEMS_SUCCESSFUL;
+
+	DEBUG_PRINT( "Initialize eDMA ...\n");
+	sc = mpc55xx_edma_init();
+	if (sc != RTEMS_SUCCESSFUL) {
+		BSP_panic( "Cannot initialize eDMA");
+	} else {
+		DEBUG_DONE();
+	}
+}
+
+static void mpc55xx_ebi_init()
+{
+	struct EBI_CS_tag cs = { BR : MPC55XX_ZERO_FLAGS, OR : MPC55XX_ZERO_FLAGS };
+	union SIU_PCR_tag pcr = MPC55XX_ZERO_FLAGS;
+	int i = 0;
+
+	/* External SRAM (0 wait states, 512kB, 4 word burst) */
+	cs.BR.B.BA = 0;
+	cs.BR.B.PS = 1;
+	cs.BR.B.BL = 1;
+	cs.BR.B.WEBS = 0;
+	cs.BR.B.TBDIP = 0;
+	cs.BR.B.BI = 1; /* TODO: Enable burst */
+	cs.BR.B.V = 1;
+
+	cs.OR.B.AM = 0x1fff0;
+	cs.OR.B.SCY = 0;
+	cs.OR.B.BSCY = 0;
+
+	EBI.CS [0] = cs;
+
+	/* !CS [0] */
+	SIU.PCR [0].R = 0x443;
+
+	/* ADDR [8 : 31] */
+	for (i = 4; i < 4 + 24; ++i) {
+		SIU.PCR [i].R = 0x440;
+	}
+
+	/* DATA [0 : 15] */
+	for (i = 28; i < 28 + 16; ++i) {
+		SIU.PCR [i].R = 0x440;
+	}
+
+	/* RD_!WR */
+	SIU.PCR [62].R = 0x443;
+
+	/* !BDIP */
+	SIU.PCR [63].R = 0x443;
+
+	/* !WE [0 : 3] */
+	for (i = 64; i < 64 + 4; ++i) {
+		SIU.PCR [i].R = 0x443;
+	}
+
+	/* !OE */
+	SIU.PCR [68].R = 0x443;
+
+	/* !TS */
+	SIU.PCR [69].R = 0x443;
+}
+
+/**
+ * @brief Start BSP.
+ */
+void bsp_start(void)
+{
+	ppc_cpu_id_t myCpu;
+	ppc_cpu_revision_t myCpuRevision;
+
+	uint32_t ram_start = bsp_ram_start;
+	uint32_t ram_end = bsp_ram_end;
+	uint32_t interrupt_stack_start = ram_end - 2 * MPC55XX_INTERRUPT_STACK_SIZE;
+	uint32_t interrupt_stack_size = MPC55XX_INTERRUPT_STACK_SIZE;
+	uint32_t work_space_start = bsp_section_bss_end;
+	uint32_t work_space_end = work_space_start + rtems_configuration_get_work_space_size();
+
+	/* ESCI pad configuration */
+	SIU.PCR [89].R = 0x400;
+	SIU.PCR [90].R = 0x400;
+
+	DEBUG_PRINT( "BSP start ...\n");
+
+	/* Memory layout */
+
+	Configuration.work_space_start = work_space_start;
+
+	DEBUG_PRINT( "System clock          : %i\n", mpc55xx_get_system_clock());
+	DEBUG_PRINT( "Memory start          : 0x%08x\n", ram_start);
+	DEBUG_PRINT( "Memory end            : 0x%08x\n", ram_end);
+	DEBUG_PRINT( "Memory size           : 0x%08x\n", ram_end - ram_start);
+	DEBUG_PRINT( "Work space start      : 0x%08x\n", work_space_start);
+	DEBUG_PRINT( "Work space end        : 0x%08x\n", work_space_end);
+	DEBUG_PRINT( "Work space size       : 0x%08x\n", work_space_end - work_space_start);
+	DEBUG_PRINT( "Interrupt stack start : 0x%08x\n", interrupt_stack_start);
+	DEBUG_PRINT( "Interrupt stack end   : 0x%08x\n", interrupt_stack_start + interrupt_stack_size);
+	DEBUG_PRINT( "Interrupt stack size  : 0x%08x\n", interrupt_stack_size);
+
+	if (work_space_end > interrupt_stack_start) {
+		BSP_panic( "Not enough memory for the work space");
+	}
+	
+	/*
+	 * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
+	 * function store the result in global variables so that it can be used
+	 * latter...
+	 */
+	myCpu = get_ppc_cpu_type();
+	myCpuRevision = get_ppc_cpu_revision();
+	
+	/* Time reference value */
+	bsp_clicks_per_usec = bsp_clock_speed / 1000000;
+
+	/* Initialize External Bus Interface */
+	mpc55xx_ebi_init();
+	
+	/* Initialize exceptions */
+	DEBUG_PRINT( "Initialize exceptions ...\n");
+	ppc_exc_initialize( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, interrupt_stack_start, interrupt_stack_size);
+	DEBUG_DONE();
+
+	/* Initialize interrupts */
+	DEBUG_PRINT( "Initialize interrupts ...\n");
+	if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) {
+		BSP_panic( "Cannot initialize interrupts");
+	} else {
+		DEBUG_DONE();
+	}
+	
+	DEBUG_PRINT( "BSP start done\n");
+
+	return;
+
+	/* TODO */
+	/*
+	* Enable instruction and data caches. Do not force writethrough mode.
+	*/
+#if INSTRUCTION_CACHE_ENABLE
+	rtems_cache_enable_instruction();
+#endif
+#if DATA_CACHE_ENABLE
+	rtems_cache_enable_data();
+#endif
+}
+
+/**
+ * @brief Idle thread body.
+ */
+Thread _Thread_Idle_body( uint32_t ignored)
+{
+
+	while (1) {
+		asm volatile(
+			"mfmsr 3;"
+			"oris 3,3,4;"
+			"sync;"
+			"mtmsr 3;"
+			"isync;"
+			"ori 3,3,0;"
+			"ori 3,3,0"
+		);
+	}
+	return 0;
+}
Index: c/src/lib/libbsp/powerpc/mpc55xxevb/startup/linkcmds
===================================================================
--- c/src/lib/libbsp/powerpc/mpc55xxevb/startup/linkcmds	(revision 574fb675105b77dfe9598915207f1f32790f905f)
+++ c/src/lib/libbsp/powerpc/mpc55xxevb/startup/linkcmds	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -0,0 +1,278 @@
+/**
+ * @file
+ *
+ * Derived from internal linker script of GNU ld (GNU Binutils) 2.18 for elf32ppc emulation.
+ */
+
+OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc", "elf32-powerpc")
+OUTPUT_ARCH(powerpc)
+ENTRY(start)
+
+INCLUDE linkcmds.memory
+
+SECTIONS
+{
+	.text : {
+		/*
+		 * BSP: Start of text section
+		 */
+		bsp_section_text_start = .;
+
+		/*
+		 * BSP: System startup entry
+		 */
+		KEEP (*(.entry))
+
+		/*
+		 * BSP: Moved into .text from .init
+		 */
+		KEEP (*(.init))
+
+		*(.text .stub .text.* .gnu.linkonce.t.*)
+		KEEP (*(.text.*personality*))
+		/* .gnu.warning sections are handled specially by elf32.em.  */
+		*(.gnu.warning)
+		*(.glink)
+		
+		/*
+		 * BSP: Special FreeBSD sysctl sections
+		 */
+		. = ALIGN (16);
+		__start_set_sysctl_set = .;
+		*(set_sysctl_*);
+		__stop_set_sysctl_set = ABSOLUTE(.);
+		*(set_domain_*);
+		*(set_pseudo_*);
+
+		/*
+		 * BSP: Moved into .text from .*
+		 */
+		*(.rodata .rodata.* .gnu.linkonce.r.*)
+		*(.rodata1)
+		*(.interp)
+		*(.note.gnu.build-id)
+		*(.hash)
+		*(.gnu.hash)
+		*(.dynsym)
+		*(.dynstr)
+		*(.gnu.version)
+		*(.gnu.version_d)
+		*(.gnu.version_r)
+		*(.eh_frame_hdr)
+
+		/*
+		 * BSP: Magic PPC stuff
+		 */
+		*(.PPC.*)
+
+		/*
+		 * BSP: Required by cpukit/score/src/threadhandler.c
+		 */
+		PROVIDE (_fini = .);
+
+		/*
+		 * BSP: Moved into .text from .fini
+		 */
+		KEEP (*(.fini))
+
+		. = ALIGN (bsp_section_align);
+
+		PROVIDE (__etext = .);
+		PROVIDE (_etext = .);
+		PROVIDE (etext = .);
+	} > ROM =0
+
+	.sdata2 : {
+		PROVIDE (_SDA2_BASE_ = 32768);
+
+		*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
+
+		. = ALIGN (bsp_section_align);
+	} > ROM =0
+
+	.sbss2 : {
+		*(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)
+
+		. = ALIGN (bsp_section_align);
+
+		/*
+		 * BSP: End of text section
+		 */
+		bsp_section_text_end = .;
+	} > ROM =0
+
+	.data : AT (bsp_section_text_end) {
+		/*
+		 * BSP: Start of data section
+		 */
+		bsp_section_data_start = .;
+
+		/*
+		 * BSP: Reserve space for exception handler
+		 */
+		. = . + 0x180;
+
+		/*
+		 * BSP: Moved into .data from .ctors
+		 */
+		/* gcc uses crtbegin.o to find the start of
+		   the constructors, so we make sure it is
+		   first.  Because this is a wildcard, it
+		   doesn't matter if the user does not
+		   actually link against crtbegin.o; the
+		   linker won't look for a file to match a
+		   wildcard.  The wildcard also means that it
+		   doesn't matter which directory crtbegin.o
+		   is in.  */
+		KEEP (*crtbegin.o(.ctors))
+		KEEP (*crtbegin?.o(.ctors))
+		/* We don't want to include the .ctor section from
+		   the crtend.o file until after the sorted ctors.
+		   The .ctor section from the crtend file contains the
+		   end of ctors marker and it must be last */
+		KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+		KEEP (*(SORT(.ctors.*)))
+		KEEP (*(.ctors))
+
+		/*
+		 * BSP: Moved into .data from .dtors
+		 */
+		KEEP (*crtbegin.o(.dtors))
+		KEEP (*crtbegin?.o(.dtors))
+		KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+		KEEP (*(SORT(.dtors.*)))
+		KEEP (*(.dtors))
+
+		/*
+		 * BSP: Moved into .data from .*
+		 */
+		*(.tdata .tdata.* .gnu.linkonce.td.*)
+		*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+		*(.data1)
+		KEEP (*(.eh_frame))
+		*(.gcc_except_table .gcc_except_table.*)
+		KEEP (*(.jcr))
+		*(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*)
+		*(.fixup)
+		*(.got1)
+		*(.got2)
+		*(.dynamic)
+		*(.got)
+		*(.plt)
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP (*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP (*(SORT(.init_array.*)))
+		KEEP (*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP (*(.fini_array))
+		KEEP (*(SORT(.fini_array.*)))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		*(.data .data.* .gnu.linkonce.d.*)
+		KEEP (*(.gnu.linkonce.d.*personality*))
+		SORT(CONSTRUCTORS)
+
+		. = ALIGN (bsp_section_align);
+	} > RAM
+
+	.sdata : {
+		PROVIDE (_SDA_BASE_ = 32768);
+		*(.sdata .sdata.* .gnu.linkonce.s.*)
+
+		. = ALIGN (bsp_section_align);
+
+		_edata = .;
+		PROVIDE (edata = .);
+
+		/*
+		 * BSP: End of data section
+		 */
+		bsp_section_data_end = .;
+	} > RAM
+
+	.sbss : {
+		/*
+		 * BSP: Start of bss section
+		 */
+		bsp_section_bss_start = .;
+
+		__bss_start = .;
+
+		PROVIDE (__sbss_start = .); PROVIDE (___sbss_start = .);
+		*(.scommon)
+		*(.dynsbss)
+		*(.sbss .sbss.* .gnu.linkonce.sb.*)
+		PROVIDE (__sbss_end = .); PROVIDE (___sbss_end = .);
+
+		. = ALIGN (bsp_section_align);
+	} > RAM
+
+	.bss : {
+		*(COMMON)
+		*(.dynbss)
+		*(.bss .bss.* .gnu.linkonce.b.*)
+
+		. = ALIGN (bsp_section_align);
+
+		__end = .;
+		_end = .;
+		PROVIDE (end = .);
+
+		/*
+		 * BSP: End of bss section
+		 */
+		bsp_section_bss_end = .;
+	} > RAM
+	
+	/* Stabs debugging sections.  */
+	.stab          0 : { *(.stab) }
+	.stabstr       0 : { *(.stabstr) }
+	.stab.excl     0 : { *(.stab.excl) }
+	.stab.exclstr  0 : { *(.stab.exclstr) }
+	.stab.index    0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment       0 : { *(.comment) }
+	/* DWARF debug sections.
+	   Symbols in the DWARF debugging sections are relative to the beginning
+	   of the section so we begin them at 0.  */
+	/* DWARF 1 */
+	.debug          0 : { *(.debug) }
+	.line           0 : { *(.line) }
+	/* GNU DWARF 1 extensions */
+	.debug_srcinfo  0 : { *(.debug_srcinfo) }
+	.debug_sfnames  0 : { *(.debug_sfnames) }
+	/* DWARF 1.1 and DWARF 2 */
+	.debug_aranges  0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	/* DWARF 2 */
+	.debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+	.debug_abbrev   0 : { *(.debug_abbrev) }
+	.debug_line     0 : { *(.debug_line) }
+	.debug_frame    0 : { *(.debug_frame) }
+	.debug_str      0 : { *(.debug_str) }
+	.debug_loc      0 : { *(.debug_loc) }
+	.debug_macinfo  0 : { *(.debug_macinfo) }
+	/* SGI/MIPS DWARF 2 extensions */
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames  0 : { *(.debug_varnames) }
+	/* DWARF 3 */
+	.debug_pubtypes 0 : { *(.debug_pubtypes) }
+	.debug_ranges   0 : { *(.debug_ranges) }
+	.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
+
+	/DISCARD/ : {
+		*(.note.GNU-stack) *(.gnu_debuglink)
+	}
+
+	/*
+	 * BSP: Catch all unknown sections
+	 */
+	.nirvana : {
+		*(*)
+	} > NIRVANA
+}
Index: c/src/lib/libbsp/powerpc/mpc55xxevb/startup/linkcmds.memory
===================================================================
--- c/src/lib/libbsp/powerpc/mpc55xxevb/startup/linkcmds.memory	(revision 574fb675105b77dfe9598915207f1f32790f905f)
+++ c/src/lib/libbsp/powerpc/mpc55xxevb/startup/linkcmds.memory	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -0,0 +1,21 @@
+MEMORY
+{
+	ROM (RX) : ORIGIN = 0x0, LENGTH = 3M
+	RAM (AIW) : ORIGIN = 0x40000000, LENGTH = 128K
+	EXT_RAM : ORIGIN = 0x20000000, LENGTH = 512K
+	NIRVANA : ORIGIN = 0x0, LENGTH = 0
+}
+
+bsp_ram_start = ORIGIN (RAM);
+bsp_ram_end = ORIGIN (RAM) + LENGTH (RAM);
+bsp_ram_size = LENGTH (RAM);
+
+bsp_rom_start = ORIGIN (ROM);
+bsp_rom_end = ORIGIN (ROM) + LENGTH (ROM);
+bsp_rom_size = LENGTH (ROM);
+
+bsp_external_ram_start = ORIGIN (EXT_RAM);
+bsp_external_ram_end = ORIGIN (EXT_RAM) + LENGTH (EXT_RAM);
+bsp_external_ram_size = LENGTH (EXT_RAM);
+
+bsp_section_align = 32;
Index: c/src/lib/libbsp/powerpc/mpc55xxevb/startup/sd-card-init.c
===================================================================
--- c/src/lib/libbsp/powerpc/mpc55xxevb/startup/sd-card-init.c	(revision 574fb675105b77dfe9598915207f1f32790f905f)
+++ c/src/lib/libbsp/powerpc/mpc55xxevb/startup/sd-card-init.c	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -0,0 +1,149 @@
+#include  <stdio.h>
+
+#include <mpc55xx/mpc55xx.h>
+#include <mpc55xx/regs.h>
+#include <mpc55xx/dspi.h>
+
+#include <libchip/spi-sd-card.h>
+
+#define DEBUG
+
+#include <rtems/status-checks.h>
+
+#include <bsp.h>
+
+static rtems_status_code mpc55xx_dspi_init()
+{
+	int rv = 0;
+	int i = 0;
+	char device_name [] = "/dev/spi0";
+	union SIU_PCR_tag pcr = MPC55XX_ZERO_FLAGS;
+
+	rv = rtems_libi2c_initialize();
+	CHECK_RVSC( rv, "rtems_libi2c_initialize");
+
+	/* DSPI D inputs are taken from DSPI C */
+	SIU.DISR.R = 0x000000FC;
+
+	/* DSPI A signals */
+	pcr.B.PA = 1;
+	pcr.B.ODE = 0;
+	pcr.B.HYS = 0;
+	pcr.B.SRC = 3;
+	pcr.B.WPE = 1;
+	pcr.B.WPS = 1;
+
+	/* SCK */
+	pcr.B.OBE = 1;
+	pcr.B.IBE = 0;
+	SIU.PCR [93].R = pcr.R;
+
+	/* SIN */
+	pcr.B.OBE = 0;
+	pcr.B.IBE = 1;
+	SIU.PCR [94].R = pcr.R;
+
+	/* SOUT */
+	pcr.B.OBE = 1;
+	pcr.B.IBE = 0;
+	SIU.PCR [95].R = pcr.R;
+
+	/* PCSx */
+	pcr.B.OBE = 1;
+	pcr.B.IBE = 0;
+	SIU.PCR [96].R = pcr.R;
+	SIU.PCR [97].R = pcr.R;
+	SIU.PCR [98].R = pcr.R;
+	SIU.PCR [99].R = pcr.R;
+	SIU.PCR [100].R = pcr.R;
+	SIU.PCR [101].R = pcr.R;
+
+	mpc55xx_dspi_bus_table [3].master = 0;
+	for (i = 0; i < MPC55XX_DSPI_NUMBER; ++i) {
+		device_name [8] = '0' + i;
+		rv = rtems_libi2c_register_bus( device_name, (rtems_libi2c_bus_t *) &mpc55xx_dspi_bus_table [i]);
+		CHECK_RVSC( rv, device_name);
+	}
+
+	return RTEMS_SUCCESSFUL;
+}
+
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <dirent.h>
+#include <stdio.h>
+#include <rtems/fsmount.h>
+#include <rtems/dosfs.h>
+#include <rtems/ide_part_table.h>
+#include <rtems/console.h>
+
+#define MPC55XX_DEVICE "sd-card-a"
+#define MPC55XX_DEVICE_FILE "/dev/" MPC55XX_DEVICE
+#define MPC55XX_PARTITION "/dev/sd-card-a1"
+#define MPC55XX_MOUNT_POINT "/mnt"
+
+static fstab_t mpc55xx_fs_table [] = { {
+		MPC55XX_PARTITION, MPC55XX_MOUNT_POINT,
+		&msdos_ops, RTEMS_FILESYSTEM_READ_WRITE,
+		FSMOUNT_MNT_OK | FSMOUNT_MNTPNT_CRTERR | FSMOUNT_MNT_FAILED,
+		FSMOUNT_MNT_OK
+	}, {
+		MPC55XX_DEVICE_FILE, MPC55XX_MOUNT_POINT,
+		&msdos_ops, RTEMS_FILESYSTEM_READ_WRITE,
+		FSMOUNT_MNT_OK | FSMOUNT_MNTPNT_CRTERR | FSMOUNT_MNT_FAILED,
+		0
+	}
+};
+
+#define SD_CARD_NUMBER 1
+
+sd_card_driver_entry sd_card_driver_table [SD_CARD_NUMBER] = { {
+		.driver = {
+			.ops = &sd_card_driver_ops,
+			.size = sizeof( sd_card_driver_entry)
+		},
+		.table_index = 0,
+		.minor = 0,
+		.device_name = "sd-card-a",
+		.disk_device_name = "/dev/sd-card-a",
+		.transfer_mode = SD_CARD_TRANSFER_MODE_DEFAULT,
+		.command = SD_CARD_COMMAND_DEFAULT,
+		/* response : whatever, */
+		.response_index = SD_CARD_COMMAND_SIZE,
+		.n_ac_max = SD_CARD_N_AC_MAX_DEFAULT,
+		.block_number = 0,
+		.block_size = 0,
+		.block_size_shift = 0,
+		.busy = 1,
+		.verbose = 1,
+		.schedule_if_busy = 0,
+	}
+};
+
+rtems_status_code mpc55xx_sd_card_init()
+{
+	rtems_status_code sc = RTEMS_SUCCESSFUL;
+	int rv = 0;
+	sd_card_driver_entry *e = &sd_card_driver_table [0];
+
+	DEBUG_PRINT( "Task started\n");
+
+	sc = mpc55xx_dspi_init();
+	CHECK_SC( rv, "Intitalize DSPI bus");
+
+	rv = rtems_libi2c_register_drv( e->device_name, (rtems_libi2c_drv_t *) e, mpc55xx_dspi_bus_table [0].bus_number, 0);
+	CHECK_RVSC( rv, "Register SD Card driver");
+
+	sc = rtems_ide_part_table_initialize( MPC55XX_DEVICE_FILE);
+	CHECK_SC( sc, "Initialize IDE partition table");
+
+	rv = mkdir( MPC55XX_MOUNT_POINT, S_IRWXU);
+	CHECK_RVSC( rv, "Create mount point");
+
+	rv = rtems_fsmount( mpc55xx_fs_table, sizeof( mpc55xx_fs_table) / sizeof( mpc55xx_fs_table [0]), NULL);
+	CHECK_RVSC( rv, "Mount file systems");
+
+	return RTEMS_SUCCESSFUL;
+}
Index: c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S
===================================================================
--- c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S	(revision 574fb675105b77dfe9598915207f1f32790f905f)
+++ c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -0,0 +1,272 @@
+/**
+ * @file
+ *
+ * @ingroup mpc55xx_asm
+ *
+ * @brief Boot and system start code.
+ */
+
+/*
+ * Copyright (c) 2008
+ * Embedded Brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * rtems@embedded-brains.de
+ *
+ * The license and distribution terms for this file may be found in the file
+ * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
+ */
+
+/**
+ * @defgroup mpc55xx_asm Assembler files
+ *
+ * @ingroup mpc55xx
+ */
+   
+#include <libcpu/powerpc-utility.h>
+#include <mpc55xx/reg-defs.h>
+
+.section ".entry", "ax"  
+PUBLIC_VAR (start)
+start:
+/*
+ * BAM
+ */
+
+	/* BAM: RCHW */
+	.int 0x5a0000
+
+	/* BAM: Address of start instruction */
+	.int 0x8
+
+/*
+ * Enable time base
+ */
+
+	li r0, 0
+	mtspr TBWU, r0
+	mtspr TBWL, r0
+	mfspr r2, HID0
+	ori r2, r2, 0x4000
+	mtspr HID0, r2
+
+/*
+ * System clock
+ */
+
+	bl SYM (mpc55xx_fmpll_reset_config)
+
+/*
+ * Enable branch prediction
+ */
+
+	LWI r2, BUCSR_BBFI | BUCSR_BPEN
+	mtspr BUCSR, r2
+
+/*
+ * Basics
+ */
+
+	/* Set stack start to end of ram */
+	LA r1, bsp_ram_end
+	addi r1, r1, -8
+
+	/* Enable SPE */
+	mfmsr r2
+	oris r2, r2, 0x200
+	mtmsr r2
+
+	/* Config internal flash */
+	bl SYM (mpc55xx_flash_config)
+
+	/* FIXME: Config cache */
+	bl config_cache
+
+/*
+ * TODO, FIXME: Enable cache in the MMU for the SRAM
+ */
+
+.equ MAS0, 624
+.equ MAS1, 625
+.equ MAS2, 626
+.equ MAS3, 627
+
+	LWI r3, 0x10030000
+	mtspr MAS0, r3
+	tlbre
+	LWI r4, ~0x00000008
+	mfspr r3, MAS2
+	and r3, r3, r4
+	mtspr MAS2, r3
+	tlbwe
+
+/*
+ * TODO, FIXME: Set MMU for the external SRAM
+ */
+
+	LWI r3, 0x10020000
+	mtspr MAS0, r3
+	tlbre
+	LWI r4, 0xfff
+	mfspr r3, MAS3
+	and r3, r3, r4
+	LWI r4, 0x20000000
+	or r3, r3, r4
+	mtspr MAS3, r3
+	tlbwe
+
+/*
+ * Zero RAM
+ */
+
+	/* Addresses */
+	LA r3, bsp_ram_start
+	LA r4, bsp_ram_end
+
+	/* Assert: Proper alignment of destination start */
+	andi. r6, r3, 0x37
+	bne twiddle
+
+	/* Assert: Proper alignment of destination end */
+	andi. r6, r4, 0x37
+	bne twiddle
+
+	/* Data size = destination end - destination start */
+	subf r4, r3, r4
+
+	/* Save time */
+	mftb r24
+
+	/* Zero */
+	bl SYM (mpc55xx_zero_32)
+
+	/* Save time and get time delta */
+	mftb r25
+	subf r24, r24, r25
+
+/*
+ * Copy data
+ */
+
+	/* Addresses */
+	LA r3, bsp_section_text_end
+	LA r4, bsp_section_data_start
+	LA r5, bsp_section_data_end
+
+	/* Assert: Proper alignment of source start */
+	andi. r6, r3, 0x7
+	bne twiddle
+
+	/* Assert: Proper alignment of destination start */
+	andi. r6, r4, 0x7
+	bne twiddle
+
+	/* Assert: Proper alignment of destination end */
+	andi. r6, r5, 0x7
+	bne twiddle
+
+	/* Data size = destination end - destination start */
+	subf r5, r4, r5
+
+	/* Copy */
+	bl SYM (mpc55xx_copy_8)
+
+	/* Save time and get time delta */
+	mftb r26
+	subf r25, r25, r26
+
+/*
+ * Prepare high level initialization
+ */
+	LA r3, bsp_ram_start
+	LA r4, ppc_exc_vector_base
+	stw r3, 0(r4)
+
+	/* Set global BSP clock speed variable */
+	bl SYM (mpc55xx_get_system_clock)
+	LA r4, bsp_clock_speed
+	stw r3, 0(r4)
+
+	/* Create NULL */
+	li r0, 0
+
+	/* Return address */
+	stw r0, 4(r1)
+
+	/* Back chain */
+	stw r0, 0(r1)
+
+	/* Read-only small data */
+	LA r2, _SDA2_BASE_
+
+	/* Read-write small data */
+	LA r13, _SDA_BASE_
+
+/*
+ * Start RTEMS
+ */
+
+	/* Clear argc and argv */
+        xor r3, r3, r3
+        xor r4, r4, r4
+        
+	/* Start RTEMS */
+        bl SYM (boot_card)
+
+	/* Spin around */
+	b twiddle
+
+.equ L1CSR0, 1010
+.equ L1CSR0_CINV, 0x2
+.equ L1CSR0_CABT, 0x4
+/* FIXME: CORG??? .equ L1CSR0_SETTINGS, 0x00180011 */
+.equ L1CSR0_SETTINGS, 0x00100001
+
+/*
+ * Configure cache
+ */
+config_cache:
+	/* Start cache invalidation */
+	LWI r5, L1CSR0_CINV
+	mtspr L1CSR0, r5
+
+	/* Bit masks to test and clear invalidation abortion (CABT) */
+	LWI r6, L1CSR0_CABT
+	not r7, r6
+
+	/* Wait for cache invalidation to complete */
+check_cache_invalidation:
+	mfspr r9, L1CSR0
+
+	/* Check if the invalidate was aborted */
+	and. r10, r9, r6
+	beq no_chache_invalidation_abort
+
+	/* Clear CABT bit */
+	and r10, r9, r7
+	mtspr L1CSR0, r10
+
+	/* Retry invalidation */
+	b config_cache
+
+no_chache_invalidation_abort:
+	/* Check CINV bit */
+	and. r10, r5, r9
+
+	/* Wait? */
+	bne check_cache_invalidation
+ 
+	/* Enable cache */
+	LWI r6, L1CSR0_SETTINGS
+	mfspr r5, L1CSR0
+	or r5, r5, r6
+	msync
+	isync
+	mtspr L1CSR0, r5
+
+	/* Return */
+	blr   
+
+twiddle:				
+	b	twiddle
Index: c/src/lib/libbsp/powerpc/mpc55xxevb/tests/tests.c
===================================================================
--- c/src/lib/libbsp/powerpc/mpc55xxevb/tests/tests.c	(revision 574fb675105b77dfe9598915207f1f32790f905f)
+++ c/src/lib/libbsp/powerpc/mpc55xxevb/tests/tests.c	(revision 574fb675105b77dfe9598915207f1f32790f905f)
@@ -0,0 +1,674 @@
+#include <stdio.h>
+
+#include <rtems/irq.h>
+
+#include <mpc55xx/regs.h>
+#include <mpc55xx/mpc55xx.h>
+#include <mpc55xx/dspi.h>
+#include <mpc55xx/edma.h>
+
+#include <libchip/spi-sd-card.h>
+
+#include <bsp.h>
+#include <bsp/irq.h>
+
+#include <rtems/irq-extension.h>
+
+#include <libcpu/powerpc-utility.h>
+
+// #define DEBUG
+
+#include <rtems/status-checks.h>
+
+static rtems_driver_address_table test_mpc55xx_drv_ops = {
+	initialization_entry : NULL,
+	open_entry : NULL,
+	close_entry : NULL,
+	read_entry : NULL,
+	write_entry : NULL,
+	control_entry : NULL
+};
+
+static rtems_libi2c_drv_t test_mpc55xx_dspi_drv = {
+	ops : &test_mpc55xx_drv_ops,
+	size : sizeof( rtems_libi2c_drv_t)
+};
+
+#define MPC55XX_TEST_DSPI_ADDRESS 0
+
+// #define MPC55XX_TEST_DSPI_BUFSIZE (16 * 32)
+#define MPC55XX_TEST_DSPI_BUFSIZE 8
+
+// #define MPC55XX_TEST_DSPI_BUFSIZE_CACHE_PROOF MPC55XX_TEST_DSPI_BUFSIZE
+#define MPC55XX_TEST_DSPI_BUFSIZE_CACHE_PROOF 32
+
+rtems_device_minor_number test_mpc55xx_dspi_bus [MPC55XX_DSPI_NUMBER];
+
+static rtems_libi2c_tfr_mode_t test_mpc55xx_dspi_transfer_mode = { baudrate : 550000, bits_per_char : 8, lsb_first : FALSE, clock_inv : FALSE, clock_phs : FALSE };
+
+static rtems_id test_mpc55xx_dspi_ping;
+
+static rtems_id test_mpc55xx_dspi_pong;
+
+static unsigned char test_mpc55xx_dspi_writer_outbuf [2] [MPC55XX_TEST_DSPI_BUFSIZE_CACHE_PROOF] __attribute__ ((aligned (32)));
+
+static unsigned char test_mpc55xx_dspi_writer_inbuf [MPC55XX_TEST_DSPI_BUFSIZE_CACHE_PROOF] __attribute__ ((aligned (32)));
+
+static unsigned char test_mpc55xx_dspi_reader_inbuf [MPC55XX_TEST_DSPI_BUFSIZE_CACHE_PROOF] __attribute__ ((aligned (32)));
+
+static rtems_task test_mpc55xx_dspi_writer( rtems_task_argument arg)
+{
+	rtems_status_code sc = RTEMS_SUCCESSFUL;
+	int rv = 0;
+	rtems_device_minor_number device;
+	rtems_libi2c_read_write_t read_and_write = { rd_buf : NULL, wr_buf : NULL, byte_cnt : 0 };
+	int i = 0;
+
+	DEBUG_PRINT( "Task started\n");
+
+	device = rtems_libi2c_register_drv( NULL, &test_mpc55xx_dspi_drv, test_mpc55xx_dspi_bus [2], 0);
+	CHECK_RV_TASK( device, "rtems_libi2c_register_drv");
+
+	sc = rtems_libi2c_send_start( device);
+	CHECK_SC_TASK( sc, "rtems_libi2c_send_start");
+
+	rv = rtems_libi2c_ioctl( device, RTEMS_LIBI2C_IOCTL_SET_TFRMODE, &test_mpc55xx_dspi_transfer_mode);
+	CHECK_RV_TASK( rv, "rtems_libi2c_ioctl");
+
+	sc = rtems_libi2c_send_addr( device, MPC55XX_TEST_DSPI_ADDRESS);
+	CHECK_SC_TASK( sc, "rtems_libi2c_send_addr");
+	
+	for (i = 0; i < MPC55XX_TEST_DSPI_BUFSIZE; ++i) {
+		test_mpc55xx_dspi_writer_outbuf [0] [i] = 0xa5;
+		test_mpc55xx_dspi_writer_outbuf [1] [i] = 0xa5;
+		// test_mpc55xx_dspi_writer_outbuf [0] [i] = i + 1;
+		// test_mpc55xx_dspi_writer_outbuf [1] [i] = -(i + 1);
+	}
+
+	int toggle = 0;
+	read_and_write.byte_cnt = MPC55XX_TEST_DSPI_BUFSIZE;
+	read_and_write.rd_buf = test_mpc55xx_dspi_writer_inbuf;
+	read_and_write.wr_buf = test_mpc55xx_dspi_writer_outbuf [toggle];
+	while (1) {
+		tic();
+
+		// sc = rtems_semaphore_obtain( test_mpc55xx_dspi_pong, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
+		// CHECK_SC_TASK( sc, "rtems_semaphore_obtain");
+
+		DEBUG_PRINT( "Ping\n");
+
+		// sc = rtems_libi2c_send_start( device);
+		// CHECK_SC_TASK( sc, "rtems_libi2c_send_start");
+
+		// sc = rtems_libi2c_send_addr( device, MPC55XX_TEST_DSPI_ADDRESS);
+		// CHECK_SC_TASK( sc, "rtems_libi2c_send_addr");
+
+		rv = rtems_libi2c_ioctl( device, RTEMS_LIBI2C_IOCTL_READ_WRITE, &read_and_write);
+		CHECK_RV_TASK( rv, "rtems_libi2c_ioctl: RTEMS_LIBI2C_IOCTL_READ_WRITE");
+
+		// rv = rtems_libi2c_write_bytes( device, test_mpc55xx_dspi_writer_outbuf [0], MPC55XX_TEST_DSPI_BUFSIZE);
+		// CHECK_RV_TASK( rv, "rtems_libi2c_write_bytes");
+
+		// sc = rtems_libi2c_send_stop( device);
+		// CHECK_SC_TASK( sc, "rtems_libi2c_send_stop");
+
+		toggle = toggle ? 0 : 1;
+		read_and_write.wr_buf = test_mpc55xx_dspi_writer_outbuf [toggle];
+
+		// sc = rtems_semaphore_release( test_mpc55xx_dspi_ping);
+		// CHECK_SC_TASK( sc, "rtems_semaphore_release");
+	}
+
+	sc = rtems_libi2c_send_stop( device);
+	CHECK_SC_TASK( sc, "rtems_libi2c_send_stop");
+
+	sc = rtems_task_delete( RTEMS_SELF);
+	CHECK_SC_TASK( sc, "rtems_task_delete");
+}
+
+static rtems_task test_mpc55xx_dspi_reader( rtems_task_argument arg)
+{
+	rtems_status_code sc = RTEMS_SUCCESSFUL;
+	int rv = 0;
+	rtems_device_minor_number device;
+	int i = 0;
+
+	DEBUG_PRINT( "Task started\n");
+
+	device = rtems_libi2c_register_drv( NULL, &test_mpc55xx_dspi_drv, test_mpc55xx_dspi_bus [3], 0);
+	CHECK_RV_TASK( device, "rtems_libi2c_register_drv");
+
+	sc = rtems_libi2c_send_start( device);
+	CHECK_SC_TASK( sc, "rtems_libi2c_send_start");
+
+	rv = rtems_libi2c_ioctl( device, RTEMS_LIBI2C_IOCTL_SET_TFRMODE, &test_mpc55xx_dspi_transfer_mode);
+	CHECK_RV_TASK( rv, "rtems_libi2c_ioctl");
+
+	sc = rtems_libi2c_send_addr( device, MPC55XX_TEST_DSPI_ADDRESS);
+	CHECK_SC_TASK( sc, "rtems_libi2c_send_addr");
+	
+	for (i = 0; i < MPC55XX_TEST_DSPI_BUFSIZE; ++i) {
+		test_mpc55xx_dspi_reader_inbuf [i] = -1;
+	}
+
+	sc = rtems_semaphore_obtain( test_mpc55xx_dspi_ping, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
+	CHECK_SC_TASK( sc, "rtems_semaphore_obtain");
+
+	DEBUG_PRINT( "Pong\n");
+
+	sc = rtems_semaphore_release( test_mpc55xx_dspi_pong);
+	CHECK_SC_TASK( sc, "rtems_semaphore_release");
+
+	while (1) {
+		sc = rtems_semaphore_obtain( test_mpc55xx_dspi_ping, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
+		CHECK_SC_TASK( sc, "rtems_semaphore_obtain");
+
+		DEBUG_PRINT( "Pong\n");
+		
+		rv = rtems_libi2c_read_bytes( device, test_mpc55xx_dspi_reader_inbuf, MPC55XX_TEST_DSPI_BUFSIZE);
+		CHECK_RV_TASK( rv, "rtems_libi2c_read_bytes");
+
+		sc = rtems_semaphore_release( test_mpc55xx_dspi_pong);
+		CHECK_SC_TASK( sc, "rtems_semaphore_release");
+
+		printk( "Time: %i, Value: 0x%02x%02x%02x%02x\n", tac(),
+			test_mpc55xx_dspi_reader_inbuf [0], test_mpc55xx_dspi_reader_inbuf [1],
+			test_mpc55xx_dspi_reader_inbuf [2], test_mpc55xx_dspi_reader_inbuf [3]);
+	}
+
+	sc = rtems_libi2c_send_stop( device);
+	CHECK_SC_TASK( sc, "rtems_libi2c_send_stop");
+
+	sc = rtems_task_delete( RTEMS_SELF);
+	CHECK_SC_TASK( sc, "rtems_task_delete");
+}
+
+rtems_task test_sd_card( rtems_task_argument arg);
+
+static rtems_task test_mpc55xx_intc( rtems_task_argument arg);
+
+rtems_status_code mpc55xx_dspi_register()
+{
+	rtems_status_code sc = RTEMS_SUCCESSFUL;
+	int rv = 0;
+	int i = 0;
+	char device_name [] = "/dev/spi0";
+	union SIU_PCR_tag pcr = MPC55XX_ZERO_FLAGS;
+
+	printk( "Boot time: %u\n", ppc_time_base());
+	test_mpc55xx_intc( 0);
+
+	rv = rtems_libi2c_initialize();
+	CHECK_RVSC( rv, "rtems_libi2c_initialize");
+
+	/* DSPI D inputs are taken from DSPI C */
+	SIU.DISR.R = 0x000000FC;
+
+	/* DSPI A signals */
+	pcr.B.PA = 1;
+	pcr.B.ODE = 0;
+	pcr.B.HYS = 0;
+	pcr.B.SRC = 3;
+	pcr.B.WPE = 1;
+	pcr.B.WPS = 1;
+
+	/* SCK */
+	pcr.B.OBE = 1;
+	pcr.B.IBE = 0;
+	SIU.PCR [93].R = pcr.R;
+
+	/* SIN */
+	pcr.B.OBE = 0;
+	pcr.B.IBE = 1;
+	SIU.PCR [94].R = pcr.R;
+
+	/* SOUT */
+	pcr.B.OBE = 1;
+	pcr.B.IBE = 0;
+	SIU.PCR [95].R = pcr.R;
+
+	/* PCSx */
+	pcr.B.OBE = 1;
+	pcr.B.IBE = 0;
+	SIU.PCR [96].R = pcr.R;
+	SIU.PCR [97].R = pcr.R;
+	SIU.PCR [98].R = pcr.R;
+	SIU.PCR [99].R = pcr.R;
+	SIU.PCR [100].R = pcr.R;
+	SIU.PCR [101].R = pcr.R;
+
+	mpc55xx_dspi_bus_table [3].master = 0;
+	for (i = 0; i < MPC55XX_DSPI_NUMBER; ++i) {
+		device_name [8] = '0' + i;
+		rv = rtems_libi2c_register_bus( device_name, (rtems_libi2c_bus_t *) &mpc55xx_dspi_bus_table [i]);
+		CHECK_RVSC( rv, device_name);
+		test_mpc55xx_dspi_bus [i] = rv;
+	}
+
+	sc = rtems_semaphore_create (
+		rtems_build_name ( 'P', 'I', 'N', 'G'),
+		1,
+		RTEMS_SIMPLE_BINARY_SEMAPHORE | RTEMS_INHERIT_PRIORITY | RTEMS_PRIORITY,
+		RTEMS_NO_PRIORITY,
+		&test_mpc55xx_dspi_ping
+	);
+	CHECK_SC( sc, "rtems_semaphore_create");
+
+	sc = rtems_semaphore_create (
+		rtems_build_name ( 'P', 'O', 'N', 'G'),
+		0,
+		RTEMS_SIMPLE_BINARY_SEMAPHORE | RTEMS_INHERIT_PRIORITY | RTEMS_PRIORITY,
+		RTEMS_NO_PRIORITY,
+		&test_mpc55xx_dspi_pong
+	);
+	CHECK_SC( sc, "rtems_semaphore_create");
+
+	// rtems_id writer_task_id;
+	// rtems_id reader_task_id;
+	// 
+	// sc = rtems_task_create(
+	// 	rtems_build_name( 'T', 'W', 'R', 'T'),
+	// 	2,
+	// 	RTEMS_MINIMUM_STACK_SIZE,
+	// 	RTEMS_DEFAULT_MODES,
+	// 	RTEMS_DEFAULT_ATTRIBUTES,
+	// 	&writer_task_id
+	// );
+	// CHECK_SC( sc, "rtems_task_create");
+	// sc = rtems_task_create(
+	// 	rtems_build_name( 'T', 'R', 'D', 'R'),
+	// 	1,
+	// 	RTEMS_MINIMUM_STACK_SIZE,
+	// 	RTEMS_DEFAULT_MODES,
+	// 	RTEMS_DEFAULT_ATTRIBUTES,
+	// 	&reader_task_id
+	// );
+	// CHECK_SC( sc, "rtems_task_create");
+	// 
+	// sc = rtems_task_start( writer_task_id, test_mpc55xx_dspi_writer, 0);
+	// CHECK_SC( sc, "rtems_task_start");
+	// sc = rtems_task_start( reader_task_id, test_mpc55xx_dspi_reader, 0);
+	// CHECK_SC( sc, "rtems_task_start");
+
+	rtems_id sd_card_task_id;
+	sc = rtems_task_create(
+		rtems_build_name( 'T', 'S', 'D', 'C'),
+		1,
+		RTEMS_MINIMUM_STACK_SIZE,
+		RTEMS_DEFAULT_MODES,
+		RTEMS_DEFAULT_ATTRIBUTES,
+		&sd_card_task_id
+	);
+	CHECK_SC( sc, "rtems_task_create");
+	sc = rtems_task_start( sd_card_task_id, test_sd_card, 0);
+	CHECK_SC( sc, "rtems_task_start");
+
+	rtems_id intc_id;
+	sc = rtems_task_create(
+		rtems_build_name( 'I', 'N', 'T', 'C'),
+		2,
+		RTEMS_MINIMUM_STACK_SIZE,
+		RTEMS_DEFAULT_MODES,
+		RTEMS_DEFAULT_ATTRIBUTES,
+		&intc_id
+	);
+	CHECK_SC( sc, "rtems_task_create");
+	sc = rtems_task_start( intc_id, test_mpc55xx_intc, 0);
+	CHECK_SC( sc, "rtems_task_start");
+
+	sc = rtems_task_delete( RTEMS_SELF);
+	CHECK_SC( sc, "rtems_task_delete");
+
+	return RTEMS_SUCCESSFUL;
+}
+
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <dirent.h>
+#include <stdio.h>
+#include <rtems/fsmount.h>
+#include <rtems/dosfs.h>
+#include <rtems/ide_part_table.h>
+
+#define TEST_SD_CARD_BUF_SIZE 512
+#define TEST_SD_CARD_BIGBUF_SIZE (256 * 1024)
+
+#define TEST_SD_CARD_DEVICE_FILE "/dev/sd-card-a"
+#define TEST_SD_CARD_PARTITION "/dev/sd-card-a1"
+#define TEST_SD_CARD_MOUNT_POINT "/mnt"
+#define TEST_SD_CARD_DIRECTORY "/mnt/testdir"
+
+static fstab_t test_sd_card_fs_table [] = { {
+		TEST_SD_CARD_PARTITION, TEST_SD_CARD_MOUNT_POINT,
+		&msdos_ops, RTEMS_FILESYSTEM_READ_WRITE,
+		FSMOUNT_MNT_OK | FSMOUNT_MNTPNT_CRTERR | FSMOUNT_MNT_FAILED,
+		FSMOUNT_MNT_OK
+	}, {
+		TEST_SD_CARD_DEVICE_FILE, TEST_SD_CARD_MOUNT_POINT,
+		&msdos_ops, RTEMS_FILESYSTEM_READ_WRITE,
+		FSMOUNT_MNT_OK | FSMOUNT_MNTPNT_CRTERR | FSMOUNT_MNT_FAILED,
+		0
+	}
+};
+
+static uint8_t test_sd_card_buf [TEST_SD_CARD_BUF_SIZE] __attribute__ ((aligned (32)));
+
+static int test_sd_card_print_dir( const char* dirname, unsigned level)
+{
+	int rv = 0;
+	DIR *dir = NULL;
+	struct dirent *ent;
+	struct stat s;
+	int i = 0;
+
+	/* Open */
+	dir = opendir( dirname);
+	rv = dir == NULL ? -1 : 0;
+	CHECK_RV( rv, "Open directory");
+
+	/* Change CWD */
+	rv = chdir( dirname);
+	CHECK_RV( rv, "Change directory");
+
+	/* Read */
+	ent = readdir( dir);
+	while (ent != NULL) {
+		if (stat( ent->d_name, &s) == 0 && strcmp( ".", ent->d_name) != 0 && strcmp( "..", ent->d_name)) {
+			for (i = 0; i < level; ++i) {
+				printk( "\t");
+			}
+			printk( "<%s>\n", ent->d_name);
+			if (S_ISDIR( s.st_mode)) {
+				rv = test_sd_card_print_dir( ent->d_name, level + 1);
+				CHECK_RV( rv, "Next directory");
+			}
+		}
+		ent = readdir( dir);
+	}
+
+	/* Change CWD */
+	rv = chdir( "..");
+	CHECK_RV( rv, "Change directory");
+
+	/* Close */
+	rv = closedir( dir);
+	CHECK_RV( rv, "Close directory");
+
+	return 0;
+}
+
+#define SD_CARD_NUMBER 1
+
+static sd_card_driver_entry sd_card_driver_table_XXX [SD_CARD_NUMBER] = { {
+		driver : {
+			ops : &sd_card_driver_ops,
+			size : sizeof( sd_card_driver_entry)
+		},
+		table_index : 0,
+		minor : 0,
+		device_name : "sd-card-a",
+		disk_device_name : "/dev/sd-card-a",
+		transfer_mode : SD_CARD_TRANSFER_MODE_DEFAULT,
+		command : SD_CARD_COMMAND_DEFAULT,
+		/* response : whatever, */
+		response_index : SD_CARD_COMMAND_SIZE,
+		n_ac_max : SD_CARD_N_AC_MAX_DEFAULT,
+		block_number : 0,
+		block_size : 0,
+		block_size_shift : 0,
+		busy : 1,
+		verbose : 1,
+		schedule_if_busy : 0,
+	}
+};
+
+rtems_task test_sd_card( rtems_task_argument arg)
+{
+	rtems_status_code sc = RTEMS_SUCCESSFUL;
+	int rv = 0;
+	rtems_device_minor_number minor;
+	sd_card_driver_entry *e = &sd_card_driver_table [0];
+	int fd = 0;
+	unsigned i = 0;
+	unsigned avg = 0;
+	unsigned t = 0;
+	char file_name [] = "00000000.TXT";
+	uint8_t *buf = NULL;
+
+	DEBUG_PRINT( "Task started\n");
+
+	minor = rtems_libi2c_register_drv( e->device_name, (rtems_libi2c_drv_t *) e, test_mpc55xx_dspi_bus [0], 0);
+	CHECK_RV_TASK( (int) minor, "rtems_libi2c_register_drv");
+
+	buf = malloc( TEST_SD_CARD_BIGBUF_SIZE);
+	for (i = 0; i < TEST_SD_CARD_BIGBUF_SIZE; ++i) {
+		if (i % 27 == 26) {
+			buf [i] = '\n';
+		} else {
+			buf [i] = 'A' + i % 27;
+		}
+	}
+	buf [i - 1] = '\n';
+
+	rv = test_sd_card_print_dir( "/dev", 0);
+	CHECK_RV_TASK( rv, "Print directory");
+
+	sc = rtems_ide_part_table_initialize( TEST_SD_CARD_DEVICE_FILE);
+	CHECK_SC_TASK( sc, "Initialize IDE partition table");
+
+	rv = test_sd_card_print_dir( "/dev", 0);
+	CHECK_RV_TASK( rv, "Print directory");
+
+	rv = mkdir( TEST_SD_CARD_MOUNT_POINT, S_IRWXU);
+	CHECK_RV_TASK( rv, "Create mount point");
+
+	rv = rtems_fsmount( test_sd_card_fs_table, sizeof( test_sd_card_fs_table) / sizeof( test_sd_card_fs_table [0]), NULL);
+	CHECK_RV_TASK( rv, "Mount file systems");
+
+	//rv = test_sd_card_print_dir( TEST_SD_CARD_MOUNT_POINT, 0);
+	//CHECK_RV_TASK( rv, "Print directory");
+
+	rv = mkdir( TEST_SD_CARD_DIRECTORY, S_IRWXU);
+
+	rv = chdir( TEST_SD_CARD_DIRECTORY);
+	CHECK_RV_TASK( rv, "Change directory");
+
+	i = 0;
+	while (1) {
+		snprintf( file_name, 13, "%08i.TXT", i);
+		tic();
+		fd = creat( file_name, S_IREAD | S_IWRITE);
+		CHECK_RV_TASK( fd, "Create file");
+		rv = write( fd, buf, TEST_SD_CARD_BIGBUF_SIZE);
+		CHECK_RV_TASK( rv, "Write file");
+		rv = close( fd);
+		CHECK_RV_TASK( rv, "Close file");
+		t = tac();
+		avg = ((uint64_t) avg * ((uint64_t) i) + (uint64_t) t) / ((uint64_t) i + 1);
+		printk( "%s: %u (%u)\n", file_name, tac(), avg);
+		++i;
+	}
+
+	rv = chdir( "..");
+	CHECK_RV_TASK( rv, "Change directory");
+
+	rv = test_sd_card_print_dir( TEST_SD_CARD_DIRECTORY, 0);
+	CHECK_RV_TASK( rv, "Print directory");
+
+
+	// /* Write */
+	// int b = 0;
+	// const char device_name [] = "/dev/spi0.sd-card-0";
+	// fd = open( device_name, O_RDWR);
+	//
+	// CHECK_RV_TASK( fd, "open");
+	// while (1) {
+	// 	for (i = 0; i < TEST_SD_CARD_BUF_SIZE; ++i) {
+	// 		test_sd_card_buf [i] = b;
+	// 	}
+	// 	++b;
+	// 	rv = write( fd, test_sd_card_buf, TEST_SD_CARD_BUF_SIZE);
+	// 	if (rv < 0) {
+	// 		break;
+	// 	}
+	// }
+	// rv = close( fd);
+	// CHECK_RV_TASK( rv, "close");
+	// 
+	// /* Read */
+	// fd = open( device_name, O_RDWR);
+	// CHECK_RV_TASK( fd, "open");
+	// while (1) {
+	// 	rv = read( fd, test_sd_card_buf, TEST_SD_CARD_BUF_SIZE);
+	// 	if (rv < 0) {
+	// 		break;
+	// 	}
+	// 	printk( "%02x", test_sd_card_buf [rv - 1]);
+	// 	if (i++ % 64 == 0) {
+	// 		printk( "\n");
+	// 	}
+	// }
+	// rv = close( fd);
+	// CHECK_RV_TASK( rv, "close");
+
+	sc = rtems_task_delete( RTEMS_SELF);
+	CHECK_SC_TASK( sc, "rtems_task_delete");
+}
+
+#define ITER 4
+#define BUFSIZE (128 * ITER)
+
+static char inbuf [BUFSIZE];
+static char outbuf [BUFSIZE];
+
+static rtems_status_code test_mpc55xx_edma()
+{
+	rtems_status_code sc = RTEMS_SUCCESSFUL;
+	int rv = 0;
+	int channel = 0;
+	uint32_t error_status = 0;
+	rtems_id transfer_update;
+
+	sc = rtems_semaphore_create (
+		rtems_build_name ( 'T', 'S', 'T', 'C'),
+		0,
+		RTEMS_SIMPLE_BINARY_SEMAPHORE | RTEMS_INHERIT_PRIORITY | RTEMS_PRIORITY,
+		RTEMS_NO_PRIORITY,
+		&transfer_update
+	);
+	CHECK_SC( sc, "rtems_semaphore_create");
+
+	rv = mpc55xx_edma_obtain_channel( channel, &error_status, transfer_update);
+	CHECK_RV( rv, "mpc55xx_edma_obtain_channel");
+
+	int i = 0;
+	for (i = 0; i < BUFSIZE; ++i) {
+		inbuf [i] = i;
+		outbuf [i] = -1;
+	}
+	rtems_cache_flush_multiple_data_lines( inbuf, BUFSIZE);
+	rtems_cache_flush_multiple_data_lines( outbuf, BUFSIZE);
+
+	struct tcd_t tcd = MPC55XX_EDMA_TCD_DEFAULT;
+	tcd.SADDR = (uint32_t) &inbuf;
+	tcd.DADDR = (uint32_t) &outbuf;
+	tcd.NBYTES = BUFSIZE / ITER;
+	tcd.SLAST = -BUFSIZE;
+	tcd.CITER = ITER;
+	tcd.BITER = ITER;
+	tcd.INT_HALF = 1;
+
+	EDMA.TCD [channel] = tcd;
+
+	while (1) {
+		while (1) {
+			if (EDMA.TCD [channel].DONE == 1) {
+				EDMA.TCD [channel].DONE = 0;
+				printk( "%s: Done\n", __func__);
+				break;
+			} else if (EDMA.TCD [channel].ACTIVE == 0) {
+				EDMA.SSBR.R = channel;
+				printk( "%s: Start: %i (%i)\n", __func__, EDMA.TCD [channel].CITER, EDMA.TCD [channel].BITER);
+			}
+			sc = rtems_semaphore_obtain( transfer_update, RTEMS_WAIT, 10);
+			if (sc == RTEMS_TIMEOUT) {
+				continue;
+			}
+			CHECK_SC( sc, "rtems_semaphore_obtain");
+		}
+		printk( "%s: Error status: 0x%08x\n", __func__, error_status);
+	}
+
+	return sc;
+}
+
+static unsigned test_mpc55xx_intc_counter = 0;
+
+static inline void test_mpc55xx_intc_worker( void *data)
+{
+	int s = 0;
+	int i = *(int *) data;
+	printk( "(%i): Start: %u\n", i, tac());
+	s = mpc55xx_intc_clear_software_irq( i);
+	if (i < MPC55XX_IRQ_SOFTWARE_NUMBER) {
+		tic();
+		s = mpc55xx_intc_raise_software_irq( i + 1);
+	}
+	++test_mpc55xx_intc_counter;
+	printk( "(%i): Done\n", i);
+}
+
+static void test_mpc55xx_intc_handler( rtems_vector_number vector, void *data)
+{
+	test_mpc55xx_intc_worker( data);
+}
+
+static void test_mpc55xx_intc_handler_2( void *data)
+{
+	test_mpc55xx_intc_worker( data);
+}
+
+static void test_mpc55xx_intc_handler_3( void *data)
+{
+	test_mpc55xx_intc_worker( data);
+}
+
+static int test_mpc55xx_intc_handler_data [MPC55XX_IRQ_SOFTWARE_NUMBER];
+
+static rtems_task test_mpc55xx_intc( rtems_task_argument arg)
+{
+	volatile int i = 0;
+	int p = 0;
+	unsigned s = 0;
+	rtems_irq_connect_data e;
+	rtems_status_code sc = RTEMS_SUCCESSFUL;
+
+	for (i = MPC55XX_IRQ_SOFTWARE_MIN, p = MPC55XX_INTC_MIN_PRIORITY; i <= MPC55XX_IRQ_SOFTWARE_MAX; ++i, ++p) {
+		test_mpc55xx_intc_handler_data [i] = i;
+		e.name = i;
+		e.handle = &test_mpc55xx_intc_handler_data [i];
+
+		sc = rtems_interrupt_handler_install( i, "test_mpc55xx_intc_handler", RTEMS_INTERRUPT_SHARED, test_mpc55xx_intc_handler, e.handle);
+		if (sc != RTEMS_SUCCESSFUL) {
+			BSP_panic( "Handler install failed");
+		}
+
+		e.hdl = test_mpc55xx_intc_handler_2;
+		if (BSP_install_rtems_shared_irq_handler( &e) != RTEMS_SUCCESSFUL) {
+			BSP_panic( "Handler install 2 failed");
+		}
+
+		e.hdl = test_mpc55xx_intc_handler_3;
+		if (BSP_install_rtems_shared_irq_handler( &e) != RTEMS_SUCCESSFUL) {
+			BSP_panic( "Handler install 3 failed");
+		}
+	}
+
+	while (1) {
+		i = (int) (7.0 * (rand_r( &s) / (RAND_MAX + 1.0)));
+		tic();
+		mpc55xx_intc_raise_software_irq( i);
+	}
+}
