Changeset 574fb67 in rtems for c/src/lib/libbsp/powerpc


Ignore:
Timestamp:
Jul 14, 2008, 4:15:28 PM (11 years ago)
Author:
Thomas Doerfler <Thomas.Doerfler@…>
Branches:
4.10, 4.11, 4.9, master
Children:
18e6e824
Parents:
3c6fe2e
Message:

updated gen83xx BSP
updated haleakala BSP
added MPC55xx BSP

Location:
c/src/lib/libbsp/powerpc
Files:
21 added
3 deleted
23 edited
1 moved

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/ChangeLog

    r3c6fe2e r574fb67  
     12008-07-14      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * mpc55xxevb: New BSP.
     4
    152008-07-14      Thomas Doefler <Thomas.Doerfler@embedded-brains.de>
    26        * haleakala: added new BSP
  • c/src/lib/libbsp/powerpc/acinclude.m4

    r3c6fe2e r574fb67  
    1515  motorola_powerpc )
    1616    AC_CONFIG_SUBDIRS([motorola_powerpc]);;
     17  mpc55xxevb )
     18    AC_CONFIG_SUBDIRS([mpc55xxevb]);;
    1719  mpc8260ads )
    1820    AC_CONFIG_SUBDIRS([mpc8260ads]);;
  • c/src/lib/libbsp/powerpc/gen83xx/ChangeLog

    r3c6fe2e r574fb67  
     12008-07-14      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * irq/irq_init.c, irq/irq.h, startup/linkcmds:
     4        Removed.
     5
     6        * README.mpc8313erdb, include/irq-config.h, include/irq.h, irq/irq.c,
     7        startup/linkcmds.base, startup/linkcmds.mpc8313erdb: New files.
     8
     9        * Makefile.am, configure.ac, console/config.c, console/console.c,
     10        i2c/i2c_init.c, include/bsp.h, include/hwreg_vals.h, network/network.c,
     11        spi/spi_init.c, start/start.S, startup/bspstart.c, startup/cpuinit.c,
     12        startup/linkcmds.hsc_cm01, startup/linkcmds.mpc8349eamds: Support
     13        MPC8313ERDB.
     14
    1152008-05-15      Joel Sherrill <joel.sherrill@OARcorp.com>
    216
  • c/src/lib/libbsp/powerpc/gen83xx/Makefile.am

    r3c6fe2e r574fb67  
    1212include_HEADERS = include/bsp.h
    1313include_HEADERS += include/tm27.h
     14
     15libcpudir = ../../../libcpu/@RTEMS_CPU@
    1416
    1517nodist_include_HEADERS = include/bspopts.h
     
    3436project_lib_DATA += rtems_crti.$(OBJEXT)
    3537
    36 dist_project_lib_DATA += startup/linkcmds \
     38dist_project_lib_DATA += startup/linkcmds.base \
     39                         startup/linkcmds.mpc8313erdb \
    3740                         startup/linkcmds.mpc8349eamds \
    3841                         startup/linkcmds.hsc_cm01
    3942
    4043mpc83xx_regs_SOURCES = startup/mpc83xx_regs.c
    41 startup_SOURCES = ../../shared/bspclean.c ../../shared/bsplibc.c \
    42     ../../shared/bsppost.c startup/bspstart.c ../../shared/bootcard.c \
    43     ../../shared/bsppredriverhook.c \
    44     ../../shared/sbrk.c ../../shared/gnatinstallhandler.c startup/cpuinit.c
    45 pclock_SOURCES = ../../powerpc/shared/clock/p_clock.c
    4644
    47 include_bsp_HEADERS = ./irq/irq.h \
    48     ./include/hwreg_vals.h        \
    49     ../../powerpc/shared/vectors/vectors.h
     45startup_SOURCES = ../../shared/bspclean.c \
     46        ../../shared/bsplibc.c \
     47        ../../shared/bsppost.c \
     48        ../../shared/bootcard.c \
     49        ../../shared/bsppredriverhook.c \
     50        ../../shared/sbrk.c \
     51        ../../shared/gnatinstallhandler.c \
     52        ../shared/src/tictac.c \
     53        startup/cpuinit.c \
     54        startup/bspstart.c
    5055
    51 vectors_SOURCES = ../../powerpc/shared/vectors/vectors.h \
    52     ../../powerpc/shared/vectors/vectors_init.c \
    53     ../../powerpc/shared/vectors/vectors.S
    54 irq_SOURCES = ./irq/irq.h ./irq/irq_init.c ./irq/ipic.c \
    55         ../shared/irq/irq_asm.S
     56clock_SOURCES = ../shared/clock/clock.c
     57
     58include_bsp_HEADERS = include/irq.h \
     59        include/irq-config.h \
     60        ../../shared/include/irq-generic.h \
     61        include/hwreg_vals.h \
     62        ../shared/include/u-boot.h \
     63        ../shared/include/tictac.h
     64
     65irq_SOURCES = include/irq.h \
     66        include/irq-config.h \
     67        irq/irq.c \
     68        ../../shared/src/irq-generic.c \
     69        ../../shared/src/irq-legacy.c
     70
    5671console_SOURCES = console/console.c console/ns16550cfg.c
    5772bsp_i2c_SOURCES   = i2c/i2c_init.c
     
    6782
    6883noinst_LIBRARIES = libbsp.a
    69 libbsp_a_SOURCES = $(startup_SOURCES) $(pclock_SOURCES) $(console_SOURCES) \
    70     $(vectors_SOURCES) $(irq_SOURCES) $(mpc83xx_regs_SOURCES) \
     84libbsp_a_SOURCES = $(startup_SOURCES) $(clock_SOURCES) $(console_SOURCES) \
     85    $(irq_SOURCES) $(mpc83xx_regs_SOURCES) \
    7186    $(bsp_i2c_SOURCES) $(bsp_spi_SOURCES)
    7287
    73 libbsp_a_LIBADD = \
    74     ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
    75     ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
    76     ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
    77     ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
    78     ../../../libcpu/@RTEMS_CPU@/mpc6xx/mmu.rel   \
    79     ../../../libcpu/@RTEMS_CPU@/mpc6xx/timer.rel \
    80     ../../../libcpu/@RTEMS_CPU@/mpc6xx/clock.rel \
    81     ../../../libcpu/@RTEMS_CPU@/mpc83xx/i2c.rel \
    82     ../../../libcpu/@RTEMS_CPU@/mpc83xx/spi.rel
     88libbsp_a_LIBADD = $(libcpudir)/shared/cpuIdent.rel \
     89        $(libcpudir)/shared/cache.rel \
     90        $(libcpudir)/@exceptions@/rtems-cpu.rel \
     91        $(libcpudir)/@exceptions@/raw_exception.rel \
     92        $(libcpudir)/@exceptions@/exc_bspsupport.rel \
     93        $(libcpudir)/mpc6xx/mmu.rel   \
     94        $(libcpudir)/mpc6xx/timer.rel \
     95        $(libcpudir)/mpc83xx/i2c.rel \
     96        $(libcpudir)/mpc83xx/spi.rel \
     97        $(libcpudir)/mpc83xx/gtm.rel
    8398
    8499if HAS_NETWORKING
    85100libbsp_a_LIBADD += network.rel
    86 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/mpc83xx/tsec.rel
     101libbsp_a_LIBADD += $(libcpudir)/mpc83xx/tsec.rel
    87102endif
    88103
  • c/src/lib/libbsp/powerpc/gen83xx/configure.ac

    r3c6fe2e r574fb67  
    1111AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.10])
    1212RTEMS_BSP_CONFIGURE
     13RTEMS_AMPOLISH3
    1314
    1415RTEMS_PROG_CC_FOR_TARGET([-ansi -fasm])
  • c/src/lib/libbsp/powerpc/gen83xx/console/config.c

    r3c6fe2e r574fb67  
    9898                16,                             /* ulMargin */
    9999                8,                              /* ulHysteresis */
    100                 (void *)9600,   /* baud rate */ /* pDeviceParams */
     100
     101                /* pDeviceParams */
     102                /* baud rate */
     103#ifdef MPC8313ERDB
     104                (void *)115200,
     105#else /* MPC8313ERDB */
     106                (void *)9600,
     107#endif /* MPC8313ERDB */
     108
    101109                (uint32_t)&(mpc83xx.duart[0]),  /* ulCtrlPort1e */
    102110                0,                              /* ulCtrlPort2 */
     
    118126                16,                             /* ulMargin */
    119127                8,                              /* ulHysteresis */
    120                 (void *)9600,   /* baud rate */ /* pDeviceParams */
     128
     129                /* pDeviceParams */
     130                /* baud rate */
     131#ifdef MPC8313ERDB
     132                (void *)115200,
     133#else /* MPC8313ERDB */
     134                (void *)9600,
     135#endif /* MPC8313ERDB */
     136
    121137                (uint32_t)&(mpc83xx.duart[1]),  /* ulCtrlPort1-Filled in at runtime */
    122138                0,                              /* ulCtrlPort2 */
  • c/src/lib/libbsp/powerpc/gen83xx/console/console.c

    r3c6fe2e r574fb67  
    4545#include "console.h"
    4646#include <rtems/bspIo.h>
     47#include <rtems/termiostypes.h>
    4748
    4849/*
     
    99100        status = rtems_termios_open ( major, minor, arg, &Callbacks);
    100101        Console_Port_Data[minor].termios_data = args->iop->data1;
     102        if (status == 0) {
     103                rtems_termios_set_initial_baud( Console_Port_Data [minor].termios_data, (int) Console_Port_Tbl [minor].pDeviceParams);
     104        }
    101105
    102106        return status;
     
    257261    Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
    258262      deviceWritePolled(Console_Port_Minor,c);
     263
     264    if (c == '\n') {
     265      Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
     266        deviceWritePolled(Console_Port_Minor,'\r');
     267    }
    259268   
    260269    rtems_interrupt_enable(Irql);
  • c/src/lib/libbsp/powerpc/gen83xx/i2c/i2c_init.c

    r3c6fe2e r574fb67  
    2626  {
    2727    {/* public fields */
    28       ops:      &mpc83xx_i2c_ops,
    29       size:     sizeof(mpc83xx_i2c_bus_tbl[0]),
     28      .ops = &mpc83xx_i2c_ops,
     29      .size = sizeof(mpc83xx_i2c_bus_tbl[0]),
    3030    },
    3131    { /* our private fields */
    32       reg_ptr:  &mpc83xx.i2c[0],
    33       initialized: FALSE,
    34       irq_number : BSP_IPIC_IRQ_I2C1,
    35       base_frq   : 0 /* will be set during initiailization */
     32      .reg_ptr = &mpc83xx.i2c[0],
     33      .initialized = FALSE,
     34      .irq_number = BSP_IPIC_IRQ_I2C1,
     35      .base_frq = 0 /* will be set during initiailization */
    3636    }
    3737  },
     
    3939  {
    4040    { /* public fields */
    41       ops:      &mpc83xx_i2c_ops,
    42       size:     sizeof(mpc83xx_i2c_bus_tbl[1]),
     41      .ops = &mpc83xx_i2c_ops,
     42      .size = sizeof(mpc83xx_i2c_bus_tbl[1]),
    4343    },
    4444    { /* our private fields */
    45       reg_ptr:  &mpc83xx.i2c[1],
    46       initialized: FALSE,
    47       irq_number : BSP_IPIC_IRQ_I2C2,
    48       base_frq   : 0 /* will be set during initiailization */
     45      .reg_ptr = &mpc83xx.i2c[1],
     46      .initialized = FALSE,
     47      .irq_number = BSP_IPIC_IRQ_I2C2,
     48      .base_frq = 0 /* will be set during initiailization */
    4949    }
    5050  }
     
    115115  i2c2_busno = ret_code;
    116116
     117#ifdef RTEMS_BSP_I2C_EEPROM_DEVICE_NAME
     118
    117119  /*
    118120   * register EEPROM to bus 1, Address 0x50
     
    121123                                       i2c_2b_eeprom_driver_descriptor,
    122124                                       i2c1_busno,0x50);
     125
    123126  if (ret_code < 0) {
    124127    return -ret_code;
    125128  }
     129
     130#endif /* RTEMS_BSP_I2C_EEPROM_DEVICE_NAME */
    126131
    127132  /*
  • c/src/lib/libbsp/powerpc/gen83xx/include/bsp.h

    r3c6fe2e r574fb67  
    2121#define __GEN83xx_BSP_h
    2222
     23/*
     24 * MPC8313E Reference Design Board
     25 */
     26
     27#ifdef MPC8313ERDB
     28
     29#define HAS_UBOOT
     30
     31/* For U-Boot */
     32#define CONFIG_MPC83XX
     33#define CONFIG_HAS_ETH1
     34
     35#endif /* MPC8313ERDB */
     36
     37#include <libcpu/powerpc-utility.h>
     38
    2339#include <bsp/hwreg_vals.h>
     40
     41/*
     42 * Some symbols defined in the linker command file.
     43 */
     44
     45LINKER_SYMBOL( bsp_ram_start);
     46LINKER_SYMBOL( bsp_ram_end);
     47LINKER_SYMBOL( bsp_ram_size);
     48
     49LINKER_SYMBOL( bsp_rom_start);
     50LINKER_SYMBOL( bsp_rom_end);
     51LINKER_SYMBOL( bsp_rom_size);
     52
     53LINKER_SYMBOL( bsp_section_text_start);
     54LINKER_SYMBOL( bsp_section_text_end);
     55LINKER_SYMBOL( bsp_section_text_size);
     56
     57LINKER_SYMBOL( bsp_section_data_start);
     58LINKER_SYMBOL( bsp_section_data_end);
     59LINKER_SYMBOL( bsp_section_data_size);
     60
     61LINKER_SYMBOL( bsp_section_bss_start);
     62LINKER_SYMBOL( bsp_section_bss_end);
     63LINKER_SYMBOL( bsp_section_bss_size);
     64
     65LINKER_SYMBOL( bsp_interrupt_stack_start);
     66LINKER_SYMBOL( bsp_interrupt_stack_end);
     67LINKER_SYMBOL( bsp_interrupt_stack_size);
     68LINKER_SYMBOL( bsp_interrupt_stack_pointer);
     69
     70LINKER_SYMBOL( bsp_workspace_start);
     71
     72LINKER_SYMBOL( IMMRBAR);
    2473
    2574#ifndef ASM
     
    3685#include <bsp/irq.h>
    3786#include <bsp/vectors.h>
     87#include <bsp/tictac.h>
     88
     89#ifdef HAS_UBOOT
     90
     91#include <bsp/u-boot.h>
     92
     93extern bd_t mpc83xx_uboot_board_info;
     94
     95extern const size_t mpc83xx_uboot_board_info_size;
     96
     97#endif /* HAS_UBOOT */
    3898
    3999/* miscellaneous stuff assumed to exist */
     
    98158
    99159/*
    100  *  Convert decrement value to tenths of microsecnds (used by
    101  *  shared timer driver).
    102  *
    103  *    + CPU has a csb_clock bus,
    104  *    + There are 4 bus cycles per click
    105  *    + We return value in 1/10 microsecond units.
    106  *   Modified following equation to integer equation to remove
    107  *   floating point math.
    108  *   (int) ((float)(_value) / ((XLB_CLOCK/1000000 * 0.1) / 4.0))
    109  */
    110 
    111 extern unsigned int BSP_bus_frequency;
    112 #define BSP_Convert_decrementer( _value ) \
    113   (int) (((_value) * 4000) / (BSP_bus_frequency/10000))
    114 
    115 /*
    116160 * Network driver configuration
    117161 */
    118162struct rtems_bsdnet_ifconfig;
    119163extern int BSP_tsec_attach(struct rtems_bsdnet_ifconfig *config,int attaching);
     164#define RTEMS_BSP_NETWORK_DRIVER_ATTACH BSP_tsec_attach
     165
     166#ifdef MPC8313ERDB
     167
     168#define RTEMS_BSP_NETWORK_DRIVER_NAME   "tsec2"
     169#define RTEMS_BSP_NETWORK_DRIVER_NAME2  "tsec1"
     170
     171#else /* MPC8313ERDB */
     172
    120173#define RTEMS_BSP_NETWORK_DRIVER_NAME   "tsec1"
    121 #define RTEMS_BSP_NETWORK_DRIVER_ATTACH BSP_tsec_attach
    122 
    123174#define RTEMS_BSP_NETWORK_DRIVER_NAME2  "tsec2"
     175
     176#endif /* MPC8313ERDB */
    124177
    125178#if defined(MPC8349EAMDS)
     
    151204#endif /* defined(HSC_CM01) */
    152205
     206extern unsigned int BSP_bus_frequency;
     207
     208extern uint32_t bsp_clicks_per_usec;
     209
     210/*
     211 *  Convert decrementer value to tenths of microseconds (used by shared timer
     212 *  driver).
     213 */
     214#define BSP_Convert_decrementer( _value ) \
     215  ((int) (((_value) * 10) / bsp_clicks_per_usec))
     216
     217void mpc83xx_zero_4( void *dest, size_t n);
     218
    153219#ifdef __cplusplus
    154220}
  • c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h

    r3c6fe2e r574fb67  
    2222
    2323#include <mpc83xx/mpc83xx.h>
     24
    2425/*
    2526 * distinguish board characteristics
     
    104105                          RCWHR_LALE_NORM    |  \
    105106                          RCWHR_LDP_PAR)
     107
     108#elif defined( HAS_UBOOT)
     109
     110/* TODO */
     111
    106112#else
     113
    107114#error "board type not defined"
     115
    108116#endif
    109117
     
    112120 * for Freescale MPC8349EAMDS
    113121 */
    114 /*
    115  * address range definitions
    116  */
    117 /* ROM definitions (8 MB, mirrored multiple times) */
    118 #define ROM_START       0xFE000000
    119 #define ROM_SIZE        0x02000000
    120 #define ROM_END         (ROM_START+ROM_SIZE-1)
    121 #define BOOT_START      ROM_START
    122 #define BOOT_END        ROM_END
    123 
    124 /* SDRAM definitions (256 MB) */
    125 #define RAM_START       0x00000000
    126 #define RAM_SIZE        0x10000000
    127 #define RAM_END         (RAM_START+RAM_SIZE-1)
    128 
    129 
    130 /* working internal memory map base address */
    131 #define IMMRBAR         0xE0000000
    132122
    133123/*
    134124 * working values for various registers, used in start/start.S
    135125 */
     126
    136127/*
    137128 * Local Access Windows
     
    184175 * for JPK HSC_CM01
    185176 */
    186 /*
    187  * address range definitions
    188  */
    189 /* ROM definitions (8 MB, mirrored multiple times) */
    190 #define ROM_START       0xFE000000
    191 #define ROM_SIZE        0x02000000
    192 #define ROM_END         (ROM_START+ROM_SIZE-1)
    193 #define BOOT_START      ROM_START
    194 #define BOOT_END        ROM_END
    195 
    196 /* SDRAM definitions (256 MB) */
    197 #define RAM_START       0x00000000
    198 #define RAM_SIZE        0x10000000
    199 #define RAM_END         (RAM_START+RAM_SIZE-1)
    200 
    201 
    202 /* working internal memory map base address */
    203 #define IMMRBAR         0xE0000000
    204177
    205178/*
    206179 * working values for various registers, used in start/start.S
    207180 */
     181
    208182/*
    209183 * Local Access Windows
     
    211185 */
    212186
    213 #define LBLAWBAR0_VAL  ROM_START
     187#define LBLAWBAR0_VAL  bsp_rom_start
    214188#define LBLAWAR0_VAL   0x80000018
    215189#define LBLAWBAR1_VAL  0xF8000000
    216190#define LBLAWAR1_VAL   0x80000015
    217 #define DDRLAWBAR0_VAL RAM_START
     191#define DDRLAWBAR0_VAL bsp_ram_start
    218192#define DDRLAWAR0_VAL  0x8000001B
    219193/*
     
    251225#define DDR_SDRAM_INIT_ADDR_VAL      0
    252226#define DDR_SDRAM_INTERVAL_VAL       0x05080000
     227
     228#elif defined( HAS_UBOOT)
     229
     230/* TODO */
     231
    253232#else
     233
    254234#error "board type not defined"
     235
    255236#endif
    256 
    257237
    258238/**************************
  • c/src/lib/libbsp/powerpc/gen83xx/include/irq.h

    r3c6fe2e r574fb67  
    2020#define GEN83xx_IRQ_IRQ_H
    2121
     22#include <stdbool.h>
     23
    2224#include <rtems.h>
    2325#include <rtems/irq.h>
     26#include <rtems/irq-extension.h>
    2427
    2528/*
     
    125128
    126129    BSP_IPIC_IRQ_LAST     = BSP_IPIC_IRQ_MAX_OFFSET,
    127     BSP_DECREMENTER       = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0
    128130  } rtems_irq_symbolic_name;
    129131
    130   extern rtems_irq_connect_data *BSP_rtems_irq_tbl;
    131   void BSP_rtems_irq_mng_init(unsigned cpuId);
     132rtems_status_code mpc83xx_ipic_set_mask( rtems_vector_number vector, rtems_vector_number mask_vector, bool mask);
    132133
    133   /* ipic.c */
    134   rtems_status_code BSP_irq_handle_at_ipic(uint32_t excNum);
    135   void BSP_irq_enable_at_ipic (rtems_irq_number irqnum);
    136   void BSP_irq_disable_at_ipic (rtems_irq_number irqnum);
     134#define MPC83XX_IPIC_INTERRUPT_NORMAL 0
     135
     136#define MPC83XX_IPIC_INTERRUPT_SYSTEM 1
     137
     138#define MPC83XX_IPIC_INTERRUPT_CRITICAL 2
     139
     140rtems_status_code mpc83xx_ipic_set_highest_priority_interrupt( rtems_vector_number vector, int type);
    137141
    138142#ifdef __cplusplus
  • c/src/lib/libbsp/powerpc/gen83xx/network/network.c

    r3c6fe2e r574fb67  
    3030#define TSEC_IFMODE_GMII  1
    3131
    32 #if defined(MPC8349EAMDS)
     32#if defined( MPC8313ERDB)
     33
    3334#define TSEC_IFMODE TSEC_IFMODE_RGMII
    34 #endif
    3535
    36 #if defined(HSC_CM01)
     36#elif defined( MPC8349EAMDS)
     37
    3738#define TSEC_IFMODE TSEC_IFMODE_RGMII
     39
     40#elif defined( HSC_CM01)
     41
     42#define TSEC_IFMODE TSEC_IFMODE_RGMII
     43
     44#else
     45
     46#warning No TSEC configuration available
     47
    3848#endif
    3949
     
    5767\*=========================================================================*/
    5868{
    59   char hw_addr[6] = {0x00,0x04,0x9F,0x00,0x2f,0xcb};
    6069  int    unitNumber;
    6170  char   *unitName;
     
    101110   */
    102111  if (config->hardware_address == NULL) {
     112
     113#ifdef HAS_UBOOT
     114
     115    switch (unitNumber) {
     116      case 1:
     117        config->hardware_address = mpc83xx_uboot_board_info.bi_enetaddr;
     118        break;
     119
     120#ifdef CONFIG_HAS_ETH1
     121      case 2:
     122        config->hardware_address = mpc83xx_uboot_board_info.bi_enet1addr;
     123        break;
     124#endif /* CONFIG_HAS_ETH1 */
     125
     126#ifdef CONFIG_HAS_ETH2
     127      case 3:
     128        config->hardware_address = mpc83xx_uboot_board_info.bi_enet2addr;
     129        break;
     130#endif /* CONFIG_HAS_ETH2 */
     131
     132#ifdef CONFIG_HAS_ETH3
     133      case 4:
     134        config->hardware_address = mpc83xx_uboot_board_info.bi_enet3addr;
     135        break;
     136#endif /* CONFIG_HAS_ETH3 */
     137
     138      default:
     139        return 0;
     140    }
     141
     142#else /* HAS_UBOOT */
     143
     144    char hw_addr [6] = { 0x00, 0x04, 0x9f, 0x00, 0x2f, 0xcb};
     145
    103146    config->hardware_address = hw_addr;
     147
     148#endif /* HAS_UBOOT */
     149
    104150  }
    105151  /*
  • c/src/lib/libbsp/powerpc/gen83xx/preinstall.am

    r3c6fe2e r574fb67  
    4141PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
    4242
     43../../../libcpu/@RTEMS_CPU@/$(dirstamp):
     44        @$(MKDIR_P) ../../../libcpu/@RTEMS_CPU@
     45        @: > ../../../libcpu/@RTEMS_CPU@/$(dirstamp)
     46PREINSTALL_DIRS += ../../../libcpu/@RTEMS_CPU@/$(dirstamp)
     47
    4348$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
    4449        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
     
    6671TMPINSTALL_FILES += $(PROJECT_LIB)/rtems_crti.$(OBJEXT)
    6772
    68 $(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
    69         $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
    70 PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds
     73$(PROJECT_LIB)/linkcmds.base: startup/linkcmds.base $(PROJECT_LIB)/$(dirstamp)
     74        $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.base
     75PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.base
     76
     77$(PROJECT_LIB)/linkcmds.mpc8313erdb: startup/linkcmds.mpc8313erdb $(PROJECT_LIB)/$(dirstamp)
     78        $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.mpc8313erdb
     79PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.mpc8313erdb
    7180
    7281$(PROJECT_LIB)/linkcmds.mpc8349eamds: startup/linkcmds.mpc8349eamds $(PROJECT_LIB)/$(dirstamp)
     
    7887PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.hsc_cm01
    7988
    80 $(PROJECT_INCLUDE)/bsp/irq.h: ./irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     89$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    8190        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
    8291PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
    8392
    84 $(PROJECT_INCLUDE)/bsp/hwreg_vals.h: ./include/hwreg_vals.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     93$(PROJECT_INCLUDE)/bsp/irq-config.h: include/irq-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     94        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-config.h
     95PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-config.h
     96
     97$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     98        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
     99PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
     100
     101$(PROJECT_INCLUDE)/bsp/hwreg_vals.h: include/hwreg_vals.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    85102        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/hwreg_vals.h
    86103PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/hwreg_vals.h
    87104
    88 $(PROJECT_INCLUDE)/bsp/vectors.h: ../../powerpc/shared/vectors/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    89         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
    90 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h
     105$(PROJECT_INCLUDE)/bsp/u-boot.h: ../shared/include/u-boot.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     106        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/u-boot.h
     107PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/u-boot.h
    91108
     109$(PROJECT_INCLUDE)/bsp/tictac.h: ../shared/include/tictac.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     110        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tictac.h
     111PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tictac.h
     112
  • c/src/lib/libbsp/powerpc/gen83xx/spi/spi_init.c

    r3c6fe2e r574fb67  
    2121#include <bsp/irq.h>
    2222#include <bsp.h>
    23 #if defined(MPC8349EAMDS)
     23
     24#if defined( MPC8313ERDB)
     25
     26#include <libchip/spi-sd-card.h>
     27
     28#elif defined( MPC8349EAMDS)
     29
    2430#include <libchip/spi-flash-m25p40.h>
    25 #endif
    26 #if defined(HSC_CM01)
     31
     32#elif defined( HSC_CM01)
     33
    2734#include <libchip/spi-fram-fm25l256.h>
     35
     36#else
     37
     38#warning No SPI configuration available
     39
    2840#endif
    2941
     
    5264\*=========================================================================*/
    5365{
    54 #if defined(MPC8349EAMDS)
     66
     67#if defined( MPC8313ERDB)
     68
     69  /* Check address */
     70  if (addr > 0) {
     71    return RTEMS_INVALID_NUMBER;
     72  }
     73
     74  /* SCS (active low) */
     75  mpc83xx.gpio [0].gpdat &= ~0x20000000;
     76
     77#elif defined( MPC8349EAMDS)
     78
    5579  /*
    5680   * check device address for valid range
     
    6589   */
    6690  mpc83xx.gpio[0].gpdat &= ~(1 << (31- 0));
    67 #endif
    68 #if defined(HSC_CM01)
     91
     92#elif defined( HSC_CM01)
     93
    6994  /*
    7095   * check device address for valid range
     
    89114   */
    90115  mpc83xx.gpio[0].gpdat |= (1 << (31- 27));
    91 #endif
     116
     117#endif
     118
    92119  return  RTEMS_SUCCESSFUL;
    93120}
     
    111138\*=========================================================================*/
    112139{
    113 #if defined(MPC8349EAMDS)
     140
     141#if defined( MPC8313ERDB)
     142
     143  /* SCS (inactive high) */
     144  mpc83xx.gpio [0].gpdat |= 0x20000000;
     145
     146#elif defined( MPC8349EAMDS)
     147
    114148  /*
    115149   * GPIO1[0] is nSEL_SPI for M25P40
     
    117151   */
    118152  mpc83xx.gpio[0].gpdat |=  (1 << (31- 0));
    119 #endif
    120 #if defined(HSC_CM01)
     153
     154#elif defined( HSC_CM01)
     155
    121156  /*
    122157   * GPIO1[27] is high-active strobe
     
    124159   */
    125160  mpc83xx.gpio[0].gpdat &= ~(0x1 << (31-27));
    126 #endif
     161
     162#endif
     163
    127164  return 0;
    128165}
     
    149186  printk("bsp_spi_send_stop called... ");
    150187#endif
    151 #if defined(MPC8349EAMDS)
     188
     189#if defined( MPC8313ERDB)
     190
     191  /* SCS (inactive high) */
     192  mpc83xx.gpio [0].gpdat |= 0x20000000;
     193
     194#elif defined( MPC8349EAMDS)
     195
    152196  /*
    153197   * deselect given device
     
    156200   */
    157201  mpc83xx.gpio[0].gpdat |=  (1 << (31- 0));
    158 #endif
    159 #if defined(HSC_CM01)
     202
     203#elif defined( HSC_CM01)
     204
    160205  /*
    161206   * deselect device
     
    163208   */
    164209  mpc83xx.gpio[0].gpdat &= ~(1 << (31- 27));
    165 #endif
     210
     211#endif
     212
    166213#if defined(DEBUG)
    167214  printk("... exit OK\r\n");
     
    175222
    176223rtems_libi2c_bus_ops_t bsp_spi_ops = {
    177   init:            mpc83xx_spi_init,
    178   send_start:      bsp_spi_send_start_dummy,
    179   send_stop:        bsp_spi_send_stop,
    180   send_addr:        bsp_spi_sel_addr,
    181   read_bytes:      mpc83xx_spi_read_bytes,
    182   write_bytes:      mpc83xx_spi_write_bytes,
    183   ioctl:            mpc83xx_spi_ioctl
     224  .init = mpc83xx_spi_init,
     225  .send_start = bsp_spi_send_start_dummy,
     226  .send_stop = bsp_spi_send_stop,
     227  .send_addr = bsp_spi_sel_addr,
     228  .read_bytes = mpc83xx_spi_read_bytes,
     229  .write_bytes = mpc83xx_spi_write_bytes,
     230  .ioctl = mpc83xx_spi_ioctl
    184231};
    185232
    186233static mpc83xx_spi_desc_t bsp_spi_bus_desc = {
    187234  {/* public fields */
    188     ops:        &bsp_spi_ops,
    189     size:       sizeof(bsp_spi_bus_desc),
     235    .ops = &bsp_spi_ops,
     236    .size = sizeof(bsp_spi_bus_desc)
    190237  },
    191238  { /* our private fields */
    192     reg_ptr:     &mpc83xx.spi,
    193     initialized: FALSE,
    194     irq_number: BSP_IPIC_IRQ_SPI,
    195     base_frq  : 0 /* filled in during init */
     239    .reg_ptr =&mpc83xx.spi,
     240    .initialized = FALSE,
     241    .irq_number = BSP_IPIC_IRQ_SPI,
     242    .base_frq = 0 /* filled in during init */
    196243  }
    197244};
     245
     246#ifdef MPC8313ERDB
     247
     248#include <libchip/spi-sd-card.h>
     249
     250sd_card_driver_entry sd_card_driver_table [1] = { {
     251                .driver = {
     252                        .ops = &sd_card_driver_ops,
     253                        .size = sizeof( sd_card_driver_entry)
     254                },
     255                .table_index = 0,
     256                .minor = 0,
     257                .device_name = "sd-card-a",
     258                .disk_device_name = "/dev/sd-card-a",
     259                .transfer_mode = SD_CARD_TRANSFER_MODE_DEFAULT,
     260                .command = SD_CARD_COMMAND_DEFAULT,
     261                /* .response = whatever, */
     262                .response_index = SD_CARD_COMMAND_SIZE,
     263                .n_ac_max = SD_CARD_N_AC_MAX_DEFAULT,
     264                .block_number = 0,
     265                .block_size = 0,
     266                .block_size_shift = 0,
     267                .busy = 1,
     268                .verbose = 1,
     269                .schedule_if_busy = 0
     270        }
     271};
     272
     273#endif /* MPC8313ERDB */
     274
    198275
    199276/*=========================================================================*\
     
    230307   * init port pins used to address/select SPI devices
    231308   */
    232 #if defined(MPC8349EAMDS)
     309
     310#if defined( MPC8313ERDB)
     311
     312  /*
     313   * Configured as master (direct connection to SD card)
     314   *
     315   * GPIO[28] : SOUT
     316   * GPIO[29] : SIN
     317   * GPIO[30] : SCLK
     318   * GPIO[02] : SCS (inactive high), GPIO[02] is normally connected to U43 at
     319   * pin 15 of MC74LCX244DT.
     320   */
     321
     322  /* Function */
     323  mpc83xx.syscon.sicrl = (mpc83xx.syscon.sicrl & ~0x03fc0000) | 0x30000000;
     324
     325  /* Direction */
     326  mpc83xx.gpio [0].gpdir = (mpc83xx.gpio [0].gpdir & ~0x0000000f) | 0x2000000b;
     327
     328  /* Data */
     329  mpc83xx.gpio [0].gpdat |= 0x20000000;
     330
     331  /* Open Drain */
     332  /* mpc83xx.gpio [0].gpdr  |= 0x0000000f; */
     333
     334#elif defined( MPC8349EAMDS)
     335
    233336  /*
    234337   * GPIO1[0] is nSEL_SPI for M25P40
     
    238341  mpc83xx.gpio[0].gpdir |=  (1 << (31- 0));
    239342  mpc83xx.gpio[0].gpdr  &= ~(1 << (31- 0));
    240 #endif
    241 #if defined(HSC_CM01)
     343
     344#elif defined( HSC_CM01)
     345
    242346  /*
    243347   * GPIO1[24] is SPI_A0
     
    250354  mpc83xx.gpio[0].gpdir |=  (0xf << (31-27));
    251355  mpc83xx.gpio[0].gpdr  &= ~(0xf << (31-27));
    252 #endif
     356
     357#endif
     358
    253359  /*
    254360   * update base frequency in spi descriptor
     
    265371  }
    266372  spi_busno = ret_code;
    267 #if defined(MPC8349EAMDS)
     373
     374#if defined( MPC8313ERDB)
     375
     376  /* Register SD Card driver */
     377  ret_code = rtems_libi2c_register_drv(
     378    sd_card_driver_table [0].device_name,
     379    (rtems_libi2c_drv_t *) &sd_card_driver_table [0],
     380    spi_busno,
     381    0
     382  );
     383
     384#elif defined( MPC8349EAMDS)
     385
    268386  /*
    269387   * register M25P40 Flash
     
    272390                                       spi_flash_m25p40_rw_driver_descriptor,
    273391                                       spi_busno,0x00);
    274   if (ret_code < 0) {
    275     return -ret_code;
    276   }
    277 #endif
    278 #if defined(HSC_CM01)
     392#elif defined(HSC_CM01)
     393
    279394  /*
    280395   * register FM25L256 FRAM
     
    283398                                       spi_fram_fm25l256_rw_driver_descriptor,
    284399                                       spi_busno,0x02);
     400
     401#endif
     402
    285403  if (ret_code < 0) {
    286404    return -ret_code;
    287405  }
    288 #endif
     406
    289407  /*
    290408   * FIXME: further drivers, when available
  • c/src/lib/libbsp/powerpc/gen83xx/start/start.S

    r3c6fe2e r574fb67  
    1919/* $Id$ */   
    2020
    21 #include <rtems/asm.h>
     21#include <libcpu/powerpc-utility.h>
    2222#include <rtems/powerpc/cache.h>
    23 #include <rtems/powerpc/registers.h>
     23#include <bsp.h>
    2424#include <mpc83xx/mpc83xx.h>
    25 #include <bsp.h>
    26 
    27 /* Macro definitions to load a register with a 32-bit address.
    28    Both functions identically.  Sometimes one mnemonic is more
    29    appropriate than the other.
    30    reg          -> register to load
    31    value        -> value to be loaded
    32    LA  reg,value    ("Load Address")
    33    LWI reg,value    ("Load Word Immediate") */
    34 
    35 .macro LA reg, value
    36         lis \reg , \value@h
    37         ori \reg , \reg, \value@l
    38 .endm
    39 
    40 .macro LWI reg, value
    41         lis \reg , (\value)@h
    42         ori \reg , \reg, (\value)@l
    43 .endm
    4425
    4526.macro SET_IMM_REGW base, reg2, offset, value
     
    4829.endm
    4930
    50 /* Macro definitions to test, set or clear a single
    51    bit or bit pattern in a given 32bit GPR.
    52    reg1         -> register content to be tested
    53    reg2         -> 2nd register only needed for computation
    54    mask         -> any bit pattern */
    55 
    56 .macro  TSTBITS reg1, reg2, reg3, mask  /* Match is indicated by EQ=0 (CR) */
    57         LWI     \reg3, \mask            /* Unmatch is indicated by EQ=1 (CR) */
    58         and     \reg1, \reg1, \reg3
    59         and     \reg2, \reg2, \reg3
    60         cmplw   \reg1, \reg2
    61         sync
    62 .endm   
    63        
    64 .macro  SETBITS reg1, reg2, mask
    65         LWI     \reg2, \mask
    66         or      \reg1, \reg1, \reg2
    67         sync
    68 .endm
    69 
    70 .macro  CLRBITS reg1, reg2, mask
    71         LWI     \reg2, \mask
    72         andc    \reg1, \reg1, \reg2
    73         sync
    74 .endm
    75 
    7631#define REP8(l) l ; l; l; l; l; l; l; l;
    7732
    78 .extern _bss_start
    79 .extern _bss_size
    80 .extern _data_start
    81 .extern _data_size
    82 .extern _text_start
    83 .extern _text_size
    84 /*.extern _s_got*/
    8533.extern boot_card
    86 .extern MBAR   
     34.extern MBAR
    8735
    8836#if defined(RESET_CONF_WRD_L)
     
    10957PUBLIC_VAR (start)
    11058start:
     59
     60#ifdef HAS_UBOOT
     61
     62.extern mpc83xx_uboot_board_info
     63.extern mpc83xx_uboot_board_info_size
     64
     65        /* Reset time base */
     66        li      r0, 0
     67        mtspr   TBWU, r0
     68        mtspr   TBWL, r0
     69
     70        /* Copy board info */
     71        LA      r6, mpc83xx_uboot_board_info
     72        LW      r5, mpc83xx_uboot_board_info_size
     73        mtctr   r5
     74
     75copy_uboot_board_info:
     76
     77        lwz     r5, 0(r3)
     78        addi    r3, r3, 4
     79        stw     r5, 0(r6)
     80        addi    r6, r6, 4
     81        bdnz    copy_uboot_board_info
     82
     83#endif /* HAS_UBOOT */
     84
    11185        /*
    11286         * basic CPU setup:     
     
    11791        CLRBITS r30, r29, MSR_IP|MSR_EE
    11892        mtmsr   r30                             /* Set RI/ME, Clr EE in MSR */
     93
    11994        b start_rom_skip
    12095       
     
    166141         * ROM startup: jump to code final ROM location
    167142         */
    168         LA      r20, ROM_START /* ROM-RAM reloc in r20 */
     143        LA      r20, bsp_rom_start /* ROM-RAM reloc in r20 */
    169144        LA      r29, start_code_in_rom /* get compile time addr of label */
    170145        add     r29,r20,r29    /* compute exec address */
     
    381356         */
    382357        /* get start address of text section in RAM */
    383         LA      r29, _text_start 
     358        LA      r29, bsp_section_text_start 
    384359        /* get start address of text section in ROM (add reloc offset) */
    385360        add     r30, r20, r29   
    386361        /* get size of startup code */
    387362        LA      r28, end_reloc_startup
    388         LA      r31, _text_start
     363        LA      r31, bsp_section_text_start
    389364        sub     28,r28,r31
    390365        /* copy startup code from ROM to RAM location */
     
    410385        add     r30, r20, r29   
    411386        /* get size of rest of code */
    412         LA      r28, _text_start
    413         LA      r31, _text_size
     387        LA      r28, bsp_section_text_start
     388        LA      r31, bsp_section_text_size
    414389        add     r28,r28,r31
    415390        sub     r28,r28,r29
     
    420395         */
    421396        /* get start address of data section in RAM */
    422         LA      r29, _data_start
     397        LA      r29, bsp_section_data_start
    423398        /* get start address of data section in ROM (add reloc offset) */
    424399        add     r30, r20, r29   
    425400        /* get size of RAM image */
    426         LA      r28, _data_size 
     401        LA      r28, bsp_section_data_size 
    427402        /* copy initialized data section from ROM to RAM location */
    428403        bl      copy_image       
     
    433408         * ROM/RAM startup: clear bss in SDRAM
    434409         */
    435         LWI     r30, _bss_start  /* get start address of bss section */
    436         LWI     r29, _bss_size   /* get size of bss section */
    437         bl      clr_mem          /* Clear the bss section */
     410        LA      r3, bsp_section_bss_start  /* get start address of bss section */
     411        LWI     r4, bsp_section_bss_size   /* get size of bss section */
     412        bl      mpc83xx_zero_4          /* Clear the bss section */
    438413        /*
    439414         * call boot_card
    440415         */
    441 /* set stack pointer (common for RAM/ROM startup) */
    442         LA      r1, _text_start 
     416
     417        /* Set stack pointer (common for RAM/ROM startup) */
     418        LA      r1, bsp_section_text_start 
    443419        addi    r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */     
     420
     421        /* Create NULL */
     422        li r0, 0
     423
     424        /* Return address */
     425        stw r0, 4(r1)
     426
     427        /* Back chain */
     428        stw r0, 0(r1)
     429
     430        /* Read-only small data */
     431        LA r2, _SDA2_BASE_
     432
     433        /* Read-write small data */
     434        LA r13, _SDA_BASE_
     435
    444436/* clear arguments and do further init. in C (common for RAM/ROM startup) */
    445437        xor     r3, r3, r3
     
    487479        blr
    488480
    489 clr_mem:
    490         mr      r28, r29               
    491         srwi    r29, r29, 2
    492         mtctr   r29                             /* set ctr reg */
    493        
    494        
    495         slwi    r29, r29, 2
    496         sub     r28, r28, r29                   /* maybe some residual bytes */
    497         xor     r29, r29, r29           
    498        
    499        
    500 clr_mem_word:
    501         stswi   r29, r30, 0x04                  /* store r29 (word) to r30 memory location */
    502         addi    r30, r30, 0x04                  /* increment r30 */
    503        
    504         bdnz    clr_mem_word                    /* dec counter and loop */
    505        
    506        
    507         cmpwi   r28, 0x00                       /* clear mem. finished ? */
    508         beq     clr_mem_end;
    509         mtctr   r28                             /* reload counter for residual bytes */
    510 clr_mem_byte:
    511         stswi   r29, r30, 0x01                  /* store r29 (byte) to r30 memory location  */
    512         addi    r30, r30, 0x01                  /* update r30 */
    513        
    514         bdnz    clr_mem_byte                    /* dec counter and loop */
    515        
    516 clr_mem_end:
    517         blr                                     /* return */
     481       
     482/**
     483 * @fn int mpc83xx_zero_4( void *dest, size_t n)
     484 *
     485 * @brief Zero all @a n bytes starting at @a dest with 4 byte writes.
     486 *
     487 * The address @a dest has to be aligned on 4 byte boundaries.  The size @a n
     488 * must be evenly divisible by 4.
     489 */
     490GLOBAL_FUNCTION mpc83xx_zero_4
     491        /* Create zero */
     492        xor     r0, r0, r0
     493
     494        /* Set offset */
     495        xor     r5, r5, r5
     496
     497        /* Loop counter for the first bytes up to 16 bytes */
     498        rlwinm. r9, r4, 30, 30, 31
     499        beq     mpc83xx_zero_4_more
     500        mtctr   r9
     501
     502mpc83xx_zero_4_head:
     503
     504        stwx    r0, r3, r5
     505        addi    r5, r5, 8
     506        bdnz    mpc83xx_zero_4_head
     507
     508mpc83xx_zero_4_more:
     509
     510        /* More than 16 bytes? */
     511        srwi.   r9, r4, 4
     512        beqlr
     513        mtctr   r9
     514
     515        /* Set offsets */
     516        addi    r6, r5, 4
     517        addi    r7, r5, 8
     518        addi    r8, r5, 12
     519
     520mpc83xx_zero_4_tail:
     521
     522        stwx    r0, r3, r5
     523        addi    r5, r5, 16
     524        stwx    r0, r3, r6
     525        addi    r6, r6, 16
     526        stwx    r0, r3, r7
     527        addi    r7, r7, 16
     528        stwx    r0, r3, r8
     529        addi    r8, r8, 16
     530        bdnz    mpc83xx_zero_4_tail
     531       
     532        /* Return */
     533        blr
     534
    518535end_reloc_startup:
  • c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c

    r3c6fe2e r574fb67  
    1 /*===============================================================*\
    2 | Project: RTEMS generic MPC83xx BSP                              |
    3 +-----------------------------------------------------------------+
    4 |                    Copyright (c) 2007                           |
    5 |                    Embedded Brains GmbH                         |
    6 |                    Obere Lagerstr. 30                           |
    7 |                    D-82178 Puchheim                             |
    8 |                    Germany                                      |
    9 |                    rtems@embedded-brains.de                     |
    10 +-----------------------------------------------------------------+
    11 | The license and distribution terms for this file may be         |
    12 | found in the file LICENSE in this distribution or at            |
    13 |                                                                 |
    14 | http://www.rtems.com/license/LICENSE.                           |
    15 |                                                                 |
    16 +-----------------------------------------------------------------+
    17 | this file contains the BSP startup code                         |
    18 \*===============================================================*/
     1/**
     2 * @file
     3 *
     4 * @ingroup mpc83xx
     5 *
     6 * @brief Source for BSP startup code.
     7 */
    198
    209/*
    21  *  $Id$
    22  */
    23 
    24 #include <bsp.h>
     10 * Copyright (c) 2008
     11 * Embedded Brains GmbH
     12 * Obere Lagerstr. 30
     13 * D-82178 Puchheim
     14 * Germany
     15 * rtems@embedded-brains.de
     16 *
     17 * The license and distribution terms for this file may be found in the file
     18 * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
     19 *
     20 * $Id$
     21 */
     22
     23#include <string.h>
    2524
    2625#include <rtems/libio.h>
    2726#include <rtems/libcsupport.h>
    28 #include <rtems/powerpc/powerpc.h>
    2927#include <rtems/score/thread.h>
    3028
    31 #include <rtems/bspIo.h>
    32 #include <libcpu/cpuIdent.h>
    33 #include <libcpu/spr.h>
    34 #include <bsp/irq.h>
    35 
    36 #include <string.h>
    37 
    38 SPR_RW(SPRG0)
    39 SPR_RW(SPRG1)
    40 
    41 extern unsigned long intrStackPtr;
     29#include <libcpu/powerpc-utility.h>
     30
     31#include <bsp.h>
     32#include <bsp/irq-generic.h>
     33#include <bsp/ppc_exc_bspsupp.h>
     34
     35#ifdef HAS_UBOOT
     36
     37/*
     38 * We want this in the data section, because the startup code clears the BSS
     39 * section after the initialization of the board info.
     40 */
     41bd_t mpc83xx_uboot_board_info = { .bi_baudrate = 123 };
     42
     43/* Size in words */
     44const size_t mpc83xx_uboot_board_info_size = (sizeof( bd_t) + 3) / 4;
     45
     46#endif /* HAS_UBOOT */
     47
     48/* Configuration parameters for console driver, ... */
     49unsigned int BSP_bus_frequency;
     50
     51/* Configuration parameters for clock driver, ... */
     52uint32_t bsp_clicks_per_usec;
     53
    4254static char *BSP_heap_start, *BSP_heap_end;
    43 
    44 /*
    45  * constants for c_clock driver:
    46  * system bus frequency (for timebase etc)
    47  * and
    48  * Time base divisior: scaling value:
    49  * BSP_time_base_divisor = TB ticks per millisecond/BSP_bus_frequency
    50  */
    51 unsigned int BSP_bus_frequency;
    52 unsigned int BSP_time_base_divisor = 4000;  /* 4 bus clicks per TB click */
    53 
    54 /*
    55  *  Driver configuration parameters
    56  */
    57 uint32_t   bsp_clicks_per_usec;
    5855
    5956/*
     
    6158 *  Look in rtems/c/src/lib/libbsp/shared/bsplibc.c.
    6259 */
    63 void bsp_libc_init( void *, uint32_t, int );
    64 extern void initialize_exceptions(void);
    65 extern void cpu_init(void);
    66 
    67 void BSP_panic(char *s)
    68   {
    69   printk("%s PANIC %s\n",_RTEMS_version, s);
    70   /*
    71    * FIXME: hang/restart system
    72    */
    73   __asm__ __volatile ("sc");
    74   }
    75 
    76 void _BSP_Fatal_error(unsigned int v)
    77   {
    78   printk("%s PANIC ERROR %x\n",_RTEMS_version, v);
    79   /*
    80    * FIXME: hang/restart system
    81    */
    82   __asm__ __volatile ("sc");
    83   }
    84 
    85 /*
    86  *  Function:   bsp_pretasking_hook
    87  *  Created:    95/03/10
    88  *
    89  *  Description:
    90  *      BSP pretasking hook.  Called just before drivers are initialized.
    91  *      Used to setup libc and install any BSP extensions.
    92  *
    93  *  NOTES:
    94  *      Must not use libc (to do io) from here, since drivers are
    95  *      not yet initialized.
    96  *
    97  */
    98 
    99 void
    100 bsp_pretasking_hook(void)
    101 {
    102 
    103   /*
    104    * initialize libc including the heap
    105    */
    106   bsp_libc_init( BSP_heap_start,
    107                  BSP_heap_end - BSP_heap_start,
    108                  0);
     60extern void cpu_init( void);
     61
     62void BSP_panic( char *s)
     63{
     64        rtems_interrupt_level level;
     65
     66        rtems_interrupt_disable( level);
     67
     68        printk( "%s PANIC %s\n", _RTEMS_version, s);
     69
     70        while (1) {
     71                /* Do nothing */
     72        }
     73}
     74
     75void _BSP_Fatal_error( unsigned n)
     76{
     77        rtems_interrupt_level level;
     78
     79        rtems_interrupt_disable( level);
     80
     81        printk( "%s PANIC ERROR %u\n", _RTEMS_version, n);
     82
     83        while (1) {
     84                /* Do nothing */
     85        }
     86}
     87
     88void bsp_pretasking_hook( void)
     89{
     90        /* Initialize libc including the heap */
     91        bsp_libc_init( BSP_heap_start, BSP_heap_end - BSP_heap_start, 0);
    10992}
    11093
    11194void bsp_calc_mem_layout()
    11295{
    113   /*
    114    * these labels (!) are defined in the linker command file
    115    * or when the linker is invoked
    116    * NOTE: the information(size) is the address of the object,
    117    * not the object otself
    118    */
    119   extern unsigned char TopRamReserved;
    120   extern unsigned char _WorkspaceBase[];
    121 
    122   /*
    123    * compute the memory layout:
    124    * - first unused address is Workspace start
    125    * - Heap starts at end of workspace
    126    * - Heap ends at end of memory - reserved memory area
    127    */
    128   Configuration.work_space_start = _WorkspaceBase;
    129 
    130   BSP_heap_start = ((char *)Configuration.work_space_start +
    131                     rtems_configuration_get_work_space_size());
    132 
    133 #if defined(HAS_UBOOT)
    134   BSP_heap_end = (uboot_bdinfo_ptr->bi_memstart
    135                   + uboot_bdinfo_ptr->bi_memsize
    136                   - (uint32_t)&TopRamReserved);
    137 #else
    138   BSP_heap_end = (void *)(RAM_END - (uint32_t)&TopRamReserved);
     96        size_t workspace_size = rtems_configuration_get_work_space_size();
     97
     98        /* We clear the workspace here */
     99        Configuration.do_zero_of_workspace = 0;
     100        /*
     101        TODO
     102        mpc83xx_zero_4( bsp_workspace_start, workspace_size);
     103         */
     104        mpc83xx_zero_4( bsp_interrupt_stack_start, bsp_ram_end - bsp_interrupt_stack_start);
     105
     106        Configuration.work_space_start = bsp_workspace_start;
     107
     108        BSP_heap_start = (char *) Configuration.work_space_start + workspace_size;
     109
     110#ifdef HAS_UBOOT
     111        BSP_heap_end = mpc83xx_uboot_board_info.bi_memstart + mpc83xx_uboot_board_info.bi_memsize;
     112#else /* HAS_UBOOT */
     113        BSP_heap_end = bsp_ram_end;
     114#endif /* HAS_UBOOT */
     115}
     116
     117void bsp_start( void)
     118{
     119        ppc_cpu_id_t myCpu;
     120        ppc_cpu_revision_t myCpuRevision;
     121
     122        uint32_t interrupt_stack_start = (uint32_t) bsp_interrupt_stack_start;
     123        uint32_t interrupt_stack_size = (uint32_t) bsp_interrupt_stack_size;
     124
     125        /*
     126         * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
     127         * store the result in global variables so that it can be used latter...
     128         */
     129        myCpu = get_ppc_cpu_type();
     130        myCpuRevision = get_ppc_cpu_revision();
     131
     132        /* Determine heap and workspace placement */
     133        bsp_calc_mem_layout();
     134
     135        cpu_init();
     136
     137        /*
     138         * This is evaluated during runtime, so it should be ok to set it
     139         * before we initialize the drivers.
     140         */
     141
     142        /* Initialize some device driver parameters */
     143
     144#ifdef HAS_UBOOT
     145        BSP_bus_frequency = mpc83xx_uboot_board_info.bi_busfreq;
     146#else /* HAS_UBOOT */
     147        BSP_bus_frequency = BSP_CLKIN_FRQ * BSP_SYSPLL_MF / BSP_SYSPLL_CKID;
     148#endif /* HAS_UBOOT */
     149
     150        bsp_clicks_per_usec = BSP_bus_frequency / 4000000;
     151
     152        /*
     153         * Enable instruction and data caches. Do not force writethrough mode.
     154         */
     155
     156#if INSTRUCTION_CACHE_ENABLE
     157        rtems_cache_enable_instruction();
    139158#endif
    140159
    141 }
    142 
    143 
    144 void bsp_start(void)
    145 {
    146   ppc_cpu_id_t myCpu;
    147   ppc_cpu_revision_t myCpuRevision;
    148   register unsigned char* intrStack;
    149 
    150   /*
    151    * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
    152    * store the result in global variables so that it can be used latter...
    153    */
    154   myCpu             = get_ppc_cpu_type();
    155   myCpuRevision = get_ppc_cpu_revision();
    156   /*
    157    * determine heap and workspace placement
    158    */
    159   bsp_calc_mem_layout();
    160 
    161   cpu_init();
    162 
    163   /*
    164    * Initialize some SPRG registers related to irq handling
    165    */
    166 
    167   intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE);
    168 
    169   _write_SPRG1((unsigned int)intrStack);
    170 
    171   /* Signal them that this BSP has fixed PR288 - eventually, this should
    172    * go away
    173    */
    174   _write_SPRG0(PPC_BSP_HAS_FIXED_PR288);
    175 
    176   /*
    177    * this is evaluated during runtime, so it should be ok to set it
    178    * before we initialize the drivers
    179    */
    180   BSP_bus_frequency   = BSP_CLKIN_FRQ * BSP_SYSPLL_MF / BSP_SYSPLL_CKID;
    181   /*
    182    *  initialize the device driver parameters
    183    */
    184   bsp_clicks_per_usec = (BSP_bus_frequency/1000000);
    185 
    186   /*
    187    * Install our own set of exception vectors
    188    */
    189 
    190   initialize_exceptions();
    191 
    192   /*
    193    * Enable instruction and data caches. Do not force writethrough mode.
    194    */
    195 #if INSTRUCTION_CACHE_ENABLE
    196   rtems_cache_enable_instruction();
     160#if DATA_CACHE_ENABLE
     161        rtems_cache_enable_data();
    197162#endif
    198 #if DATA_CACHE_ENABLE
    199   rtems_cache_enable_data();
     163
     164        /* Initialize exception handler */
     165        ppc_exc_initialize(
     166                PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
     167                interrupt_stack_start,
     168                interrupt_stack_size
     169        );
     170
     171        /* Initalize interrupt support */
     172        if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) {
     173                BSP_panic("Cannot intitialize interrupt support\n");
     174        }
     175
     176#ifdef SHOW_MORE_INIT_SETTINGS
     177        printk("Exit from bspstart\n");
    200178#endif
    201 
    202   /*
    203    *  Allocate the memory for the RTEMS Work Space.  This can come from
    204    *  a variety of places: hard coded address, malloc'ed from outside
    205    *  RTEMS world (e.g. simulator or primitive memory manager), or (as
    206    *  typically done by stock BSPs) by subtracting the required amount
    207    *  of work space from the last physical address on the CPU board.
    208    */
    209 
    210   /*
    211    * Initalize RTEMS IRQ system
    212    */
    213   BSP_rtems_irq_mng_init(0);
    214 
    215 #ifdef SHOW_MORE_INIT_SETTINGS
    216   printk("Exit from bspstart\n");
    217 #endif
    218 
    219   }
    220 
    221 /*
    222  *
    223  *  _Thread_Idle_body
    224  *
    225  *  Replaces the one in c/src/exec/score/src/threadidlebody.c
    226  *  The MSR[POW] bit is set to put the CPU into the low power mode
    227  *  defined in HID0.  HID0 is set during starup in start.S.
    228  *
    229  */
    230 Thread _Thread_Idle_body(uint32_t ignored )
    231   {
    232 
    233   for(;;)
    234     {
    235 
    236     asm volatile("mfmsr 3; oris 3,3,4; sync; mtmsr 3; isync; ori 3,3,0; ori 3,3,0");
    237 
    238     }
    239 
    240   return 0;
    241 
    242   }
    243 
     179}
     180
     181/**
     182 * @brief Idle thread body.
     183 *
     184 * Replaces the one in c/src/exec/score/src/threadidlebody.c
     185 * The MSR[POW] bit is set to put the CPU into the low power mode
     186 * defined in HID0.  HID0 is set during starup in start.S.
     187 */
     188Thread _Thread_Idle_body( uint32_t ignored)
     189{
     190
     191        while (1) {
     192                asm volatile (
     193                        "mfmsr 3;"
     194                        "oris 3, 3, 4;"
     195                        "sync;"
     196                        "mtmsr 3;"
     197                        "isync;"
     198                        "ori 3, 3, 0;"
     199                        "ori 3, 3, 0"
     200                );
     201        }
     202
     203        return NULL;
     204}
  • c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c

    r3c6fe2e r574fb67  
    156156   */
    157157  GET_HID0(reg);
    158   reg |=  (HID0_ICFI | HID0_DCI);
     158  reg = (reg & ~(HID0_ILOCK | HID0_DLOCK)) | HID0_ICFI | HID0_DCI;
    159159  SET_HID0(reg);
    160160  reg &= ~(HID0_ICFI | HID0_DCI);
     
    171171  SET_IBAT(6,ibat.batu,ibat.batl);
    172172  SET_IBAT(7,ibat.batu,ibat.batl);
    173 
    174   calc_dbat_regvals(&ibat,RAM_START,RAM_SIZE,0,0,0,0,BPP_RX);
     173#ifdef HAS_UBOOT
     174  calc_dbat_regvals(&ibat,mpc83xx_uboot_board_info.bi_memstart,mpc83xx_uboot_board_info.bi_memsize,0,0,0,0,BPP_RX);
     175#else /* HAS_UBOOT */
     176  calc_dbat_regvals(&ibat,(uint32_t) bsp_ram_start,(uint32_t) bsp_ram_size,0,0,0,0,BPP_RX);
     177#endif /* HAS_UBOOT */
     178
    175179  SET_IBAT(0,ibat.batu,ibat.batl);
    176   calc_dbat_regvals(&ibat,ROM_START,ROM_SIZE,0,0,0,0,BPP_RX);
     180
     181#ifdef HAS_UBOOT
     182  calc_dbat_regvals(&ibat,mpc83xx_uboot_board_info.bi_flashstart,mpc83xx_uboot_board_info.bi_flashsize,0,0,0,0,BPP_RX);
     183#else /* HAS_UBOOT */
     184  calc_dbat_regvals(&ibat,(uint32_t) bsp_rom_start,(uint32_t) bsp_rom_size,0,0,0,0,BPP_RX);
     185#endif /* HAS_UBOOT */
     186
    177187  SET_IBAT(1,ibat.batu,ibat.batl);
    178188
     
    187197  SET_DBAT(7,dbat.batu,dbat.batl);
    188198
    189   calc_dbat_regvals(&dbat,RAM_START,RAM_SIZE,1,0,1,0,BPP_RW);
     199#ifdef HAS_UBOOT
     200  calc_dbat_regvals(&dbat,mpc83xx_uboot_board_info.bi_memstart,mpc83xx_uboot_board_info.bi_memsize,0,0,0,0,BPP_RW);
     201#else /* HAS_UBOOT */
     202  calc_dbat_regvals(&dbat,(uint32_t) bsp_ram_start,(uint32_t) bsp_ram_size,0,0,0,0,BPP_RW);
     203#endif /* HAS_UBOOT */
     204
    190205  SET_DBAT(0,dbat.batu,dbat.batl);
    191206
    192   calc_dbat_regvals(&dbat,ROM_START,ROM_SIZE,1,0,1,0,BPP_RX);
     207#ifdef HAS_UBOOT
     208  calc_dbat_regvals(&dbat,mpc83xx_uboot_board_info.bi_flashstart,mpc83xx_uboot_board_info.bi_flashsize,0,0,0,0,BPP_RX);
     209#else /* HAS_UBOOT */
     210  calc_dbat_regvals(&dbat,(uint32_t) bsp_rom_start,(uint32_t) bsp_rom_size,0,0,0,0,BPP_RX);
     211#endif /* HAS_UBOOT */
     212
    193213  SET_DBAT(1,dbat.batu,dbat.batl);
    194214
    195   calc_dbat_regvals(&dbat,IMMRBAR,1024*1024,1,1,1,1,BPP_RW);
     215#ifdef HAS_UBOOT
     216  calc_dbat_regvals(&dbat,mpc83xx_uboot_board_info.bi_immrbar,1024*1024,0,1,0,1,BPP_RW);
     217#else /* HAS_UBOOT */
     218  calc_dbat_regvals(&dbat,(uint32_t) IMMRBAR,1024*1024,0,1,0,1,BPP_RW);
     219#endif /* HAS_UBOOT */
     220
    196221  SET_DBAT(2,dbat.batu,dbat.batl);
    197222
  • c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.hsc_cm01

    r3c6fe2e r574fb67  
    1 /*
    2  *  This file contains directives for the GNU linker which are specific
    3  *  to a hsc_cm01 board
     1/**
     2 * @file
    43 *
    5  *  $Id$
     4 * HSC_CM01 Board.
    65 */
    76
    8 OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc",
    9               "elf32-powerpc")
    10 OUTPUT_ARCH(powerpc)
    11  
    12 ENTRY(start)
     7MEMORY {
     8        RAM : ORIGIN = 0x0, LENGTH = 256M
     9        ROM : ORIGIN = 0xfe000000, LENGTH = 8M
     10        MPC83XX_REGS : ORIGIN = 0xe0000000, LENGTH = 256k
     11        NIRVANA : ORIGIN = 0x0, LENGTH = 0
     12}
    1313
    14 /*
    15  * Declare some sizes.
    16  * XXX: The assignment of ". += XyzSize;" fails in older gld's if the
    17  *      number used there is not constant.  If this happens to you, edit
    18  *      the lines marked XXX below to use a constant value.
    19  */
    20 HeapSize = DEFINED(HeapSize) ? HeapSize    : 0x6800000;  /* 104M  Heap */
    21 StackSize = DEFINED(StackSize) ? StackSize :   0x80000;  /* 512 kB   */
    22 WorkSpaceSize = DEFINED(WorkSpaceSize) ? WorkSpaceSize : 0x80000; /* 512k */
    23 RamDiskSize = DEFINED(RamDiskSize) ? RamDiskSize : 0x80000; /* 512 ram disk */
    24 
    25 /*
    26  * optionally reserve additional space
    27  */
    28 TopRamReserved = DEFINED(TopRamReserved) ? TopRamReserved : 0;
    29  
    30 MEMORY
    31         {
    32         ram          : org = 0x0,        l = 256M
    33         mpc83xx_regs : org = 0xE0000000, l = 256k
    34         }
    35 
    36 
    37 SECTIONS
    38 {
    39 
    40     .mpc83xx_regs (NOLOAD) :
    41     {
    42     IMMRBAR = .;
    43     mpc83xx_regs*(.text)
    44     mpc83xx_regs*(.data)
    45     mpc83xx_regs*(.bss)
    46     mpc83xx_regs*(*COM*)
    47     } > mpc83xx_regs
    48 
    49    .resconf 0x000 :
    50     {
    51     *(.resconf)
    52     } > ram
    53 
    54    .vectors 0x100 :
    55     {
    56     *(.vectors)
    57     }   
    58     > ram
    59 
    60     /*
    61      * The stack will live in this area - between the vectors and
    62      * the text section.
    63      */
    64        
    65     .text 0x10000:
    66     {
    67     _textbase = .;
    68 
    69 
    70     text.start = .;
    71 
    72     /* Entry point is the .entry section */
    73     *(.entry)
    74     *(.entry2)
    75 
    76     /* Actual Code */
    77     *(.text*)
    78 
    79     *(.rodata*)
    80     *(.rodata1)
    81 
    82 
    83     /*
    84      * Special FreeBSD sysctl sections.
    85      */
    86     . = ALIGN (16);
    87     __start_set_sysctl_set = .;
    88     *(set_sysctl_*);
    89     __stop_set_sysctl_set = ABSOLUTE(.);
    90     *(set_domain_*);
    91     *(set_pseudo_*);
    92 
    93     /* C++ constructors/destructors */
    94     *(.gnu.linkonce.t*)
    95 
    96     /*  Initialization and finalization code.
    97      *
    98      *  Various files can provide initialization and finalization functions.
    99      *  The bodies of these functions are in .init and .fini sections. We
    100      *  accumulate the bodies here, and prepend function prologues from
    101      *  ecrti.o and function epilogues from ecrtn.o. ecrti.o must be linked
    102      *  first; ecrtn.o must be linked last. Because these are wildcards, it
    103      *  doesn't matter if the user does not actually link against ecrti.o and
    104      *  ecrtn.o; the linker won't look for a file to match a wildcard.  The
    105      *  wildcard also means that it doesn't matter which directory ecrti.o
    106      *  and ecrtn.o are in.
    107      */
    108     PROVIDE (_init = .);
    109     *ecrti.o(.init)
    110     *(.init)
    111     *ecrtn.o(.init)
    112    
    113     PROVIDE (_fini = .);
    114     *ecrti.o(.fini)
    115     *(.fini)
    116     *ecrtn.o(.init)
    117 
    118     /*
    119      *  C++ constructors and destructors for static objects.
    120      *  PowerPC EABI does not use crtstuff yet, so we build "old-style"
    121      *  constructor and destructor lists that begin with the list lenght
    122      *  end terminate with a NULL entry.
    123      */
    124      
    125     PROVIDE (__CTOR_LIST__ = .);             
    126     *crtbegin.o(.ctors)
    127     *(.ctors)
    128     *crtend.o(.ctors)
    129     LONG(0)
    130     PROVIDE (__CTOR_END__ = .);
    131        
    132     PROVIDE (__DTOR_LIST__ = .);
    133     *crtbegin.o(.dtors)
    134     *(.dtors)
    135     *crtend.o(.dtors)
    136     LONG(0)
    137     PROVIDE (__DTOR_END__ = .);
    138        
    139     /* Exception frame info */
    140     *(.eh_frame)
    141 
    142     /* Miscellaneous read-only data */
    143     _rodata_start = . ;
    144     *(.gnu.linkonce.r*)
    145     *(.lit)
    146     *(.shdata)
    147     *(.rodata)
    148     *(.rodata1)
    149     *(.descriptors)
    150     *(rom_ver)
    151     _erodata = .;
    152 
    153     PROVIDE (__EXCEPT_START__ = .);
    154     *(.gcc_except_table*)
    155     PROVIDE (__EXCEPT_END__ = .);
    156     __GOT_START__ = .;
    157     s.got = .;
    158     *(.got.plt)
    159     *(.got)
    160     *(.got1)
    161     PROVIDE (__GOT2_START__ = .);
    162     PROVIDE (_GOT2_START_ = .);
    163     *(.got2)
    164     PROVIDE (__GOT2_END__ = .);
    165     PROVIDE (_GOT2_END_ = .);
    166    
    167     PROVIDE (__FIXUP_START__ = .);
    168     PROVIDE (_FIXUP_START_ = .);
    169     *(.fixup)
    170     PROVIDE (_FIXUP_END_ = .);
    171     PROVIDE (__FIXUP_END__ = .);
    172    
    173 
    174     /* Various possible names for the end of the .text section */
    175     etext = ALIGN(0x10);
    176     _etext = .;
    177     _endtext = .;
    178     text.end = .;
    179     PROVIDE (etext = .);
    180     PROVIDE (__etext = .);
    181  
    182     } > ram
    183 
    184   .jcr : { KEEP (*(.jcr)) } > ram
    185 
    186     .rel.dyn : {
    187       *(.rel.init)
    188       *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
    189       *(.rel.fini)
    190       *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
    191       *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*)
    192       *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
    193       *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
    194       *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
    195       *(.rel.ctors)
    196       *(.rel.dtors)
    197       *(.rel.got)
    198       *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)
    199       *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)
    200       *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)
    201       *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)
    202       *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
    203     } >ram
    204     .rela.dyn : {
    205       *(.rela.init)
    206       *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
    207       *(.rela.fini)
    208       *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
    209       *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
    210       *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
    211       *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
    212       *(.rela.ctors)
    213       *(.rela.dtors)
    214       *(.rela.got)
    215       *(.rela.got1)
    216       *(.rela.got2)
    217       *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
    218       *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
    219       *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
    220       *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
    221       *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
    222     } >ram
    223 
    224     PROVIDE (__SDATA2_START__ = .);
    225   .sdata2         : { *(.sdata2) *(.gnu.linkonce.s2.*)  } >ram
    226   .sbss2          : { *(.sbss2) *(.gnu.linkonce.sb2.*)  } >ram
    227     PROVIDE (__SBSS2_END__ = .);
    228        
    229     .sbss2        : { *(.sbss2)         } >ram
    230     PROVIDE (__SBSS2_END__ = .);
    231        
    232     /* R/W Data */
    233     .data ( . ) :
    234     {
    235       . = ALIGN (4);
    236 
    237       data.start = .;
    238 
    239       *(.data)
    240       *(.data1)
    241       *(.data.* .gnu.linkonce.d.*)
    242       PROVIDE (__SDATA_START__ = .);
    243       *(.sdata*)
    244       *(.gnu.linkonce.s.*)
    245       data.end = .;
    246     } > ram
    247 
    248     __SBSS_START__ = .;
    249     .bss :
    250     {
    251       bss.start = .;
    252       *(.bss .bss* .gnu.linkonce.b*)
    253       *(.sbss*) *(COMMON)
    254       . = ALIGN(4);
    255       bss.end = .;
    256     } > ram
    257     __SBSS_END__ = .;
    258 
    259     PROVIDE(_bss_start   = ADDR(.bss));
    260     PROVIDE(_bss_size    = SIZEOF(.bss));
    261     PROVIDE(_data_start  = ADDR(.data));
    262     PROVIDE(_data_size   = SIZEOF(.data));
    263     PROVIDE(_text_start  = ADDR(.text));
    264     PROVIDE(_text_size   = SIZEOF(.text));
    265     PROVIDE(_end = data.end);
    266 
    267     .gzipmalloc : {
    268         . = ALIGN (16);
    269         _startmalloc = .;
    270      } >ram
    271                
    272 
    273     /*
    274      * Interrupt stack setup
    275      */
    276     IntrStack_start = ALIGN(0x10);
    277     . += 0x4000;
    278     intrStack = .;
    279     PROVIDE(intrStackPtr = intrStack);
    280 
    281 
    282 
    283 
    284     _WorkspaceBase = .;
    285     __WorkspaceBase = .;
    286     . += WorkSpaceSize;
    287 
    288     _RamDiskBase = .;
    289     __RamDiskBase = .;
    290     . += RamDiskSize;
    291     _RamDiskEnd  = .;
    292     __RamDiskEnd = .;
    293     PROVIDE( _RamDiskSize = _RamDiskEnd - _RamDiskBase );
    294 
    295     _HeapStart = .;
    296     __HeapStart = .;
    297     . += HeapSize;
    298     _HeapEnd = .;
    299     __HeapEnd = .;
    300 
    301     clear_end = .;
    302 
    303     /* Sections for compressed .text and .data         */
    304     /* after the .datarom section is an int specifying */
    305     /* the length of the following compressed image    */
    306     /* Executes once then could get overwritten        */
    307     .textrom 0x100000 :
    308     {
    309         *(.textrom)
    310         _endloader = .;
    311     } > ram
    312 
    313     .datarom :
    314     {
    315         _dr_start = .;
    316         *(.datarom)
    317         _dr_end = .;
    318     } > ram
    319     dr_len = _dr_end - _dr_start;
    320 
    321 
    322     .line 0 : { *(.line) }
    323     .debug 0 : { *(.debug) }
    324     .debug_sfnames 0 : { *(.debug_sfnames) }
    325     .debug_srcinfo 0 : { *(.debug_srcinfo) }
    326     .debug_pubnames 0 : { *(.debug_pubnames) }
    327     .debug_aranges 0 : { *(.debug_aranges) }
    328     .debug_aregion 0 : { *(.debug_aregion) }
    329     .debug_macinfo 0 : { *(.debug_macinfo) }
    330     .stab 0 : { *(.stab) }
    331     .stabstr 0 : { *(.stabstr) }
    332 }
     14INCLUDE linkcmds.base
  • c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.mpc8349eamds

    r3c6fe2e r574fb67  
    1 /*
    2  *  This file contains directives for the GNU linker which are specific
    3  *  to a gen8349eamds board
     1/**
     2 * @file
    43 *
    5  *  $Id$
     4 * MPC8349EAMDS Board.
    65 */
    76
    8 OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc",
    9               "elf32-powerpc")
    10 OUTPUT_ARCH(powerpc)
    11  
    12 ENTRY(start)
     7MEMORY {
     8        RAM : ORIGIN = 0x0, LENGTH = 256M
     9        ROM : ORIGIN = 0xfe000000, LENGTH = 8M
     10        MPC83XX_REGS : ORIGIN = 0xe0000000, LENGTH = 256k
     11        NIRVANA : ORIGIN = 0x0, LENGTH = 0
     12}
    1313
    14 /*
    15  * Declare some sizes.
    16  * XXX: The assignment of ". += XyzSize;" fails in older gld's if the
    17  *      number used there is not constant.  If this happens to you, edit
    18  *      the lines marked XXX below to use a constant value.
    19  */
    20 HeapSize = DEFINED(HeapSize) ? HeapSize    : 0x6800000;  /* 104M  Heap */
    21 StackSize = DEFINED(StackSize) ? StackSize :   0x80000;  /* 512 kB   */
    22 WorkSpaceSize = DEFINED(WorkSpaceSize) ? WorkSpaceSize : 0x80000; /* 512k */
    23 RamDiskSize = DEFINED(RamDiskSize) ? RamDiskSize : 0x80000; /* 512 ram disk */
    24 
    25 /*
    26  * optionally reserve additional space
    27  */
    28 TopRamReserved = DEFINED(TopRamReserved) ? TopRamReserved : 0;
    29  
    30 MEMORY
    31         {
    32         ram          : org = 0x0,        l = 256M
    33         mpc83xx_regs : org = 0xE0000000, l = 256k
    34         }
    35 
    36 
    37 SECTIONS
    38 {
    39 
    40     mpc83xx_regs (NOLOAD) :
    41     {
    42     IMMRBAR = .;
    43     mpc83xx_regs*(.text)
    44     mpc83xx_regs*(.data)
    45     mpc83xx_regs*(.bss)
    46     mpc83xx_regs*(*COM*)
    47     } > mpc83xx_regs
    48 
    49    .resconf 0x000 :
    50     {
    51     *(.resconf)
    52     } > ram
    53 
    54    .vectors 0x100 :
    55     {
    56     *(.vectors)
    57     }   
    58     > ram
    59 
    60     /*
    61      * The stack will live in this area - between the vectors and
    62      * the text section.
    63      */
    64        
    65     .text 0x10000:
    66     {
    67     _textbase = .;
    68 
    69 
    70     text.start = .;
    71 
    72     /* Entry point is the .entry section */
    73     *(.entry)
    74     *(.entry2)
    75 
    76     /* Actual Code */
    77     *(.text*)
    78 
    79     *(.rodata*)
    80     *(.rodata1)
    81 
    82 
    83     /*
    84      * Special FreeBSD sysctl sections.
    85      */
    86     . = ALIGN (16);
    87     __start_set_sysctl_set = .;
    88     *(set_sysctl_*);
    89     __stop_set_sysctl_set = ABSOLUTE(.);
    90     *(set_domain_*);
    91     *(set_pseudo_*);
    92 
    93     /* C++ constructors/destructors */
    94     *(.gnu.linkonce.t*)
    95 
    96     /*  Initialization and finalization code.
    97      *
    98      *  Various files can provide initialization and finalization functions.
    99      *  The bodies of these functions are in .init and .fini sections. We
    100      *  accumulate the bodies here, and prepend function prologues from
    101      *  ecrti.o and function epilogues from ecrtn.o. ecrti.o must be linked
    102      *  first; ecrtn.o must be linked last. Because these are wildcards, it
    103      *  doesn't matter if the user does not actually link against ecrti.o and
    104      *  ecrtn.o; the linker won't look for a file to match a wildcard.  The
    105      *  wildcard also means that it doesn't matter which directory ecrti.o
    106      *  and ecrtn.o are in.
    107      */
    108     PROVIDE (_init = .);
    109     *ecrti.o(.init)
    110     *(.init)
    111     *ecrtn.o(.init)
    112    
    113     PROVIDE (_fini = .);
    114     *ecrti.o(.fini)
    115     *(.fini)
    116     *ecrtn.o(.init)
    117 
    118     /*
    119      *  C++ constructors and destructors for static objects.
    120      *  PowerPC EABI does not use crtstuff yet, so we build "old-style"
    121      *  constructor and destructor lists that begin with the list lenght
    122      *  end terminate with a NULL entry.
    123      */
    124      
    125     PROVIDE (__CTOR_LIST__ = .);             
    126     *crtbegin.o(.ctors)
    127     *(.ctors)
    128     *crtend.o(.ctors)
    129     LONG(0)
    130     PROVIDE (__CTOR_END__ = .);
    131        
    132     PROVIDE (__DTOR_LIST__ = .);
    133     *crtbegin.o(.dtors)
    134     *(.dtors)
    135     *crtend.o(.dtors)
    136     LONG(0)
    137     PROVIDE (__DTOR_END__ = .);
    138        
    139     /* Exception frame info */
    140     *(.eh_frame)
    141 
    142     /* Miscellaneous read-only data */
    143     _rodata_start = . ;
    144     *(.gnu.linkonce.r*)
    145     *(.lit)
    146     *(.shdata)
    147     *(.rodata)
    148     *(.rodata1)
    149     *(.descriptors)
    150     *(rom_ver)
    151     _erodata = .;
    152 
    153     PROVIDE (__EXCEPT_START__ = .);
    154     *(.gcc_except_table*)
    155     PROVIDE (__EXCEPT_END__ = .);
    156     __GOT_START__ = .;
    157     s.got = .;
    158     *(.got.plt)
    159     *(.got)
    160     *(.got1)
    161     PROVIDE (__GOT2_START__ = .);
    162     PROVIDE (_GOT2_START_ = .);
    163     *(.got2)
    164     PROVIDE (__GOT2_END__ = .);
    165     PROVIDE (_GOT2_END_ = .);
    166    
    167     PROVIDE (__FIXUP_START__ = .);
    168     PROVIDE (_FIXUP_START_ = .);
    169     *(.fixup)
    170     PROVIDE (_FIXUP_END_ = .);
    171     PROVIDE (__FIXUP_END__ = .);
    172    
    173 
    174     /* Various possible names for the end of the .text section */
    175     etext = ALIGN(0x10);
    176     _etext = .;
    177     _endtext = .;
    178     text.end = .;
    179     PROVIDE (etext = .);
    180     PROVIDE (__etext = .);
    181  
    182     } > ram
    183 
    184   .jcr : { KEEP (*(.jcr)) } > ram
    185 
    186     .rel.dyn : {
    187       *(.rel.init)
    188       *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
    189       *(.rel.fini)
    190       *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
    191       *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*)
    192       *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
    193       *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
    194       *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
    195       *(.rel.ctors)
    196       *(.rel.dtors)
    197       *(.rel.got)
    198       *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)
    199       *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)
    200       *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)
    201       *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)
    202       *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
    203     } >ram
    204     .rela.dyn : {
    205       *(.rela.init)
    206       *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
    207       *(.rela.fini)
    208       *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
    209       *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
    210       *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
    211       *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
    212       *(.rela.ctors)
    213       *(.rela.dtors)
    214       *(.rela.got)
    215       *(.rela.got1)
    216       *(.rela.got2)
    217       *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
    218       *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
    219       *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
    220       *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
    221       *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
    222     } >ram
    223 
    224     PROVIDE (__SDATA2_START__ = .);
    225   .sdata2         : { *(.sdata2) *(.gnu.linkonce.s2.*)  } >ram
    226   .sbss2          : { *(.sbss2) *(.gnu.linkonce.sb2.*)  } >ram
    227     PROVIDE (__SBSS2_END__ = .);
    228        
    229     .sbss2        : { *(.sbss2)         } >ram
    230     PROVIDE (__SBSS2_END__ = .);
    231        
    232     /* R/W Data */
    233     .data ( . ) :
    234     {
    235       . = ALIGN (4);
    236 
    237       data.start = .;
    238 
    239       *(.data)
    240       *(.data1)
    241       *(.data.* .gnu.linkonce.d.*)
    242       PROVIDE (__SDATA_START__ = .);
    243       *(.sdata*)
    244       *(.gnu.linkonce.s.*)
    245       data.end = .;
    246     } > ram
    247 
    248     __SBSS_START__ = .;
    249     .bss :
    250     {
    251       bss.start = .;
    252       *(.bss .bss* .gnu.linkonce.b*)
    253       *(.sbss*) *(COMMON)
    254       . = ALIGN(4);
    255       bss.end = .;
    256     } > ram
    257     __SBSS_END__ = .;
    258 
    259     PROVIDE(_bss_start   = ADDR(.bss));
    260     PROVIDE(_bss_size    = SIZEOF(.bss));
    261     PROVIDE(_data_start  = ADDR(.data));
    262     PROVIDE(_data_size   = SIZEOF(.data));
    263     PROVIDE(_text_start  = ADDR(.text));
    264     PROVIDE(_text_size   = SIZEOF(.text));
    265     PROVIDE(_end = data.end);
    266 
    267     .gzipmalloc : {
    268         . = ALIGN (16);
    269         _startmalloc = .;
    270      } >ram
    271                
    272 
    273     /*
    274      * Interrupt stack setup
    275      */
    276     IntrStack_start = ALIGN(0x10);
    277     . += 0x4000;
    278     intrStack = .;
    279     PROVIDE(intrStackPtr = intrStack);
    280 
    281 
    282 
    283 
    284     _WorkspaceBase = .;
    285     __WorkspaceBase = .;
    286     . += WorkSpaceSize;
    287 
    288     _RamDiskBase = .;
    289     __RamDiskBase = .;
    290     . += RamDiskSize;
    291     _RamDiskEnd  = .;
    292     __RamDiskEnd = .;
    293     PROVIDE( _RamDiskSize = _RamDiskEnd - _RamDiskBase );
    294 
    295     _HeapStart = .;
    296     __HeapStart = .;
    297     . += HeapSize;
    298     _HeapEnd = .;
    299     __HeapEnd = .;
    300 
    301     clear_end = .;
    302 
    303     /* Sections for compressed .text and .data         */
    304     /* after the .datarom section is an int specifying */
    305     /* the length of the following compressed image    */
    306     /* Executes once then could get overwritten        */
    307     .textrom 0x100000 :
    308     {
    309         *(.textrom)
    310         _endloader = .;
    311     } > ram
    312 
    313     .datarom :
    314     {
    315         _dr_start = .;
    316         *(.datarom)
    317         _dr_end = .;
    318     } > ram
    319     dr_len = _dr_end - _dr_start;
    320 
    321 
    322     .line 0 : { *(.line) }
    323     .debug 0 : { *(.debug) }
    324     .debug_sfnames 0 : { *(.debug_sfnames) }
    325     .debug_srcinfo 0 : { *(.debug_srcinfo) }
    326     .debug_pubnames 0 : { *(.debug_pubnames) }
    327     .debug_aranges 0 : { *(.debug_aranges) }
    328     .debug_aregion 0 : { *(.debug_aregion) }
    329     .debug_macinfo 0 : { *(.debug_macinfo) }
    330     .stab 0 : { *(.stab) }
    331     .stabstr 0 : { *(.stabstr) }
    332 }
     14INCLUDE linkcmds.base
  • c/src/lib/libbsp/powerpc/haleakala/ChangeLog

    r3c6fe2e r574fb67  
     12008-07-14      Thomas Doerfler <thomas.doerfler@embedded-brains.de>
     2
     3        * irq/irq.c: adapted DCR access syntax
     4       
     5        * startup/linkcmds, startup/bspstartup.c, Makefile.am:
     6        adapted to exception support code
     7
    182008-07-14      Thomas Doerfler <thomas.doerfler@embedded-brains.de>
    29
  • c/src/lib/libbsp/powerpc/haleakala/Makefile.am

    r3c6fe2e r574fb67  
    5757        ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h \
    5858        ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h
    59        
     59
    6060noinst_PROGRAMS += irq.rel
    6161irq_rel_SOURCES = irq/irq_init.c irq/irq.c
     
    6464
    6565
    66 if HAS_NETWORKING
    67 network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__
    68 noinst_PROGRAMS += network.rel
    69 network_rel_SOURCES = network/network.c
    70 network_rel_CPPFLAGS = $(AM_CPPFLAGS) $(network_CPPFLAGS)
    71 network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
    72 endif
     66## if HAS_NETWORKING
     67## network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__
     68## noinst_PROGRAMS += network.rel
     69## network_rel_SOURCES = network/network.c
     70## network_rel_CPPFLAGS = $(AM_CPPFLAGS) $(network_CPPFLAGS)
     71## network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
     72## endif
    7373
    7474
     
    7878libbsp_a_LIBADD = startup.rel dlentry.rel console.rel irq.rel
    7979
    80 if HAS_NETWORKING
    81 libbsp_a_LIBADD += network.rel
    82 endif
     80## if HAS_NETWORKING
     81## libbsp_a_LIBADD += network.rel
     82## endif
    8383
    8484libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
    85     ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
    86         ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
     85        ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
     86        ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
    8787        ../../../libcpu/@RTEMS_CPU@/@exceptions@/irq_bspsupport.rel \
    88     ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
     88        ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
    8989        ../../../libcpu/@RTEMS_CPU@/ppc403/clock.rel \
    90     ../../../libcpu/@RTEMS_CPU@/ppc403/timer.rel
     90        ../../../libcpu/@RTEMS_CPU@/ppc403/timer.rel
    9191
    9292
  • c/src/lib/libbsp/powerpc/haleakala/irq/irq.c

    r3c6fe2e r574fb67  
    7070/* Write the gEnabledInts state masked by gIntInhibited to the hardware */
    7171{
    72         mtdcr(UIC0_ER, gEnabledInts[0] & ~gIntInhibited[0]);
    73         mtdcr(UIC1_ER, gEnabledInts[1] & ~gIntInhibited[1]);
    74         mtdcr(UIC2_ER, gEnabledInts[2] & ~gIntInhibited[2]);
     72        PPC_SET_DEVICE_CONTROL_REGISTER(UIC0_ER,
     73                                        gEnabledInts[0] & ~gIntInhibited[0]);
     74        PPC_SET_DEVICE_CONTROL_REGISTER(UIC1_ER,
     75                                        gEnabledInts[1] & ~gIntInhibited[1]);
     76        PPC_SET_DEVICE_CONTROL_REGISTER(UIC2_ER,
     77                                        gEnabledInts[2] & ~gIntInhibited[2]);
    7578}
    7679
     
    113116                gIntInhibited[i] = 0;
    114117               
    115         mtdcr (UIC2_ER, 0x00000000);    /* disable all interrupts */
    116         mtdcr (UIC2_CR, 0x00000000);    /* Set Critical / Non Critical interrupts */
    117         mtdcr (UIC2_PR, 0xf7ffffff);    /* Set Interrupt Polarities */
    118         mtdcr (UIC2_TR, 0x01e1fff8);    /* Set Interrupt Trigger Levels */
    119         mtdcr (UIC2_VR, 0x00000001);    /* Set Vect base=0,INT31 Highest priority */
    120         mtdcr (UIC2_SR, 0xffffffff);    /* clear all interrupts */
    121 
    122         mtdcr (UIC1_ER, 0x00000000);    /* disable all interrupts */
    123         mtdcr (UIC1_CR, 0x00000000);    /* Set Critical / Non Critical interrupts */
    124         mtdcr (UIC1_PR, 0xfffac785);    /* Set Interrupt Polarities */
    125         mtdcr (UIC1_TR, 0x001d0040);    /* Set Interrupt Trigger Levels */
    126         mtdcr (UIC1_VR, 0x00000001);    /* Set Vect base=0,INT31 Highest priority */
    127         mtdcr (UIC1_SR, 0xffffffff);    /* clear all interrupts */
    128 
    129         mtdcr (UIC0_ER, 0x0000000a);    /* Disable all interrupts except cascade UIC0 and UIC1 */
    130         mtdcr (UIC0_CR, 0x00000000);    /* Set Critical / Non Critical interrupts */
    131         mtdcr (UIC0_PR, 0xffbfefef);    /* Set Interrupt Polarities */
    132         mtdcr (UIC0_TR, 0x00007000);    /* Set Interrupt Trigger Levels */
    133         mtdcr (UIC0_VR, 0x00000001);    /* Set Vect base=0,INT31 Highest priority */
    134         mtdcr (UIC0_SR, 0xffffffff);    /* clear all interrupts */
     118        /* disable all interrupts */
     119        PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_ER, 0x00000000); 
     120        /* Set Critical / Non Critical interrupts */
     121        PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_CR, 0x00000000);
     122        /* Set Interrupt Polarities */
     123        PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_PR, 0xf7ffffff);
     124        /* Set Interrupt Trigger Levels */
     125        PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_TR, 0x01e1fff8);
     126        /* Set Vect base=0,INT31 Highest priority */
     127        PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_VR, 0x00000001);
     128        /* clear all interrupts */
     129        PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_SR, 0xffffffff);
     130
     131        /* disable all interrupts */
     132        PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_ER, 0x00000000);
     133        /* Set Critical / Non Critical interrupts */
     134        PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_CR, 0x00000000);
     135        /* Set Interrupt Polarities */
     136        PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_PR, 0xfffac785);
     137        /* Set Interrupt Trigger Levels */
     138        PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_TR, 0x001d0040);
     139        /* Set Vect base=0,INT31 Highest priority */
     140        PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_VR, 0x00000001);
     141        /* clear all interrupts */
     142        PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_SR, 0xffffffff);
     143
     144        /* Disable all interrupts except cascade UIC0 and UIC1 */
     145        PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_ER, 0x0000000a);
     146        /* Set Critical / Non Critical interrupts */
     147        PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_CR, 0x00000000);
     148        /* Set Interrupt Polarities */
     149        PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_PR, 0xffbfefef);
     150        /* Set Interrupt Trigger Levels */
     151        PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_TR, 0x00007000);
     152        /* Set Vect base=0,INT31 Highest priority */
     153        PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_VR, 0x00000001);
     154        /* clear all interrupts */
     155        PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_SR, 0xffffffff);
    135156       
    136157        return 1;
     
    154175                   Likely to be only one, but we need to handle more than one,
    155176                   OR the flags into gIntInhibited */
    156                 active[0] = mfdcr(UIC0_MSR);
    157                 active[1] = mfdcr(UIC1_MSR);
    158                 active[2] = mfdcr(UIC2_MSR);
     177                active[0] = PPC_DEVICE_CONTROL_REGISTER(UIC0_MSR);
     178                active[1] = PPC_DEVICE_CONTROL_REGISTER(UIC1_MSR);
     179                active[2] = PPC_DEVICE_CONTROL_REGISTER(UIC2_MSR);
    159180                gIntInhibited[0] |= active[0];
    160181                gIntInhibited[1] |= active[1];
     
    181202                        bmask = 0x80000000 >> bit;
    182203                        switch (index) {
    183                                 case 0: mtdcr(UIC0_SR, bmask); break;
    184                                 case 1: mtdcr(UIC1_SR, bmask); break;
    185                                 case 2: mtdcr(UIC2_SR, bmask); break;
     204                        case 0:
     205                          PPC_SET_DEVICE_CONTROL_REGISTER(UIC0_SR, bmask);
     206                          break;
     207                        case 1:
     208                          PPC_SET_DEVICE_CONTROL_REGISTER(UIC1_SR, bmask);
     209                          break;
     210                        case 2:
     211                          PPC_SET_DEVICE_CONTROL_REGISTER(UIC2_SR, bmask);
     212                          break;
    186213                        }
    187214                       
  • c/src/lib/libbsp/powerpc/haleakala/startup/bspstart.c

    r3c6fe2e r574fb67  
    6969#include <rtems/bspIo.h>
    7070#include <libcpu/cpuIdent.h>
    71 #include <libcpu/spr.h>
    7271#include <rtems/powerpc/powerpc.h>
     72#include <bsp/ppc_exc_bspsupp.h>
    7373#include <ppc4xx/ppc405gp.h>
    7474#include <ppc4xx/ppc405ex.h>
    75 
    76 SPR_RW(SPRG0)
    77 SPR_RW(SPRG1)
    7875
    7976#include <stdio.h>
     
    233230void bsp_start( void )
    234231{
    235         extern unsigned long *intrStackPtr;
    236         register unsigned char* intrStack;
     232        LINKER_SYMBOL(intrStack_start);
     233        LINKER_SYMBOL(intrStack_size);
    237234        ppc_cpu_id_t myCpu;
    238235        ppc_cpu_revision_t myCpuRevision;
     
    263260       
    264261        /*
    265         * Initialize some SPRG registers related to irq handling
    266         */
    267 
    268         intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE);
    269         _write_SPRG1((unsigned int)intrStack);
    270         /* signal them that we have fixed PR288 - eventually, this should go away */
    271         /*
    272262        * Initialize default raw exception handlers.
    273263        */
    274         initialize_exceptions();
     264        ppc_exc_initialize(
     265                PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
     266                           (uint32_t) intrStack_start,
     267                           (uint32_t) intrStack_size);
    275268
    276269        /*
  • c/src/lib/libbsp/powerpc/haleakala/startup/linkcmds

    r3c6fe2e r574fb67  
    230230    intrStack = .;
    231231    PROVIDE(intrStackPtr = intrStack);
     232    PROVIDE(intrStack_start = IntrStack_start);
     233    PROVIDE(intrStack_size = kIntrStackSize);
    232234
    233235        /* Main stack: align to a cache-line boundary */
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