Changeset 56fc780 in rtems


Ignore:
Timestamp:
Jul 3, 2013, 8:16:30 AM (6 years ago)
Author:
Andreas Larsson <andreas@…>
Branches:
4.11, master
Children:
d2a94ab
Parents:
c119c0e
git-author:
Andreas Larsson <andreas@…> (07/03/13 08:16:30)
git-committer:
Daniel Hellstrom <daniel@…> (04/16/15 23:10:21)
Message:

GRSPW_PKT: Add support for Interrupt-codes

Update: Daniel Hellstrom updated SpW-IRQ implementation accoring to

changes in hardware register layout and features.

Location:
c/src/lib/libbsp/sparc/shared
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sparc/shared/include/grspw_pkt.h

    rc119c0e r56fc780  
    174174        int     hw_version;     /* GRSPW Hardware Version */
    175175        char    reserved[2];
     176        char    irq;            /* SpW Distributed Interrupt available if 1 */
     177        char    irq_num;        /* Number of interrupts that can be generated */
     178        char    itmr_width;     /* SpW Intr. ISR timers bit width. 0=no timer */
    176179};
    177180
     
    201204#define TCOPTS_EN_RX    0x0008
    202205
     206/* grspw_ic_ctrl() options:
     207 * Corresponds code duplicatingly to GRSPW_CTRL_XX_BIT defines
     208 */
     209#define ICOPTS_INTNUM           (0x1f << 27)
     210#define ICOPTS_EN_SPWIRQ_ON_EE  (1 << 24)
     211#define ICOPTS_EN_SPWIRQ_ON_IA  (1 << 23)
     212#define ICOPTS_EN_PRIO          (1 << 22)
     213#define ICOPTS_EN_TIMEOUTIRQ    (1 << 20)
     214#define ICOPTS_EN_ACKIRQ        (1 << 19)
     215#define ICOPTS_EN_TICKOUTIRQ    (1 << 18)
     216#define ICOPTS_EN_RX            (1 << 17)
     217#define ICOPTS_EN_TX            (1 << 16)
     218#define ICOPTS_BASEIRQ          (0x1f << 8)
     219#define ICOPTS_EN_FLAGFILTER    (1 << 0) /* NOTE: Not in icctrl. CTRL.bit12 */
     220
     221/* grspw_ic_rlisr() and grspw_ic_rlintack()  */
     222#define ICRELOAD_EN             (1 << 31)
     223#define ICRELOAD_MASK           0x7fffffff
     224
    203225/* grspw_rmap_ctrl() options */
    204226#define RMAPOPTS_EN_RMAP        0x0001
    205227#define RMAPOPTS_EN_BUF         0x0002
    206 
    207228
    208229/* grspw_dma_config.flags options */
     
    303324extern void grspw_tc_time(void *d, int *time);
    304325
     326/*** Interrupt-code Interface ***/
     327struct spwpkt_ic_config {
     328        unsigned int tomask;
     329        unsigned int aamask;
     330        unsigned int scaler;
     331        unsigned int isr_reload;
     332        unsigned int ack_reload;
     333};
     334/* Function Interrupt-Code ISR callback prototype. Called when respective
     335 * interrupt handling option has been enabled by grspw_ic_ctrl(), the
     336 * arguments rxirq, rxack and intto are read from the registers of the
     337 * GRSPW core read by the GRSPW ISR, they are individually valid only when
     338 * repective handling been turned on.
     339 *
     340 * data    - Custom data provided by user
     341 * rxirq   - Interrupt-Code Recevie register of the GRSPW core read by ISR
     342 *           (only defined if IQ bit enabled through grspw_ic_ctrl())
     343 * rxack   - Interrupt-Ack-Code Recevie register of the GRSPW core read by ISR
     344 *           (only defined if AQ bit enabled through grspw_ic_ctrl())
     345 * intto   - Interrupt Tick-out Recevie register of the GRSPW core read by ISR
     346 *           (only defined if TQ bit enabled through grspw_ic_ctrl())
     347 */
     348typedef void (*spwpkt_ic_isr_t)(void *data, unsigned int rxirq,
     349                                unsigned int rxack, unsigned int intto);
     350/* Control Interrupt-code settings of core
     351 * Write if 'options' not pointing to -1, always read current value
     352 */
     353extern void grspw_ic_ctrl(void *d, unsigned int *options);
     354/* Write (rw&1 == 1) configuration parameters to registers and/or,
     355 * Read  (rw&2 == 1) configuration parameters from registers, in that sequence.
     356 */
     357extern void grspw_ic_config(void *d, int rw, struct spwpkt_ic_config *cfg);
     358/* Read or Write Interrupt-code status registers.
     359 * If pointer argument *ptr == 0 then only read, if *ptr != 0 then only write.
     360 * If *ptr is NULL no operation.
     361 */
     362extern void grspw_ic_sts(void *d, unsigned int *rxirq, unsigned int *rxack,
     363                        unsigned int *intto);
     364/* Generate Tick-In for the given Interrupt-code
     365 * Returns zero on success and non-zero on failure
     366 *
     367 * Interrupt code bits (ic):
     368 * Bit 5 - ACK if 1
     369 * Bits 4-0 Interrupt-code number
     370 */
     371extern int grspw_ic_tickin(void *d, int ic);
     372/* Assign handler function to Interrupt-code timeout IRQ */
     373extern void grspw_ic_isr(void *d, spwpkt_ic_isr_t handler, void *data);
     374
    305375/*** RMAP Control Interface ***/
    306376/* Set (not -1) and/or read RMAP options. */
  • c/src/lib/libbsp/sparc/shared/spw/grspw_pkt.c

    rc119c0e r56fc780  
    8888         */
    8989        struct grspw_dma_regs dma[4];
     90
     91        volatile unsigned int icctrl;
     92        volatile unsigned int icrx;
     93        volatile unsigned int icack;
     94        volatile unsigned int ictimeout;
     95        volatile unsigned int ictickomask;
     96        volatile unsigned int icaamask;
     97        volatile unsigned int icrlpresc;
     98        volatile unsigned int icrlisr;
     99        volatile unsigned int icrlintack;
     100        volatile unsigned int resv2;
     101        volatile unsigned int icisr;
     102        volatile unsigned int resv3;
    90103};
    91104
     
    96109#define GRSPW_CTRL_NCH_BIT      27
    97110#define GRSPW_CTRL_PO_BIT       26
     111#define GRSPW_CTRL_ID_BIT       24
     112#define GRSPW_CTRL_LE_BIT       22
    98113#define GRSPW_CTRL_PS_BIT       21
    99114#define GRSPW_CTRL_NP_BIT       20
    100115#define GRSPW_CTRL_RD_BIT       17
    101116#define GRSPW_CTRL_RE_BIT       16
     117#define GRSPW_CTRL_TF_BIT       12
    102118#define GRSPW_CTRL_TR_BIT       11
    103119#define GRSPW_CTRL_TT_BIT       10
     
    117133#define GRSPW_CTRL_NCH  (0x3<<GRSPW_CTRL_NCH_BIT)
    118134#define GRSPW_CTRL_PO   (1<<GRSPW_CTRL_PO_BIT)
     135#define GRSPW_CTRL_ID   (1<<GRSPW_CTRL_ID_BIT)
     136#define GRSPW_CTRL_LE   (1<<GRSPW_CTRL_LE_BIT)
    119137#define GRSPW_CTRL_PS   (1<<GRSPW_CTRL_PS_BIT)
    120138#define GRSPW_CTRL_NP   (1<<GRSPW_CTRL_NP_BIT)
    121139#define GRSPW_CTRL_RD   (1<<GRSPW_CTRL_RD_BIT)
    122140#define GRSPW_CTRL_RE   (1<<GRSPW_CTRL_RE_BIT)
     141#define GRSPW_CTRL_TF   (1<<GRSPW_CTRL_TF_BIT)
    123142#define GRSPW_CTRL_TR   (1<<GRSPW_CTRL_TR_BIT)
    124143#define GRSPW_CTRL_TT   (1<<GRSPW_CTRL_TT_BIT)
     
    133152#define GRSPW_CTRL_LD   (1<<GRSPW_CTRL_LD_BIT)
    134153
     154#define GRSPW_CTRL_IRQSRC_MASK \
     155        (GRSPW_CTRL_LI | GRSPW_CTRL_TQ)
     156#define GRSPW_ICCTRL_IRQSRC_MASK \
     157        (GRSPW_ICCTRL_TQ | GRSPW_ICCTRL_AQ | GRSPW_ICCTRL_IQ)
     158
     159
    135160/* GRSPW - Status Register - 0x04 */
    136161#define GRSPW_STS_LS_BIT        21
     
    138163#define GRSPW_STS_EE_BIT        8
    139164#define GRSPW_STS_IA_BIT        7
    140 #define GRSPW_STS_WE_BIT        6
     165#define GRSPW_STS_WE_BIT        6       /* GRSPW1 */
    141166#define GRSPW_STS_PE_BIT        4
    142167#define GRSPW_STS_DE_BIT        3
     
    149174#define GRSPW_STS_EE    (1<<GRSPW_STS_EE_BIT)
    150175#define GRSPW_STS_IA    (1<<GRSPW_STS_IA_BIT)
    151 #define GRSPW_STS_WE    (1<<GRSPW_STS_WE_BIT)
     176#define GRSPW_STS_WE    (1<<GRSPW_STS_WE_BIT)   /* GRSPW1 */
    152177#define GRSPW_STS_PE    (1<<GRSPW_STS_PE_BIT)
    153178#define GRSPW_STS_DE    (1<<GRSPW_STS_DE_BIT)
     
    226251#define GRSPW_DMAADR_MASK       (0xff<<GRSPW_DMAADR_MASK_BIT)
    227252
     253/* GRSPW - Interrupt code receive register - 0xa4 */
     254#define GRSPW_ICCTRL_INUM_BIT   27
     255#define GRSPW_ICCTRL_IA_BIT     24
     256#define GRSPW_ICCTRL_LE_BIT     23
     257#define GRSPW_ICCTRL_PR_BIT     22
     258#define GRSPW_ICCTRL_DQ_BIT     21 /* never used */
     259#define GRSPW_ICCTRL_TQ_BIT     20
     260#define GRSPW_ICCTRL_AQ_BIT     19
     261#define GRSPW_ICCTRL_IQ_BIT     18
     262#define GRSPW_ICCTRL_IR_BIT     17
     263#define GRSPW_ICCTRL_IT_BIT     16
     264#define GRSPW_ICCTRL_NUMI_BIT   13
     265#define GRSPW_ICCTRL_BIRQ_BIT   8
     266#define GRSPW_ICCTRL_ID_BIT     7
     267#define GRSPW_ICCTRL_II_BIT     6
     268#define GRSPW_ICCTRL_TXIRQ_BIT  0
     269#define GRSPW_ICCTRL_INUM       (0x3f << GRSPW_ICCTRL_INUM_BIT)
     270#define GRSPW_ICCTRL_IA         (1 << GRSPW_ICCTRL_IA_BIT)
     271#define GRSPW_ICCTRL_LE         (1 << GRSPW_ICCTRL_LE_BIT)
     272#define GRSPW_ICCTRL_PR         (1 << GRSPW_ICCTRL_PR_BIT)
     273#define GRSPW_ICCTRL_DQ         (1 << GRSPW_ICCTRL_DQ_BIT)
     274#define GRSPW_ICCTRL_TQ         (1 << GRSPW_ICCTRL_TQ_BIT)
     275#define GRSPW_ICCTRL_AQ         (1 << GRSPW_ICCTRL_AQ_BIT)
     276#define GRSPW_ICCTRL_IQ         (1 << GRSPW_ICCTRL_IQ_BIT)
     277#define GRSPW_ICCTRL_IR         (1 << GRSPW_ICCTRL_IR_BIT)
     278#define GRSPW_ICCTRL_IT         (1 << GRSPW_ICCTRL_IT_BIT)
     279#define GRSPW_ICCTRL_NUMI       (0x7 << GRSPW_ICCTRL_NUMI_BIT)
     280#define GRSPW_ICCTRL_BIRQ       (0x1f << GRSPW_ICCTRL_BIRQ_BIT)
     281#define GRSPW_ICCTRL_ID         (1 << GRSPW_ICCTRL_ID_BIT)
     282#define GRSPW_ICCTRL_II         (1 << GRSPW_ICCTRL_II_BIT)
     283#define GRSPW_ICCTRL_TXIRQ      (0x3f << GRSPW_ICCTRL_TXIRQ_BIT)
     284
    228285/* RX Buffer Descriptor */
    229286struct grspw_rxbd {
     
    409466        void *tcisr_arg;
    410467
     468        /*** Interrupt-code Handling ***/
     469        spwpkt_ic_isr_t icisr;
     470        void *icisr_arg;
     471
    411472        /* Disable Link on SpW Link error */
    412473        int dis_link_on_err;
     
    476537        priv->tcisr = NULL;
    477538        priv->tcisr_arg = NULL;
     539        priv->icisr = NULL;
     540        priv->icisr_arg = NULL;
    478541
    479542        grspw_stats_clr(priv);
     
    665728}
    666729
     730/* Enable Global IRQ only if some irq source is set */
     731static inline int grspw_is_irqsource_set(unsigned int ctrl, unsigned int icctrl)
     732{
     733        return (ctrl & GRSPW_CTRL_IRQSRC_MASK) ||
     734                (icctrl & GRSPW_ICCTRL_IRQSRC_MASK);
     735}
     736
     737
    667738/* options and clkdiv [in/out]: set to -1 to only read current config */
    668739void grspw_link_ctrl(void *d, int *options, int *clkdiv)
     
    686757                                (*options & GRSPW_LINK_CFG);
    687758
    688                         /* Enable Global IRQ only of LI or TQ is set */
    689                         if (ctrl & (GRSPW_CTRL_LI|GRSPW_CTRL_TQ))
     759                        /* Enable Global IRQ only if some irq source is set */
     760                        if (grspw_is_irqsource_set(ctrl, REG_READ(&regs->icctrl)))
    690761                                ctrl |= GRSPW_CTRL_IE;
    691762                        else
     
    729800                ctrl |= (*options & 0xd) << GRSPW_CTRL_TQ_BIT;
    730801
    731                 /* Enable Global IRQ only of LI or TQ is set */
    732                 if (ctrl & (GRSPW_CTRL_LI|GRSPW_CTRL_TQ))
     802                /* Enable Global IRQ only if some irq source is set */
     803                if (grspw_is_irqsource_set(ctrl, REG_READ(&regs->icctrl)))
    733804                        ctrl |= GRSPW_CTRL_IE;
    734                 else 
     805                else
    735806                        ctrl &= ~GRSPW_CTRL_IE;
    736807
     
    757828void grspw_tc_time(void *d, int *time)
    758829{
     830        struct grspw_priv *priv = d;
     831        struct grspw_regs *regs = priv->regs;
     832
     833        if (time == NULL)
     834                return;
     835        if (*time != -1)
     836                REG_WRITE(&regs->time, *time & (GRSPW_TIME_TCNT | GRSPW_TIME_CTRL));
     837        *time = REG_READ(&regs->time) & (GRSPW_TIME_TCNT | GRSPW_TIME_CTRL);
     838}
     839
     840/* Generate Tick-In for the given Interrupt-code and check for generation
     841 * error.
     842 *
     843 * Returns zero on success and non-zero on failure
     844 */
     845int grspw_ic_tickin(void *d, int ic)
     846{
    759847        struct grspw_priv *priv = d;
    760848        struct grspw_regs *regs = priv->regs;
    761 
    762         if (time == NULL)
     849        IRQFLAGS_TYPE irqflags;
     850        unsigned int icctrl, mask;
     851
     852        /* Prepare before turning off IRQ */
     853        mask = 0x3f << GRSPW_ICCTRL_TXIRQ_BIT;
     854        ic = ((ic << GRSPW_ICCTRL_TXIRQ_BIT) & mask) |
     855             GRSPW_ICCTRL_II | GRSPW_ICCTRL_ID;
     856
     857        SPIN_LOCK_IRQ(&priv->devlock, irqflags);
     858        icctrl = REG_READ(&regs->icctrl);
     859        icctrl &= ~mask;
     860        icctrl |= ic;
     861        REG_WRITE(&regs->icctrl, icctrl); /* Generate SpW Interrupt Tick-In */
     862        /* the ID bit is valid after two clocks, so we not to wait here */
     863        icctrl = REG_READ(&regs->icctrl); /* Check SpW-Int generation error */
     864        SPIN_UNLOCK_IRQ(&priv->devlock, irqflags);
     865
     866        return icctrl & GRSPW_ICCTRL_ID;
     867}
     868
     869#define ICOPTS_CTRL_MASK ICOPTS_EN_FLAGFILTER
     870#define ICOPTS_ICCTRL_MASK                                              \
     871        (ICOPTS_INTNUM | ICOPTS_EN_SPWIRQ_ON_EE  | ICOPTS_EN_SPWIRQ_ON_IA | \
     872         ICOPTS_EN_PRIO | ICOPTS_EN_TIMEOUTIRQ | ICOPTS_EN_ACKIRQ | \
     873         ICOPTS_EN_TICKOUTIRQ | ICOPTS_EN_RX | ICOPTS_EN_TX | \
     874         ICOPTS_BASEIRQ)
     875
     876/* Control Interrupt-code settings of core
     877 * Write if not pointing to -1, always read current value
     878 *
     879 * TODO: A lot of code duplication with grspw_tc_ctrl
     880 */
     881void grspw_ic_ctrl(void *d, unsigned int *options)
     882{
     883        struct grspw_priv *priv = d;
     884        struct grspw_regs *regs = priv->regs;
     885        unsigned int ctrl;
     886        unsigned int icctrl;
     887        IRQFLAGS_TYPE irqflags;
     888
     889        if (options == NULL)
    763890                return;
    764         if (*time != -1)
    765                 REG_WRITE(&regs->time, *time & (GRSPW_TIME_TCNT | GRSPW_TIME_CTRL));
    766         *time = REG_READ(&regs->time) & (GRSPW_TIME_TCNT | GRSPW_TIME_CTRL);
     891
     892        if (*options != -1) {
     893                SPIN_LOCK_IRQ(&priv->devlock, irqflags);
     894
     895                ctrl = REG_READ(&regs->ctrl);
     896                ctrl &= ~GRSPW_CTRL_TF; /* Depends on one to one relation between
     897                                         * irqopts bits and ctrl bits */
     898                ctrl |= (*options & ICOPTS_CTRL_MASK) <<
     899                        (GRSPW_CTRL_TF_BIT - 0);
     900
     901                icctrl = REG_READ(&regs->icctrl);
     902                icctrl &= ~ICOPTS_ICCTRL_MASK; /* Depends on one to one relation between
     903                                                * irqopts bits and icctrl bits */
     904                icctrl |= *options & ICOPTS_ICCTRL_MASK;
     905
     906                /* Enable Global IRQ only if some irq source is set */
     907                if (grspw_is_irqsource_set(ctrl, icctrl))
     908                        ctrl |= GRSPW_CTRL_IE;
     909                else
     910                        ctrl &= ~GRSPW_CTRL_IE;
     911
     912                REG_WRITE(&regs->ctrl, ctrl);
     913                REG_WRITE(&regs->icctrl, icctrl);
     914                SPIN_UNLOCK_IRQ(&priv->devlock, irqflags);
     915        }
     916        *options = ((REG_READ(&regs->ctrl) & ICOPTS_CTRL_MASK) |
     917                    (REG_READ(&regs->icctrl) & ICOPTS_ICCTRL_MASK));
     918}
     919
     920void grspw_ic_config(void *d, int rw, struct spwpkt_ic_config *cfg)
     921{
     922        struct grspw_priv *priv = d;
     923        struct grspw_regs *regs = priv->regs;
     924
     925        if (!cfg)
     926                return;
     927
     928        if (rw & 1) {
     929                REG_WRITE(&regs->ictickomask, cfg->tomask);
     930                REG_WRITE(&regs->icaamask, cfg->aamask);
     931                REG_WRITE(&regs->icrlpresc, cfg->scaler);
     932                REG_WRITE(&regs->icrlisr, cfg->isr_reload);
     933                REG_WRITE(&regs->icrlintack, cfg->ack_reload);
     934        }
     935        if (rw & 2) {
     936                cfg->tomask = REG_READ(&regs->ictickomask);
     937                cfg->aamask = REG_READ(&regs->icaamask);
     938                cfg->scaler = REG_READ(&regs->icrlpresc);
     939                cfg->isr_reload = REG_READ(&regs->icrlisr);
     940                cfg->ack_reload = REG_READ(&regs->icrlintack);
     941        }
     942}
     943
     944/* Read or Write Interrupt-code status registers */
     945void grspw_ic_sts(void *d, unsigned int *rxirq, unsigned int *rxack, unsigned int *intto)
     946{
     947        struct grspw_priv *priv = d;
     948        struct grspw_regs *regs = priv->regs;
     949
     950        /* No locking needed since the status bits are clear-on-write */
     951
     952        if (rxirq) {
     953                if (*rxirq != 0)
     954                        REG_WRITE(&regs->icrx, *rxirq);
     955                else
     956                        *rxirq = REG_READ(&regs->icrx);
     957        }
     958
     959        if (rxack) {
     960                if (*rxack != 0)
     961                        REG_WRITE(&regs->icack, *rxack);
     962                else
     963                        *rxack = REG_READ(&regs->icack);
     964        }
     965
     966        if (intto) {
     967                if (*intto != 0)
     968                        REG_WRITE(&regs->ictimeout, *intto);
     969                else
     970                        *intto = REG_READ(&regs->ictimeout);
     971        }
     972}
     973
     974/* Assign handler function to Interrupt-code tick out IRQ */
     975void grspw_ic_isr(void *d, spwpkt_ic_isr_t handler, void *data)
     976{
     977        struct grspw_priv *priv = d;
     978
     979        priv->icisr_arg = data;
     980        priv->icisr = handler;
    767981}
    768982
     
    22542468{
    22552469        struct grspw_priv *priv = data;
    2256         unsigned int dma_stat, stat, stat_clrmsk, ctrl, timecode;
    2257         int i, handled = 0, message = WORK_NONE;
     2470        unsigned int dma_stat, stat, stat_clrmsk, ctrl, icctrl, timecode;
     2471        unsigned int rxirq, rxack, intto;
     2472        int i, handled = 0, message = WORK_NONE, call_user_int_isr;
    22582473#ifdef RTEMS_HAS_SMP
    22592474        IRQFLAGS_TYPE irqflags;
     
    22682483         */
    22692484        if ((stat & GRSPW_STS_TO) && (priv->tcisr != NULL)) {
    2270                 /* Timecode received. Let custom function handle this */
    2271                 timecode = priv->regs->time;
    2272                 (priv->tcisr)(priv->tcisr_arg, timecode);
     2485                ctrl = REG_READ(&priv->regs->ctrl);
     2486                if (ctrl & GRSPW_CTRL_TQ) {
     2487                        /* Timecode received. Let custom function handle this */
     2488                        timecode = REG_READ(&priv->regs->time) &
     2489                                        (GRSPW_TIME_CTRL | GRSPW_TIME_TCNT);
     2490                        (priv->tcisr)(priv->tcisr_arg, timecode);
     2491                }
     2492        }
     2493
     2494        /* Get Interrupt status from hardware */
     2495        icctrl = REG_READ(&priv->regs->icctrl);
     2496        if ((icctrl & GRSPW_ICCTRL_IRQSRC_MASK) && (priv->icisr != NULL)) {
     2497                call_user_int_isr = 0;
     2498                rxirq = rxack = intto = 0;
     2499
     2500                if ((icctrl & GRSPW_ICCTRL_IQ) &&
     2501                    (rxirq = REG_READ(&priv->regs->icrx)) != 0)
     2502                        call_user_int_isr = 1;
     2503
     2504                if ((icctrl & GRSPW_ICCTRL_AQ) &&
     2505                    (rxack = REG_READ(&priv->regs->icack)) != 0)
     2506                        call_user_int_isr = 1;
     2507
     2508                if ((icctrl & GRSPW_ICCTRL_TQ) &&
     2509                    (intto = REG_READ(&priv->regs->ictimeout)) != 0)
     2510                        call_user_int_isr = 1;                 
     2511
     2512                /* Let custom functions handle this POTENTIAL SPW interrupt. The
     2513                 * user function is called even if no such IRQ has happened!
     2514                 * User must make sure to clear all interrupts that have been
     2515                 * handled from the three registers by writing a one.
     2516                 */
     2517                if (call_user_int_isr)
     2518                        priv->icisr(priv->icisr_arg, rxirq, rxack, intto);
    22732519        }
    22742520
     
    24222668{
    24232669        int i;
     2670        unsigned int tmp;
    24242671
    24252672        for (i=0; i<priv->hwsup.ndma_chans; i++)
     
    24282675        REG_WRITE(&priv->regs->status, 0xffffffff);
    24292676        REG_WRITE(&priv->regs->time, 0);
     2677        /* Clear all but valuable reset values of ICCTRL */
     2678        tmp = REG_READ(&priv->regs->icctrl);
     2679        tmp &= GRSPW_ICCTRL_INUM | GRSPW_ICCTRL_BIRQ | GRSPW_ICCTRL_TXIRQ;
     2680        tmp |= GRSPW_ICCTRL_ID;
     2681        REG_WRITE(&priv->regs->icctrl, tmp);
     2682        REG_WRITE(&priv->regs->icrx, 0xffffffff);
     2683        REG_WRITE(&priv->regs->icack, 0xffffffff);
     2684        REG_WRITE(&priv->regs->ictimeout, 0xffffffff);
    24302685}
    24312686
     
    25042759        struct ambapp_core *pnpinfo;
    25052760        int i, size;
    2506         unsigned int ctrl;
     2761        unsigned int ctrl, icctrl, numi;
    25072762        union drvmgr_key_value *value;
    25082763
     
    25392794        priv->hwsup.nports = 1 + ((ctrl & GRSPW_CTRL_PO) >> GRSPW_CTRL_PO_BIT);
    25402795        priv->hwsup.ndma_chans = 1 + ((ctrl & GRSPW_CTRL_NCH) >> GRSPW_CTRL_NCH_BIT);
     2796        priv->hwsup.irq = ((ctrl & GRSPW_CTRL_ID) >> GRSPW_CTRL_ID_BIT);
     2797        icctrl = REG_READ(&priv->regs->icctrl);
     2798        numi = (icctrl & GRSPW_ICCTRL_NUMI) >> GRSPW_ICCTRL_NUMI_BIT;
     2799        if (numi > 0)
     2800                priv->hwsup.irq_num = 1 << (numi - 1);
     2801        else
     2802                priv->hwsup.irq_num = 0;
    25412803
    25422804        /* Construct hardware version identification */
     
    25512813                priv->hwsup.strip_adr = 0;
    25522814                priv->hwsup.strip_pid = 0;
     2815        }
     2816
     2817        /* Probe width of SpaceWire Interrupt ISR timers. All have the same
     2818         * width... so only the first is probed, if no timer result will be
     2819         * zero.
     2820         */
     2821        REG_WRITE(&priv->regs->icrlpresc, 0x7fffffff);
     2822        ctrl = REG_READ(&priv->regs->icrlpresc);
     2823        REG_WRITE(&priv->regs->icrlpresc, 0);
     2824        priv->hwsup.itmr_width = 0;
     2825        while (ctrl & 1) {
     2826                priv->hwsup.itmr_width++;
     2827                ctrl = ctrl >> 1;
    25532828        }
    25542829
Note: See TracChangeset for help on using the changeset viewer.