Changeset 5686b44d in rtems


Ignore:
Timestamp:
Dec 2, 2020, 7:20:36 PM (3 months ago)
Author:
Kinsey Moore <kinsey.moore@…>
Branches:
master
Children:
a92d4ae
Parents:
2b56f5a
git-author:
Kinsey Moore <kinsey.moore@…> (12/02/20 19:20:36)
git-committer:
Joel Sherrill <joel@…> (12/03/20 23:35:28)
Message:

zynq-uart: Fix set_attributes implementation

The zynq-uart set_attributes implementation was configured to always
return false which causes spconsole01 to fail. This restores the
disabled implementation which sets the baud rate registers
appropriately and allows spconsole01 to pass. This also expands the
set_attributes functionality to allow setting of the stop bits,
character width, and parity.

Location:
bsps
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • bsps/include/dev/serial/zynq-uart.h

    r2b56f5a r5686b44d  
    7979void zynq_uart_reset_tx_flush(zynq_uart_context *ctx);
    8080
     81int zynq_cal_baud_rate(
     82  uint32_t  baudrate,
     83  uint32_t* brgr,
     84  uint32_t* bauddiv,
     85  uint32_t  modereg
     86);
     87
    8188#ifdef __cplusplus
    8289}
  • bsps/shared/dev/serial/zynq-uart-polled.c

    r2b56f5a r5686b44d  
    4141}
    4242
    43 static int zynq_cal_baud_rate(uint32_t  baudrate,
     43int zynq_cal_baud_rate(uint32_t  baudrate,
    4444                              uint32_t* brgr,
    4545                              uint32_t* bauddiv,
  • bsps/shared/dev/serial/zynq-uart.c

    r2b56f5a r5686b44d  
    143143)
    144144{
    145 #if 0
    146   volatile zynq_uart *regs = zynq_uart_get_regs(minor);
     145  zynq_uart_context *ctx = (zynq_uart_context *) context;
     146  volatile zynq_uart *regs = ctx->regs;
    147147  uint32_t brgr = 0;
    148148  uint32_t bauddiv = 0;
     149  uint32_t mode = 0;
    149150  int rc;
    150151
     
    153154    return rc;
    154155
     156  /*
     157   * Configure the mode register
     158   */
     159  mode |= ZYNQ_UART_MODE_CHMODE(ZYNQ_UART_MODE_CHMODE_NORMAL);
     160
     161  /*
     162   * Parity
     163   */
     164  mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_NONE);
     165  if (term->c_cflag & PARENB) {
     166    if (!(term->c_cflag & PARODD)) {
     167      mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_ODD);
     168    } else {
     169      mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_EVEN);
     170    }
     171  }
     172
     173  /*
     174   * Character Size
     175   */
     176  switch (term->c_cflag & CSIZE)
     177  {
     178  case CS5:
     179    return false;
     180  case CS6:
     181    mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_6);
     182    break;
     183  case CS7:
     184    mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_7);
     185    break;
     186  case CS8:
     187  default:
     188    mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_8);
     189    break;
     190  }
     191
     192  /*
     193   * Stop Bits
     194   */
     195  if (term->c_cflag & CSTOPB) {
     196    /* 2 stop bits */
     197    mode |= ZYNQ_UART_MODE_NBSTOP(ZYNQ_UART_MODE_NBSTOP_STOP_2);
     198  } else {
     199    /* 1 stop bit */
     200    mode |= ZYNQ_UART_MODE_NBSTOP(ZYNQ_UART_MODE_NBSTOP_STOP_1);
     201  }
     202
    155203  regs->control &= ~(ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN);
     204  regs->mode = mode;
    156205  regs->baud_rate_gen = ZYNQ_UART_BAUD_RATE_GEN_CD(brgr);
    157206  regs->baud_rate_div = ZYNQ_UART_BAUD_RATE_DIV_BDIV(bauddiv);
     
    159208
    160209  return true;
    161 #else
    162   return false;
    163 #endif
    164210}
    165211
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