Changeset 5686b44d in rtems
- Timestamp:
- Dec 2, 2020, 7:20:36 PM (3 months ago)
- Branches:
- master
- Children:
- a92d4ae
- Parents:
- 2b56f5a
- git-author:
- Kinsey Moore <kinsey.moore@…> (12/02/20 19:20:36)
- git-committer:
- Joel Sherrill <joel@…> (12/03/20 23:35:28)
- Location:
- bsps
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
bsps/include/dev/serial/zynq-uart.h
r2b56f5a r5686b44d 79 79 void zynq_uart_reset_tx_flush(zynq_uart_context *ctx); 80 80 81 int zynq_cal_baud_rate( 82 uint32_t baudrate, 83 uint32_t* brgr, 84 uint32_t* bauddiv, 85 uint32_t modereg 86 ); 87 81 88 #ifdef __cplusplus 82 89 } -
bsps/shared/dev/serial/zynq-uart-polled.c
r2b56f5a r5686b44d 41 41 } 42 42 43 staticint zynq_cal_baud_rate(uint32_t baudrate,43 int zynq_cal_baud_rate(uint32_t baudrate, 44 44 uint32_t* brgr, 45 45 uint32_t* bauddiv, -
bsps/shared/dev/serial/zynq-uart.c
r2b56f5a r5686b44d 143 143 ) 144 144 { 145 #if 0 146 volatile zynq_uart *regs = zynq_uart_get_regs(minor);145 zynq_uart_context *ctx = (zynq_uart_context *) context; 146 volatile zynq_uart *regs = ctx->regs; 147 147 uint32_t brgr = 0; 148 148 uint32_t bauddiv = 0; 149 uint32_t mode = 0; 149 150 int rc; 150 151 … … 153 154 return rc; 154 155 156 /* 157 * Configure the mode register 158 */ 159 mode |= ZYNQ_UART_MODE_CHMODE(ZYNQ_UART_MODE_CHMODE_NORMAL); 160 161 /* 162 * Parity 163 */ 164 mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_NONE); 165 if (term->c_cflag & PARENB) { 166 if (!(term->c_cflag & PARODD)) { 167 mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_ODD); 168 } else { 169 mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_EVEN); 170 } 171 } 172 173 /* 174 * Character Size 175 */ 176 switch (term->c_cflag & CSIZE) 177 { 178 case CS5: 179 return false; 180 case CS6: 181 mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_6); 182 break; 183 case CS7: 184 mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_7); 185 break; 186 case CS8: 187 default: 188 mode |= ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_8); 189 break; 190 } 191 192 /* 193 * Stop Bits 194 */ 195 if (term->c_cflag & CSTOPB) { 196 /* 2 stop bits */ 197 mode |= ZYNQ_UART_MODE_NBSTOP(ZYNQ_UART_MODE_NBSTOP_STOP_2); 198 } else { 199 /* 1 stop bit */ 200 mode |= ZYNQ_UART_MODE_NBSTOP(ZYNQ_UART_MODE_NBSTOP_STOP_1); 201 } 202 155 203 regs->control &= ~(ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN); 204 regs->mode = mode; 156 205 regs->baud_rate_gen = ZYNQ_UART_BAUD_RATE_GEN_CD(brgr); 157 206 regs->baud_rate_div = ZYNQ_UART_BAUD_RATE_DIV_BDIV(bauddiv); … … 159 208 160 209 return true; 161 #else162 return false;163 #endif164 210 } 165 211
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