Changeset 54ba5aa in rtems


Ignore:
Timestamp:
Oct 18, 2000, 12:58:29 PM (21 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
e3250b3
Parents:
38e5a9f
Message:

2000-10-18 Joel Sherrill <joel@…>

  • cpu_asm.S, rtems/score/cpu.h: Modified to better support multilibing. These changes result in the code being able to compile with the default gcc settings. It is not functional in this configuration but does compile.
Files:
6 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/h8300/ChangeLog

    r38e5a9f r54ba5aa  
     12000-10-18      Joel Sherrill <joel@OARcorp.com>
     2
     3        * cpu_asm.S, rtems/score/cpu.h: Modified to better support
     4        multilibing.  These changes result in the code being able to
     5        compile with the default gcc settings.  It is not functional
     6        in this configuration but does compile.
     7
    182000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    29
  • c/src/exec/score/cpu/h8300/cpu_asm.S

    r38e5a9f r54ba5aa  
    4949__CPU_Context_switch:
    5050        /* Save Context */
     51#if defined(__H8300H__) || defined(__H8300S__)
    5152        stc.w   ccr,@(0:16,er0)
    5253        mov.l   er7,@(2:16,er0)
     
    6768        mov.l   @(2:16,er1),er7
    6869        ldc.w   @(0:16,er1),ccr
     70#endif
    6971
    7072        rts
     
    7678__CPU_Context_restore:
    7779       
    78         Mov.l   er0,er1
     80#if defined(__H8300H__) || defined(__H8300S__)
     81        mov.l   er0,er1
    7982        jmp             @restore:24
     83#endif
    8084
    8185
     
    97101       
    98102__ISR_Handler:
     103#if defined(__H8300H__) || defined(__H8300S__)
    99104        mov.l   er1,@-er7
    100105        mov.l   er2,@-er7
     
    177182        mov             @er7+,er1
    178183        mov             @er7+,er0
     184#endif
    179185        rte
    180186       
     
    192198_ISR_Dispatch:
    193199       
    194         Jsr             @__Thread_Dispatch
     200#if defined(__H8300H__) || defined(__H8300S__)
     201        jsr             @__Thread_Dispatch
    195202        mov             @er7+,er6
    196203        mov             @er7+,er5
     
    200207        mov             @er7+,er1
    201208        mov             @er7+,er0
     209#endif
    202210        rte
    203211       
  • c/src/exec/score/cpu/h8300/rtems/score/cpu.h

    r38e5a9f r54ba5aa  
    650650/* end of ISR handler macros */
    651651
    652 #else
     652#else /* modern gcc version */
    653653
    654654/*
     
    661661 */
    662662
    663 #if defined(__H8300__)
    664 #define _CPU_ISR_Disable( _isr_cookie )
    665     asm volatile( "orc #0x80,ccr " );
    666 #else
     663#if defined(__H8300H__) || defined(__H8300S__)
    667664#define _CPU_ISR_Disable( _isr_cookie ) \
    668665  do { \
     
    672669    (_isr_cookie) = __ccr; \
    673670  } while (0)
     671#else
     672#define _CPU_ISR_Disable( _isr_cookie ) (_isr_cookie) = 0
    674673#endif
    675674
     
    685684 */
    686685
    687 #if defined(__H8300__)
    688 #define _CPU_ISR_Enable( _isr_cookie )  \
    689    asm(" andc #0x7f,ccr \n")
    690 #else
     686#if defined(__H8300H__) || defined(__H8300S__)
    691687#define _CPU_ISR_Enable( _isr_cookie )  \
    692688  do { \
     
    694690    asm volatile( "ldc %0, ccr" :  : "m" (__ccr) ); \
    695691  } while (0)
     692#else
     693#define _CPU_ISR_Enable( _isr_cookie )
    696694#endif
    697695
     
    707705 */
    708706
    709 #if defined(__H8300__)
    710 #define _CPU_ISR_Enable( _isr_cookie )  \
    711    asm( "andc #0x7f,ccr \n orc #0x80,ccr\n" )
    712 #else
     707#if defined(__H8300H__) || defined(__H8300S__)
    713708#define _CPU_ISR_Flash( _isr_cookie ) \
    714709  do { \
     
    716711    asm volatile( "ldc %0, ccr ; orc #0x80,ccr " :  : "m" (__ccr) ); \
    717712  } while (0)
     713#else
     714#define _CPU_ISR_Flash( _isr_cookie )
    718715#endif
    719716
     
    11521149 */
    11531150 
    1154 static inline unsigned int CPU_swap_u32(
    1155   unsigned int value
     1151static inline unsigned32 CPU_swap_u32(
     1152  unsigned32 value
    11561153)
    11571154{
  • cpukit/score/cpu/h8300/ChangeLog

    r38e5a9f r54ba5aa  
     12000-10-18      Joel Sherrill <joel@OARcorp.com>
     2
     3        * cpu_asm.S, rtems/score/cpu.h: Modified to better support
     4        multilibing.  These changes result in the code being able to
     5        compile with the default gcc settings.  It is not functional
     6        in this configuration but does compile.
     7
    182000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    29
  • cpukit/score/cpu/h8300/cpu_asm.S

    r38e5a9f r54ba5aa  
    4949__CPU_Context_switch:
    5050        /* Save Context */
     51#if defined(__H8300H__) || defined(__H8300S__)
    5152        stc.w   ccr,@(0:16,er0)
    5253        mov.l   er7,@(2:16,er0)
     
    6768        mov.l   @(2:16,er1),er7
    6869        ldc.w   @(0:16,er1),ccr
     70#endif
    6971
    7072        rts
     
    7678__CPU_Context_restore:
    7779       
    78         Mov.l   er0,er1
     80#if defined(__H8300H__) || defined(__H8300S__)
     81        mov.l   er0,er1
    7982        jmp             @restore:24
     83#endif
    8084
    8185
     
    97101       
    98102__ISR_Handler:
     103#if defined(__H8300H__) || defined(__H8300S__)
    99104        mov.l   er1,@-er7
    100105        mov.l   er2,@-er7
     
    177182        mov             @er7+,er1
    178183        mov             @er7+,er0
     184#endif
    179185        rte
    180186       
     
    192198_ISR_Dispatch:
    193199       
    194         Jsr             @__Thread_Dispatch
     200#if defined(__H8300H__) || defined(__H8300S__)
     201        jsr             @__Thread_Dispatch
    195202        mov             @er7+,er6
    196203        mov             @er7+,er5
     
    200207        mov             @er7+,er1
    201208        mov             @er7+,er0
     209#endif
    202210        rte
    203211       
  • cpukit/score/cpu/h8300/rtems/score/cpu.h

    r38e5a9f r54ba5aa  
    650650/* end of ISR handler macros */
    651651
    652 #else
     652#else /* modern gcc version */
    653653
    654654/*
     
    661661 */
    662662
    663 #if defined(__H8300__)
    664 #define _CPU_ISR_Disable( _isr_cookie )
    665     asm volatile( "orc #0x80,ccr " );
    666 #else
     663#if defined(__H8300H__) || defined(__H8300S__)
    667664#define _CPU_ISR_Disable( _isr_cookie ) \
    668665  do { \
     
    672669    (_isr_cookie) = __ccr; \
    673670  } while (0)
     671#else
     672#define _CPU_ISR_Disable( _isr_cookie ) (_isr_cookie) = 0
    674673#endif
    675674
     
    685684 */
    686685
    687 #if defined(__H8300__)
    688 #define _CPU_ISR_Enable( _isr_cookie )  \
    689    asm(" andc #0x7f,ccr \n")
    690 #else
     686#if defined(__H8300H__) || defined(__H8300S__)
    691687#define _CPU_ISR_Enable( _isr_cookie )  \
    692688  do { \
     
    694690    asm volatile( "ldc %0, ccr" :  : "m" (__ccr) ); \
    695691  } while (0)
     692#else
     693#define _CPU_ISR_Enable( _isr_cookie )
    696694#endif
    697695
     
    707705 */
    708706
    709 #if defined(__H8300__)
    710 #define _CPU_ISR_Enable( _isr_cookie )  \
    711    asm( "andc #0x7f,ccr \n orc #0x80,ccr\n" )
    712 #else
     707#if defined(__H8300H__) || defined(__H8300S__)
    713708#define _CPU_ISR_Flash( _isr_cookie ) \
    714709  do { \
     
    716711    asm volatile( "ldc %0, ccr ; orc #0x80,ccr " :  : "m" (__ccr) ); \
    717712  } while (0)
     713#else
     714#define _CPU_ISR_Flash( _isr_cookie )
    718715#endif
    719716
     
    11521149 */
    11531150 
    1154 static inline unsigned int CPU_swap_u32(
    1155   unsigned int value
     1151static inline unsigned32 CPU_swap_u32(
     1152  unsigned32 value
    11561153)
    11571154{
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