Changeset 54a4fe5f in rtems


Ignore:
Timestamp:
Aug 30, 2011, 1:58:05 PM (10 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, 5, master
Children:
5be93c2
Parents:
c1188b41
Message:

2011-08-30 Peter Dufault <dufault@…>

  • make/custom/phycore_mpc5554.cfg, startup/linkcmds.phycore_mpc5554, network/if_smc.c: New files.
  • Makefile.am, preinstall.am: Reflect changes above.
  • configure.ac: Add support for the Phytec PhyCORE MPC5554. Includes:
    • HAS_SMC91111 to indicate a BSP has that neworking.
    • SMC91111_ENADDR_IS_SETUP so that it skips code to set up the MAC address.
    • MPC55XX_CLOCK_EMIOS_CHANNEL to permit one to set which eMIOS channel to use for the clock.
    • MPC55XX_BOOTFLAGS: Skips two words above the RCHW in the startup for use in skpping over the MMU setup. Required for debugging via a cheap emulator where code is loaded into RAM and then mapped in as flash.
  • BOARD_PHYCORE_MPC5554 If defined, use custom settings for the Phytec PhyCORE MPC5554 SOM.
  • clock/clock-config.c: Modify so that the EMIOS channel used for the clock can be selected at configuration time. For MPC5544 only:
    • Conditionally skip access to a register that faults if accessed on the MPC5554
    • Do not set the control register mode as was done for GW_LCFM support, it breaks interrupts.
  • make/custom/mpc55xx.inc: Make it possible to override the soft-float to set the type of floating point BSP will use.
  • startup/start.S: Add support for the "boot flags", two long-words that I manipulate with the debugger to skip over MMU setup. Use an external for the start of external SRAM instead of the hardwired number 0x20000000. Disable write access to the internal flash.
Location:
c/src/lib/libbsp/powerpc/mpc55xxevb
Files:
3 added
7 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/mpc55xxevb/ChangeLog

    rc1188b41 r54a4fe5f  
     12011-08-30      Peter Dufault <dufault@hda.com>
     2
     3        * make/custom/phycore_mpc5554.cfg, startup/linkcmds.phycore_mpc5554,
     4        network/if_smc.c: New files.
     5        * Makefile.am, preinstall.am: Reflect changes above.
     6        * configure.ac: Add support for the Phytec PhyCORE MPC5554.  Includes:
     7          - HAS_SMC91111 to indicate a BSP has that neworking.
     8          - SMC91111_ENADDR_IS_SETUP so that it skips code to set up the MAC
     9          address.
     10          - MPC55XX_CLOCK_EMIOS_CHANNEL to permit one to set which eMIOS
     11          channel to use for the clock.
     12          - MPC55XX_BOOTFLAGS: Skips two words above the RCHW in the startup
     13          for use in skpping over the MMU setup.  Required for debugging via a
     14          cheap emulator where code is loaded into RAM and then mapped in as
     15          flash.
     16         - BOARD_PHYCORE_MPC5554 If defined, use custom settings for the
     17         Phytec PhyCORE MPC5554 SOM.
     18        * clock/clock-config.c: Modify so that the EMIOS channel used for the
     19        clock can be selected at configuration time.  For MPC5544 only:
     20          - Conditionally skip access to a register that faults if accessed on
     21          the MPC5554
     22          - Do not set the control register mode as was done for GW_LCFM
     23          support, it breaks interrupts.
     24        * make/custom/mpc55xx.inc: Make it possible to override the soft-float
     25        to set the type of floating point BSP will use.
     26        * startup/start.S: Add support for the "boot flags", two long-words
     27        that I manipulate with the debugger to skip over MMU setup.  Use an
     28        external for the start of external SRAM instead of the hardwired
     29        number 0x20000000.  Disable write access to the internal flash.
     30
    1312011-08-30      Sebastian Huber <sebastian.huber@embedded-brains.de>
    232
  • c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am

    rc1188b41 r54a4fe5f  
    2525# Link commands
    2626project_lib_DATA += startup/linkcmds
    27 dist_project_lib_DATA += startup/linkcmds.gwlcfm  startup/linkcmds.mpc5566evb \
    28         startup/linkcmds.base   
     27dist_project_lib_DATA += \
     28        startup/linkcmds.gwlcfm \
     29        startup/linkcmds.phycore_mpc5554 \
     30        startup/linkcmds.mpc5566evb \
     31        startup/linkcmds.base
    2932
    3033noinst_LIBRARIES += libbsp.a
     
    7275# Network
    7376if HAS_NETWORKING
    74 libbsp_a_SOURCES += network/smsc9218i.c
     77libbsp_a_SOURCES += network/smsc9218i.c network/if_smc.c
    7578endif
    7679
  • c/src/lib/libbsp/powerpc/mpc55xxevb/clock/clock-config.c

    rc1188b41 r54a4fe5f  
    3131
    3232#include <rtems/status-checks.h>
    33 
    34 #define MPC55XX_CLOCK_EMIOS_CHANNEL (MPC55XX_EMIOS_CHANNEL_NUMBER - 1)
    3533
    3634/* This is defined in clockdrv_shell.h */
     
    105103  regs->CBDR.R = 0;
    106104  regs->CCNTR.R = 0;
     105#if MPC55XX_CHIP_TYPE != 5554
     106  /* This is reserved on the MPC5554.
     107   */
    107108  regs->ALTCADR.R = 0;
     109#endif
    108110
    109111  /* Set control register */
     112  /* The mode change, made by Thomas for GW_LCFM support, breaks interrupts
     113   * on the MPC5554.
     114   */
     115#if MPC55XX_CHIP_TYPE == 5554
     116  ccr.B.MODE = MPC55XX_EMIOS_MODE_MC_UP_INT_CLK;
     117#else
    110118  ccr.B.MODE = MPC55XX_EMIOS_MODE_MCB_UP_INT_CLK;
     119#endif
    111120  ccr.B.UCPREN = 1;
    112121  ccr.B.FEN = 1;
  • c/src/lib/libbsp/powerpc/mpc55xxevb/configure.ac

    rc1188b41 r54a4fe5f  
    5151
    5252RTEMS_BSPOPTS_SET([PRINTK_MINOR],[gwlcfm],[MPC55XX_ESCI_A_MINOR])
     53RTEMS_BSPOPTS_SET([PRINTK_MINOR],[phytec_mpc5554],[MPC55XX_ESCI_A_MINOR])
    5354RTEMS_BSPOPTS_SET([PRINTK_MINOR],[*]     ,[MPC55XX_ESCI_B_MINOR])
    5455RTEMS_BSPOPTS_HELP([PRINTK_MINOR],
     
    8485[Must be defined to set the EMIOS prescaler])
    8586
     87RTEMS_BSPOPTS_SET([HAS_SMC91111],[phycore_mpc5554],[1])
     88RTEMS_BSPOPTS_HELP([HAS_SMC91111],
     89[If defined the board has the SMC91111 networking chip.])
     90
     91RTEMS_BSPOPTS_SET([SMC91111_ENADDR_IS_SETUP],[phycore_mpc5554],[1])
     92RTEMS_BSPOPTS_HELP([SMC91111_ENADDR_IS_SETUP],
     93[If defined the SMC91111 chip has the ethernet address loaded at reset.])
     94
     95RTEMS_BSPOPTS_SET([MPC55XX_CLOCK_EMIOS_CHANNEL],[*],[(MPC55XX_EMIOS_CHANNEL_NUMBER-1)])
     96RTEMS_BSPOPTS_HELP([MPC55XX_CLOCK_EMIOS_CHANNEL],
     97[Define to the eMIOS channel to use for the BSP clock.
     98 The default is the last channel.])
     99
    86100RTEMS_BSPOPTS_SET([MPC55XX_CHIP_TYPE],[mpc5566evb],[5566])
    87101RTEMS_BSPOPTS_SET([MPC55XX_CHIP_TYPE],[gwlcfm]    ,[5516])
     
    89103RTEMS_BSPOPTS_HELP([MPC55XX_CHIP_TYPE],
    90104[specifies the chip type in use (e.g. 5554 for MPC5554)])
     105
     106RTEMS_BSPOPTS_HELP([MPC55XX_BOOTFLAGS],
     107[If defined, builds in bootflags above the RCHW for setup in a debugger to avoid startup MMU setup])
    91108
    92109RTEMS_BSPOPTS_SET([BOARD_GWLCFM],[gwlcfm],[1])
     
    99116RTEMS_BSPOPTS_HELP([RTEMS_BSP_I2C_EEPROM_DEVICE_PATH],[EEPROM device file path])
    100117
     118RTEMS_BSPOPTS_SET([BOARD_PHYCORE_MPC5554],[phycore_mpc5554],[1])
     119RTEMS_BSPOPTS_HELP([BOARD_PHYCORE_MPC5554],
     120[If defined, use custom settings for the Phytec PhyCORE MPC5554 SOM])
     121
    101122AC_CONFIG_FILES([Makefile
    102123include/bspopts.h])
  • c/src/lib/libbsp/powerpc/mpc55xxevb/make/custom/mpc55xx.inc

    rc1188b41 r54a4fe5f  
    1414RTEMS_CPU_MODEL = mpc55xx
    1515
     16CPU_CFLAGS_FLOAT?=-msoft-float
     17
    1618# FIXME
    17 CPU_CFLAGS = -mcpu=8540 -meabi -msdata -fno-common -msoft-float \
     19CPU_CFLAGS = -mcpu=8540 -meabi -msdata -fno-common $(CPU_CFLAGS_FLOAT) \
    1820    -D__ppc_generic -mstrict-align
    1921
  • c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am

    rc1188b41 r54a4fe5f  
    5757        $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.gwlcfm
    5858PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.gwlcfm
     59
     60$(PROJECT_LIB)/linkcmds.phycore_mpc5554: startup/linkcmds.phycore_mpc5554 $(PROJECT_LIB)/$(dirstamp)
     61        $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.phycore_mpc5554
     62PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.phycore_mpc5554
    5963
    6064$(PROJECT_LIB)/linkcmds.mpc5566evb: startup/linkcmds.mpc5566evb $(PROJECT_LIB)/$(dirstamp)
  • c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S

    rc1188b41 r54a4fe5f  
    3030       
    3131.section ".bsp_start_text", "ax"
     32#ifdef MPC55XX_BOOTFLAGS
     33PUBLIC_VAR (mpc55xx_bootflag_0)
     34PUBLIC_VAR (mpc55xx_bootflag_1)
     35#endif
    3236PUBLIC_VAR (start)
    3337.globl  fmpll_syncr_vals
     
    4044        .int 0x005a0000
    4145
    42         /* BAM: Address of start instruction */
    43         .int 0x8
     46#ifdef MPC55XX_BOOTFLAGS
     47        /* BAM: Address of start instruction
     48     *      We skip over the next two boot flag words to the next
     49     *      64-bit aligned start address. It is 64-bit aligned
     50     *      to play well with FLASH programming.
     51     *      These boot flags can be set by debuggers and emulators to
     52     *      customize boot.
     53     *      Currently bit0 of bootflag_0 means to "skip setting up the MMU",
     54     *      allowing external MMU setup in a debugger before branching
     55     *      to 0x10.  This can be used e.g., to map FLASH into RAM.
     56     */
     57        .int 0x00000010 /* Start address is 0x10. */
     58
     59mpc55xx_bootflag_0:
     60    .int 0xffffffff
     61mpc55xx_bootflag_1:
     62    .int 0xffffffff
     63
     64#else
     65        .int 0x00000008 /* Start address is 0x08. */
     66#endif
    4467
    4568/*
     
    98121.equ MAS3, 627
    99122
     123/* Read back MMU TLB1 entry 3 (internal SRAM) and enable the cache.
     124 */
    100125        LWI r3, 0x10030000
    101126        mtspr MAS0, r3
     
    111136 */
    112137
     138/* Read back MMU TLB1 entry 2 (external SRAM) and set the
     139 * logical address to the external RAM start.
     140 */
    113141        LWI r3, 0x10020000
    114142        mtspr MAS0, r3
     
    117145        mfspr r3, MAS3
    118146        and r3, r3, r4
    119         LWI r4, 0x20000000
     147        LA r4, bsp_external_ram_start
    120148        or r3, r3, r4
     149        mtspr MAS3, r3
     150        tlbwe
     151
     152/* Read back MMU TLB1 entry 1 (internal flash) and disable
     153 * write access.
     154 */
     155        LWI r3, 0x10010000
     156        mtspr MAS0, r3
     157        tlbre
     158        LWI r4, ~0x0000000C
     159        mfspr r3, MAS3
     160        and r3, r3, r4
    121161        mtspr MAS3, r3
    122162        tlbwe
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