Changeset 538a0a8 in rtems

Timestamp:

02/02/18 06:06:16 (5 years ago)

Author:

Christian Mauderer <christian.mauderer@…>

Branches:

5, master

Children:

6878519

Parents:

03fecae

git-author:

Christian Mauderer <christian.mauderer@…> (02/02/18 06:06:16)

git-committer:

Christian Mauderer <christian.mauderer@…> (02/12/18 13:25:02)

Message:

bsp/atsam: Allow to use a decoder for SPI CS.

The SPI controller supports a decoder connected to the chip select
lines. This patch allows to use this mode.

Files:

• bsps/arm/atsam/include/bsp/atsam-spi.h (modified) (1 diff)
• c/src/lib/libbsp/arm/atsam/spi/atsam_spi_bus.c (modified) (7 diffs)
• c/src/lib/libbsp/arm/atsam/spi/atsam_spi_init.c (modified) (2 diffs)

bsps/arm/atsam/include/bsp/atsam-spi.h

@@ -22 +22 @@
 #endif /* __cplusplus */
 
+typedef struct {
+  uint8_t     spi_peripheral_id;
+  const Pin  *pins;
+  Spi        *spi_regs;
+  size_t      pin_count;
+  bool        chip_select_decode;
+} atsam_spi_config;
+
 int spi_bus_register_atsam(
   const char *bus_path,
-  uint8_t     spi_peripheral_id,
-  Spi        *spi_regs,
-  const Pin  *pins,
-  size_t      pin_count
+  const atsam_spi_config *config
 );
 

c/src/lib/libbsp/arm/atsam/spi/atsam_spi_bus.c

@@ -50 +50 @@
   int transfer_in_progress;
   bool chip_select_active;
+  bool chip_select_decode;
 } atsam_spi_bus;
 
@@ -92 +93 @@
   uint8_t delay_cs;
   uint32_t csr = 0;
+  uint32_t mode = 0;
+  uint32_t cs = bus->base.cs;
 
   delay_cs = atsam_calculate_dlybcs(bus->base.delay_usecs);
+
+  mode |= SPI_MR_DLYBCS(delay_cs);
+  mode |= SPI_MR_MSTR;
+  mode |= SPI_MR_MODFDIS;
+  if (bus->chip_select_decode) {
+    mode |= SPI_MR_PCS(bus->base.cs);
+    mode |= SPI_MR_PCSDEC;
+    cs /= 4;
+  } else {
+    mode |= SPI_PCS(bus->base.cs);
+  }
 
   SPID_Configure(
@@ -99 +113 @@
     bus->spi.pSpiHw,
     bus->spi.spiId,
-    (SPI_MR_DLYBCS(delay_cs) |
-      SPI_MR_MSTR |
-      SPI_MR_MODFDIS |
-      SPI_PCS(bus->base.cs)),
+    mode,
     &XDMAD_Instance
   );
@@ -114 +125 @@
   atsam_set_phase_and_polarity(bus->base.mode, &csr);
 
-  SPI_ConfigureNPCS(bus->spi.pSpiHw, bus->base.cs, csr);
+  SPI_ConfigureNPCS(bus->spi.pSpiHw, cs, csr);
 }
 
@@ -142 +153 @@
     bus->chip_select_active = true;
 
-    SPI_ChipSelect(pSpiHw, 1 << msg->cs);
+    if (bus->chip_select_decode) {
+      pSpiHw->SPI_MR = (pSpiHw->SPI_MR & ~SPI_MR_PCS_Msk) | SPI_MR_PCS(msg->cs);
+    } else {
+      SPI_ChipSelect(pSpiHw, 1 << msg->cs);
+    }
     SPI_Enable(pSpiHw);
   }
@@ -390 +405 @@
 int spi_bus_register_atsam(
   const char *bus_path,
-  uint8_t     spi_peripheral_id,
-  Spi        *spi_regs,
-  const Pin  *pins,
-  size_t      pin_count
+  const atsam_spi_config *config
 )
 {
@@ -411 +423 @@
   bus->base.delay_usecs = 1;
   bus->base.cs = 1;
-  bus->spi.spiId = spi_peripheral_id;
-  bus->spi.pSpiHw = spi_regs;
-
-  PIO_Configure(pins, pin_count);
-  PMC_EnablePeripheral(spi_peripheral_id);
+  bus->spi.spiId = config->spi_peripheral_id;
+  bus->spi.pSpiHw = config->spi_regs;
+  bus->chip_select_decode = config->chip_select_decode;
+
+  PIO_Configure(config->pins, config->pin_count);
+  PMC_EnablePeripheral(config->spi_peripheral_id);
   atsam_configure_spi(bus);
   atsam_spi_init_xdma(bus);

c/src/lib/libbsp/arm/atsam/spi/atsam_spi_init.c

@@ -67 +67 @@
   };
 
+  static const atsam_spi_config config = {
+    .spi_peripheral_id = ID_SPI0,
+    .spi_regs = SPI0,
+    .pins = pins,
+    .pin_count = RTEMS_ARRAY_SIZE(pins),
+    .chip_select_decode = false
+  };
+
   return spi_bus_register_atsam(
     ATSAM_SPI_0_BUS_PATH,
-    ID_SPI0,
-    SPI0,
-    pins,
-    RTEMS_ARRAY_SIZE(pins)
+    &config
   );
 }
@@ -91 +96 @@
   };
 
+  static const atsam_spi_config config = {
+    .spi_peripheral_id = ID_SPI1,
+    .spi_regs = SPI1,
+    .pins = pins,
+    .pin_count = RTEMS_ARRAY_SIZE(pins),
+    .chip_select_decode = false
+  };
+
   return spi_bus_register_atsam(
     ATSAM_SPI_1_BUS_PATH,
-    ID_SPI1,
-    SPI1,
-    pins,
-    RTEMS_ARRAY_SIZE(pins)
+    &config
   );
 }