Changeset 538a0a8 in rtems


Ignore:
Timestamp:
Feb 2, 2018, 6:06:16 AM (21 months ago)
Author:
Christian Mauderer <christian.mauderer@…>
Branches:
master
Children:
6878519
Parents:
03fecae
git-author:
Christian Mauderer <christian.mauderer@…> (02/02/18 06:06:16)
git-committer:
Christian Mauderer <christian.mauderer@…> (02/12/18 13:25:02)
Message:

bsp/atsam: Allow to use a decoder for SPI CS.

The SPI controller supports a decoder connected to the chip select
lines. This patch allows to use this mode.

Files:
3 edited

Legend:

Unmodified
Added
Removed
  • bsps/arm/atsam/include/bsp/atsam-spi.h

    r03fecae r538a0a8  
    2222#endif /* __cplusplus */
    2323
     24typedef struct {
     25  uint8_t     spi_peripheral_id;
     26  const Pin  *pins;
     27  Spi        *spi_regs;
     28  size_t      pin_count;
     29  bool        chip_select_decode;
     30} atsam_spi_config;
     31
    2432int spi_bus_register_atsam(
    2533  const char *bus_path,
    26   uint8_t     spi_peripheral_id,
    27   Spi        *spi_regs,
    28   const Pin  *pins,
    29   size_t      pin_count
     34  const atsam_spi_config *config
    3035);
    3136
  • c/src/lib/libbsp/arm/atsam/spi/atsam_spi_bus.c

    r03fecae r538a0a8  
    5050  int transfer_in_progress;
    5151  bool chip_select_active;
     52  bool chip_select_decode;
    5253} atsam_spi_bus;
    5354
     
    9293  uint8_t delay_cs;
    9394  uint32_t csr = 0;
     95  uint32_t mode = 0;
     96  uint32_t cs = bus->base.cs;
    9497
    9598  delay_cs = atsam_calculate_dlybcs(bus->base.delay_usecs);
     99
     100  mode |= SPI_MR_DLYBCS(delay_cs);
     101  mode |= SPI_MR_MSTR;
     102  mode |= SPI_MR_MODFDIS;
     103  if (bus->chip_select_decode) {
     104    mode |= SPI_MR_PCS(bus->base.cs);
     105    mode |= SPI_MR_PCSDEC;
     106    cs /= 4;
     107  } else {
     108    mode |= SPI_PCS(bus->base.cs);
     109  }
    96110
    97111  SPID_Configure(
     
    99113    bus->spi.pSpiHw,
    100114    bus->spi.spiId,
    101     (SPI_MR_DLYBCS(delay_cs) |
    102       SPI_MR_MSTR |
    103       SPI_MR_MODFDIS |
    104       SPI_PCS(bus->base.cs)),
     115    mode,
    105116    &XDMAD_Instance
    106117  );
     
    114125  atsam_set_phase_and_polarity(bus->base.mode, &csr);
    115126
    116   SPI_ConfigureNPCS(bus->spi.pSpiHw, bus->base.cs, csr);
     127  SPI_ConfigureNPCS(bus->spi.pSpiHw, cs, csr);
    117128}
    118129
     
    142153    bus->chip_select_active = true;
    143154
    144     SPI_ChipSelect(pSpiHw, 1 << msg->cs);
     155    if (bus->chip_select_decode) {
     156      pSpiHw->SPI_MR = (pSpiHw->SPI_MR & ~SPI_MR_PCS_Msk) | SPI_MR_PCS(msg->cs);
     157    } else {
     158      SPI_ChipSelect(pSpiHw, 1 << msg->cs);
     159    }
    145160    SPI_Enable(pSpiHw);
    146161  }
     
    390405int spi_bus_register_atsam(
    391406  const char *bus_path,
    392   uint8_t     spi_peripheral_id,
    393   Spi        *spi_regs,
    394   const Pin  *pins,
    395   size_t      pin_count
     407  const atsam_spi_config *config
    396408)
    397409{
     
    411423  bus->base.delay_usecs = 1;
    412424  bus->base.cs = 1;
    413   bus->spi.spiId = spi_peripheral_id;
    414   bus->spi.pSpiHw = spi_regs;
    415 
    416   PIO_Configure(pins, pin_count);
    417   PMC_EnablePeripheral(spi_peripheral_id);
     425  bus->spi.spiId = config->spi_peripheral_id;
     426  bus->spi.pSpiHw = config->spi_regs;
     427  bus->chip_select_decode = config->chip_select_decode;
     428
     429  PIO_Configure(config->pins, config->pin_count);
     430  PMC_EnablePeripheral(config->spi_peripheral_id);
    418431  atsam_configure_spi(bus);
    419432  atsam_spi_init_xdma(bus);
  • c/src/lib/libbsp/arm/atsam/spi/atsam_spi_init.c

    r03fecae r538a0a8  
    6767  };
    6868
     69  static const atsam_spi_config config = {
     70    .spi_peripheral_id = ID_SPI0,
     71    .spi_regs = SPI0,
     72    .pins = pins,
     73    .pin_count = RTEMS_ARRAY_SIZE(pins),
     74    .chip_select_decode = false
     75  };
     76
    6977  return spi_bus_register_atsam(
    7078    ATSAM_SPI_0_BUS_PATH,
    71     ID_SPI0,
    72     SPI0,
    73     pins,
    74     RTEMS_ARRAY_SIZE(pins)
     79    &config
    7580  );
    7681}
     
    9196  };
    9297
     98  static const atsam_spi_config config = {
     99    .spi_peripheral_id = ID_SPI1,
     100    .spi_regs = SPI1,
     101    .pins = pins,
     102    .pin_count = RTEMS_ARRAY_SIZE(pins),
     103    .chip_select_decode = false
     104  };
     105
    93106  return spi_bus_register_atsam(
    94107    ATSAM_SPI_1_BUS_PATH,
    95     ID_SPI1,
    96     SPI1,
    97     pins,
    98     RTEMS_ARRAY_SIZE(pins)
     108    &config
    99109  );
    100110}
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