Ignore:
Timestamp:
Jan 30, 2017, 4:58:24 PM (4 years ago)
Author:
Kevin Kirspel <kevin-kirspel@…>
Branches:
b96abfd647154f10ea8f7fac68e25676636eded5, 13421d06177df03916665bb2f3a7fcadc51a951b, d964a6703c705cc92fd053bcefc08bb3b6baa0e2, b1e67a2bdc575f7f6e0af4922d7adb91545827ca
Children:
803a495
Parents:
ea395a7
git-author:
Kevin Kirspel <kevin-kirspel@…> (01/30/17 16:58:24)
git-committer:
Sebastian Huber <sebastian.huber@…> (02/14/17 08:37:12)
Message:

Add support for LPC32XX cache

File:
1 edited

Legend:

Unmodified
Added
Removed
  • rtemsbsd/include/machine/rtems-bsd-cache.h

    • Property mode changed from 100644 to 100755
    rea395a7 r5382f639  
    4343#include <bsp.h>
    4444
    45 #if defined(LIBBSP_ARM_LPC24XX_BSP_H)
     45#if defined(LIBBSP_ARM_LPC24XX_BSP_H) || (defined(LIBBSP_ARM_LPC32XX_BSP_H) && defined(LPC32XX_DISABLE_MMU))
    4646  /* No cache */
    4747#elif defined(LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H) || \
    48   defined(LIBBSP_ARM_XILINX_ZYNQ_BSP_H)
     48  defined(LIBBSP_ARM_XILINX_ZYNQ_BSP_H) || (defined(LIBBSP_ARM_LPC32XX_BSP_H) && !defined(LPC32XX_DISABLE_MMU))
    4949  /* With cache, no coherency support in hardware */
    5050  #define CPU_DATA_CACHE_ALIGNMENT 32
    51 #elif defined(LIBBSP_ARM_LPC32XX_BSP_H)
    52   /* With cache, no coherency support in hardware */
    53   #include <libcpu/cache.h>
    5451#elif defined(__GEN83xx_BSP_h)
    5552  /* With cache, coherency support in hardware */
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