Changeset 52f4fb6 in rtems


Ignore:
Timestamp:
Jun 26, 2018, 5:48:06 AM (10 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
b0ee789
Parents:
fef0a41
git-author:
Sebastian Huber <sebastian.huber@…> (06/26/18 05:48:06)
git-committer:
Sebastian Huber <sebastian.huber@…> (06/27/18 06:58:18)
Message:

riscv: Format assembler files

Use tabs to match the GCC generated assembler output.

Update #3433.

Files:
5 edited

Legend:

Unmodified
Added
Removed
  • bsps/riscv/riscv/start/start.S

    rfef0a41 r52f4fb6  
    2727 * SUCH DAMAGE.
    2828 */
     29
    2930#include <bsp/linker-symbols.h>
    3031#include <rtems/score/riscv-utility.h>
     
    4142PUBLIC(_start)
    4243
    43 .section .bsp_start_text, "wax"
     44        .section        .bsp_start_text, "ax", @progbits
     45        .align  2
     46
    4447TYPE_FUNC(_start)
    4548SYM(_start):
    46   la t0, ISR_Handler
    47   csrw mtvec, t0
     49        la      t0, ISR_Handler
     50        csrw    mtvec, t0
    4851
    49   /* load stack and frame pointers */
    50   la sp, _Configuration_Interrupt_stack_area_end
     52        /* load stack and frame pointers */
     53        la      sp, _Configuration_Interrupt_stack_area_end
    5154
    52   /* Clearing .bss */
    53   la t0, bsp_section_bss_begin
    54   la t1, bsp_section_bss_end
     55        /* Clearing .bss */
     56        la      t0, bsp_section_bss_begin
     57        la      t1, bsp_section_bss_end
    5558
    5659_loop_clear_bss:
    57   bge   t0, t1, _end_clear_bss
    58   SREG    x0, 0(t0)
    59   addi  t0, t0, CPU_SIZEOF_POINTER
    60   j     _loop_clear_bss
     60        bge     t0, t1, _end_clear_bss
     61        SREG    x0, 0(t0)
     62        addi    t0, t0, CPU_SIZEOF_POINTER
     63        j       _loop_clear_bss
    6164_end_clear_bss:
    6265
    63   /* Init FPU unit if it's there */
    64   li t0, MSTATUS_FS
    65   csrs mstatus, t0
     66        /* Init FPU unit if it's there */
     67        li      t0, MSTATUS_FS
     68        csrs    mstatus, t0
    6669
    67   j boot_card
     70        j       boot_card
    6871
    69   .align 4
     72        .align  4
    7073bsp_start_vector_table_begin:
    71   .word _RISCV_Exception_default /* User int */
    72   .word _RISCV_Exception_default /* Supervisor int */
    73   .word _RISCV_Exception_default /* Reserved */
    74   .word _RISCV_Exception_default /* Machine int */
    75   .word _RISCV_Exception_default /* User timer int */
    76   .word _RISCV_Exception_default /* Supervisor Timer int */
    77   .word _RISCV_Exception_default /* Reserved */
    78   .word _RISCV_Exception_default /* Machine Timer int */
    79   .word _RISCV_Exception_default /* User external int */
    80   .word _RISCV_Exception_default /* Supervisor external int */
    81   .word _RISCV_Exception_default /* Reserved */
    82   .word _RISCV_Exception_default /* Machine external int */
    83   .word _RISCV_Exception_default
    84   .word _RISCV_Exception_default
    85   .word _RISCV_Exception_default
    86   .word _RISCV_Exception_default
     74        .word   _RISCV_Exception_default /* User int */
     75        .word   _RISCV_Exception_default /* Supervisor int */
     76        .word   _RISCV_Exception_default /* Reserved */
     77        .word   _RISCV_Exception_default /* Machine int */
     78        .word   _RISCV_Exception_default /* User timer int */
     79        .word   _RISCV_Exception_default /* Supervisor Timer int */
     80        .word   _RISCV_Exception_default /* Reserved */
     81        .word   _RISCV_Exception_default /* Machine Timer int */
     82        .word   _RISCV_Exception_default /* User external int */
     83        .word   _RISCV_Exception_default /* Supervisor external int */
     84        .word   _RISCV_Exception_default /* Reserved */
     85        .word   _RISCV_Exception_default /* Machine external int */
     86        .word   _RISCV_Exception_default
     87        .word   _RISCV_Exception_default
     88        .word   _RISCV_Exception_default
     89        .word   _RISCV_Exception_default
    8790bsp_start_vector_table_end:
  • cpukit/score/cpu/riscv/riscv-context-switch.S

    rfef0a41 r52f4fb6  
    3434#include <rtems/score/cpu.h>
    3535
    36 .section .text, "ax"
    37 .align 4
     36        .section        .text, "ax", @progbits
     37        .align  2
    3838
    3939PUBLIC(_CPU_Context_switch)
     
    4444
    4545SYM(_CPU_Context_switch):
    46   /* Disable interrupts and store all registers */
    47   csrr t0, mstatus
    48   SREG t0, (32 * CPU_SIZEOF_POINTER)(a0)
     46        /* Disable interrupts and store all registers */
     47        csrr    t0, mstatus
     48        SREG    t0, (32 * CPU_SIZEOF_POINTER)(a0)
    4949
    50   csrci mstatus, MSTATUS_MIE
     50        csrci   mstatus, MSTATUS_MIE
    5151
    52   SREG x1, (1 * CPU_SIZEOF_POINTER)(a0)
    53   SREG x2, (2 * CPU_SIZEOF_POINTER)(a0)
    54   SREG x3, (3 * CPU_SIZEOF_POINTER)(a0)
    55   SREG x4, (4 * CPU_SIZEOF_POINTER)(a0)
    56   SREG x5, (5 * CPU_SIZEOF_POINTER)(a0)
    57   SREG x6, (6 * CPU_SIZEOF_POINTER)(a0)
    58   SREG x7, (7 * CPU_SIZEOF_POINTER)(a0)
    59   SREG x8, (8 * CPU_SIZEOF_POINTER)(a0)
    60   SREG x9, (9 * CPU_SIZEOF_POINTER)(a0)
    61   SREG x10, (10 * CPU_SIZEOF_POINTER)(a0)
    62   SREG x11, (11 * CPU_SIZEOF_POINTER)(a0)
    63   SREG x12, (12 * CPU_SIZEOF_POINTER)(a0)
    64   SREG x13, (13 * CPU_SIZEOF_POINTER)(a0)
    65   SREG x14, (14 * CPU_SIZEOF_POINTER)(a0)
    66   SREG x15, (15 * CPU_SIZEOF_POINTER)(a0)
    67   SREG x16, (16 * CPU_SIZEOF_POINTER)(a0)
    68   SREG x17, (17 * CPU_SIZEOF_POINTER)(a0)
    69   SREG x18, (18 * CPU_SIZEOF_POINTER)(a0)
    70   SREG x19, (19 * CPU_SIZEOF_POINTER)(a0)
    71   SREG x20, (20 * CPU_SIZEOF_POINTER)(a0)
    72   SREG x21, (21 * CPU_SIZEOF_POINTER)(a0)
    73   SREG x22, (22 * CPU_SIZEOF_POINTER)(a0)
    74   SREG x23, (23 * CPU_SIZEOF_POINTER)(a0)
    75   SREG x24, (24 * CPU_SIZEOF_POINTER)(a0)
    76   SREG x25, (25 * CPU_SIZEOF_POINTER)(a0)
    77   SREG x26, (26 * CPU_SIZEOF_POINTER)(a0)
    78   SREG x27, (27 * CPU_SIZEOF_POINTER)(a0)
    79   SREG x28, (28 * CPU_SIZEOF_POINTER)(a0)
    80   SREG x29, (28 * CPU_SIZEOF_POINTER)(a0)
    81   SREG x30, (30 * CPU_SIZEOF_POINTER)(a0)
    82   SREG x31, (31 * CPU_SIZEOF_POINTER)(a0)
     52        SREG    x1, (1 * CPU_SIZEOF_POINTER)(a0)
     53        SREG    x2, (2 * CPU_SIZEOF_POINTER)(a0)
     54        SREG    x3, (3 * CPU_SIZEOF_POINTER)(a0)
     55        SREG    x4, (4 * CPU_SIZEOF_POINTER)(a0)
     56        SREG    x5, (5 * CPU_SIZEOF_POINTER)(a0)
     57        SREG    x6, (6 * CPU_SIZEOF_POINTER)(a0)
     58        SREG    x7, (7 * CPU_SIZEOF_POINTER)(a0)
     59        SREG    x8, (8 * CPU_SIZEOF_POINTER)(a0)
     60        SREG    x9, (9 * CPU_SIZEOF_POINTER)(a0)
     61        SREG    x10, (10 * CPU_SIZEOF_POINTER)(a0)
     62        SREG    x11, (11 * CPU_SIZEOF_POINTER)(a0)
     63        SREG    x12, (12 * CPU_SIZEOF_POINTER)(a0)
     64        SREG    x13, (13 * CPU_SIZEOF_POINTER)(a0)
     65        SREG    x14, (14 * CPU_SIZEOF_POINTER)(a0)
     66        SREG    x15, (15 * CPU_SIZEOF_POINTER)(a0)
     67        SREG    x16, (16 * CPU_SIZEOF_POINTER)(a0)
     68        SREG    x17, (17 * CPU_SIZEOF_POINTER)(a0)
     69        SREG    x18, (18 * CPU_SIZEOF_POINTER)(a0)
     70        SREG    x19, (19 * CPU_SIZEOF_POINTER)(a0)
     71        SREG    x20, (20 * CPU_SIZEOF_POINTER)(a0)
     72        SREG    x21, (21 * CPU_SIZEOF_POINTER)(a0)
     73        SREG    x22, (22 * CPU_SIZEOF_POINTER)(a0)
     74        SREG    x23, (23 * CPU_SIZEOF_POINTER)(a0)
     75        SREG    x24, (24 * CPU_SIZEOF_POINTER)(a0)
     76        SREG    x25, (25 * CPU_SIZEOF_POINTER)(a0)
     77        SREG    x26, (26 * CPU_SIZEOF_POINTER)(a0)
     78        SREG    x27, (27 * CPU_SIZEOF_POINTER)(a0)
     79        SREG    x28, (28 * CPU_SIZEOF_POINTER)(a0)
     80        SREG    x29, (28 * CPU_SIZEOF_POINTER)(a0)
     81        SREG    x30, (30 * CPU_SIZEOF_POINTER)(a0)
     82        SREG    x31, (31 * CPU_SIZEOF_POINTER)(a0)
    8383
    84   SYM(restore):
     84        SYM(restore):
    8585
    86   LREG x1, (1 * CPU_SIZEOF_POINTER)(a1)
    87   LREG x2, (2 * CPU_SIZEOF_POINTER)(a1)
    88   LREG x3, (3 * CPU_SIZEOF_POINTER)(a1)
    89   LREG x4, (4 * CPU_SIZEOF_POINTER)(a1)
    90   LREG x5, (5 * CPU_SIZEOF_POINTER)(a1)
    91   LREG x6, (6 * CPU_SIZEOF_POINTER)(a1)
    92   LREG x7, (7 * CPU_SIZEOF_POINTER)(a1)
    93   LREG x8, (8 * CPU_SIZEOF_POINTER)(a1)
    94   LREG x9, (9 * CPU_SIZEOF_POINTER)(a1)
    95   LREG x10, (10 * CPU_SIZEOF_POINTER)(a1)
    96   /* Skip a1/x11 */
    97   LREG x12, (12 * CPU_SIZEOF_POINTER)(a1)
    98   LREG x13, (13 * CPU_SIZEOF_POINTER)(a1)
    99   LREG x14, (14 * CPU_SIZEOF_POINTER)(a1)
    100   LREG x15, (15 * CPU_SIZEOF_POINTER)(a1)
    101   LREG x16, (16 * CPU_SIZEOF_POINTER)(a1)
    102   LREG x17, (17 * CPU_SIZEOF_POINTER)(a1)
    103   LREG x18, (18 * CPU_SIZEOF_POINTER)(a1)
    104   LREG x19, (19 * CPU_SIZEOF_POINTER)(a1)
    105   LREG x20, (20 * CPU_SIZEOF_POINTER)(a1)
    106   LREG x21, (21 * CPU_SIZEOF_POINTER)(a1)
    107   LREG x22, (22 * CPU_SIZEOF_POINTER)(a1)
    108   LREG x23, (23 * CPU_SIZEOF_POINTER)(a1)
    109   LREG x24, (24 * CPU_SIZEOF_POINTER)(a1)
    110   LREG x25, (25 * CPU_SIZEOF_POINTER)(a1)
    111   LREG x26, (26 * CPU_SIZEOF_POINTER)(a1)
    112   LREG x27, (27 * CPU_SIZEOF_POINTER)(a1)
    113   LREG x28, (28 * CPU_SIZEOF_POINTER)(a1)
    114   LREG x29, (29 * CPU_SIZEOF_POINTER)(a1)
    115   LREG x30, (30 * CPU_SIZEOF_POINTER)(a1)
     86        LREG    x1, (1 * CPU_SIZEOF_POINTER)(a1)
     87        LREG    x2, (2 * CPU_SIZEOF_POINTER)(a1)
     88        LREG    x3, (3 * CPU_SIZEOF_POINTER)(a1)
     89        LREG    x4, (4 * CPU_SIZEOF_POINTER)(a1)
     90        LREG    x5, (5 * CPU_SIZEOF_POINTER)(a1)
     91        LREG    x6, (6 * CPU_SIZEOF_POINTER)(a1)
     92        LREG    x7, (7 * CPU_SIZEOF_POINTER)(a1)
     93        LREG    x8, (8 * CPU_SIZEOF_POINTER)(a1)
     94        LREG    x9, (9 * CPU_SIZEOF_POINTER)(a1)
     95        LREG    x10, (10 * CPU_SIZEOF_POINTER)(a1)
     96        /* Skip a1/x11 */
     97        LREG    x12, (12 * CPU_SIZEOF_POINTER)(a1)
     98        LREG    x13, (13 * CPU_SIZEOF_POINTER)(a1)
     99        LREG    x14, (14 * CPU_SIZEOF_POINTER)(a1)
     100        LREG    x15, (15 * CPU_SIZEOF_POINTER)(a1)
     101        LREG    x16, (16 * CPU_SIZEOF_POINTER)(a1)
     102        LREG    x17, (17 * CPU_SIZEOF_POINTER)(a1)
     103        LREG    x18, (18 * CPU_SIZEOF_POINTER)(a1)
     104        LREG    x19, (19 * CPU_SIZEOF_POINTER)(a1)
     105        LREG    x20, (20 * CPU_SIZEOF_POINTER)(a1)
     106        LREG    x21, (21 * CPU_SIZEOF_POINTER)(a1)
     107        LREG    x22, (22 * CPU_SIZEOF_POINTER)(a1)
     108        LREG    x23, (23 * CPU_SIZEOF_POINTER)(a1)
     109        LREG    x24, (24 * CPU_SIZEOF_POINTER)(a1)
     110        LREG    x25, (25 * CPU_SIZEOF_POINTER)(a1)
     111        LREG    x26, (26 * CPU_SIZEOF_POINTER)(a1)
     112        LREG    x27, (27 * CPU_SIZEOF_POINTER)(a1)
     113        LREG    x28, (28 * CPU_SIZEOF_POINTER)(a1)
     114        LREG    x29, (29 * CPU_SIZEOF_POINTER)(a1)
     115        LREG    x30, (30 * CPU_SIZEOF_POINTER)(a1)
    116116
    117   /* Load mstatus */
    118   LREG x31, (32 * CPU_SIZEOF_POINTER)(a1)
    119   csrw mstatus, x31
     117        /* Load mstatus */
     118        LREG    x31, (32 * CPU_SIZEOF_POINTER)(a1)
     119        csrw    mstatus, x31
    120120
    121   LREG x30, (30 * CPU_SIZEOF_POINTER)(a1)
     121        LREG    x30, (30 * CPU_SIZEOF_POINTER)(a1)
    122122
    123   LREG x11, (11 * CPU_SIZEOF_POINTER)(a1)
     123        LREG    x11, (11 * CPU_SIZEOF_POINTER)(a1)
    124124
    125   ret
     125        ret
    126126
    127   SYM(_CPU_Context_restore):
    128   mv     a1, a0
    129   j      restore
     127        SYM(_CPU_Context_restore):
     128        mv      a1, a0
     129        j       restore
    130130
    131   /* TODO no FP support for riscv32 yet */
    132   SYM(_CPU_Context_restore_fp):
    133   nop
     131        /* TODO no FP support for riscv32 yet */
     132        SYM(_CPU_Context_restore_fp):
     133        nop
    134134
    135   SYM(_CPU_Context_save_fp):
    136   nop
     135        SYM(_CPU_Context_save_fp):
     136        nop
  • cpukit/score/cpu/riscv/riscv-context-validate.S

    rfef0a41 r52f4fb6  
    3131#include <rtems/score/cpu.h>
    3232
    33 .section        .text
    34 
     33        .section        .text, "ax", @progbits
     34        .align  2
    3535
    3636PUBLIC(_CPU_Context_validate)
    3737SYM(_CPU_Context_validate):
    38   /* RISC-V/RTEMS context has 36 registers of CPU_SIZEOF_POINTER size */
    39   addi sp, sp, -1 * 36 * CPU_SIZEOF_POINTER
    40 
    41   SREG x1, (1 * CPU_SIZEOF_POINTER)(sp)
    42   /* Skip x2/sp */
    43   SREG x3, (3 * CPU_SIZEOF_POINTER)(sp)
    44   SREG x4, (4 * CPU_SIZEOF_POINTER)(sp)
    45   SREG x5, (5 * CPU_SIZEOF_POINTER)(sp)
    46   SREG x6, (6 * CPU_SIZEOF_POINTER)(sp)
    47   SREG x7, (7 * CPU_SIZEOF_POINTER)(sp)
    48   SREG x8, (8 * CPU_SIZEOF_POINTER)(sp)
    49   SREG x9, (9 * CPU_SIZEOF_POINTER)(sp)
    50   SREG x10, (10 * CPU_SIZEOF_POINTER)(sp)
    51   SREG x11, (11 * CPU_SIZEOF_POINTER)(sp)
    52   SREG x12, (12 * CPU_SIZEOF_POINTER)(sp)
    53   SREG x13, (13 * CPU_SIZEOF_POINTER)(sp)
    54   SREG x14, (14 * CPU_SIZEOF_POINTER)(sp)
    55   SREG x15, (15 * CPU_SIZEOF_POINTER)(sp)
    56   SREG x16, (16 * CPU_SIZEOF_POINTER)(sp)
    57   SREG x17, (17 * CPU_SIZEOF_POINTER)(sp)
    58   SREG x18, (18 * CPU_SIZEOF_POINTER)(sp)
    59   SREG x19, (19 * CPU_SIZEOF_POINTER)(sp)
    60   SREG x20, (20 * CPU_SIZEOF_POINTER)(sp)
    61   SREG x21, (21 * CPU_SIZEOF_POINTER)(sp)
    62   SREG x22, (22 * CPU_SIZEOF_POINTER)(sp)
    63   SREG x23, (23 * CPU_SIZEOF_POINTER)(sp)
    64   SREG x24, (24 * CPU_SIZEOF_POINTER)(sp)
    65   SREG x25, (25 * CPU_SIZEOF_POINTER)(sp)
    66   SREG x26, (26 * CPU_SIZEOF_POINTER)(sp)
    67   SREG x27, (27 * CPU_SIZEOF_POINTER)(sp)
    68   SREG x28, (28 * CPU_SIZEOF_POINTER)(sp)
    69   SREG x29, (28 * CPU_SIZEOF_POINTER)(sp)
    70   SREG x30, (30 * CPU_SIZEOF_POINTER)(sp)
    71   SREG x31, (31 * CPU_SIZEOF_POINTER)(sp)
    72 
    73   /* Fill */
    74 
    75   /* t0 is used for temporary values */
    76   mv t0, x0
    77 
    78   /* x31 contains the stack pointer */
    79   mv x31, sp
    80 
    81   .macro fill_register reg
    82   addi  t0, t0,  1
    83   mv    \reg, t0
    84   .endm
    85 
    86   fill_register x1
    87   fill_register x2
    88   fill_register x3
    89   fill_register x4
    90   fill_register x5
    91   fill_register x6
    92   fill_register x7
    93   fill_register x8
    94   fill_register x9
    95   fill_register x10
    96   fill_register x11
    97   fill_register x12
    98   fill_register x13
    99   fill_register x14
    100   fill_register x15
    101   fill_register x16
    102   fill_register x17
    103   fill_register x18
    104   fill_register x19
    105   fill_register x20
    106   fill_register x21
    107   fill_register x22
    108   fill_register x23
    109   fill_register x24
    110   fill_register x25
    111   fill_register x26
    112   fill_register x27
    113   fill_register x28
    114   fill_register x29
    115   fill_register x30
    116   fill_register x31
    117 
    118   /* Check */
     38        /* RISC-V/RTEMS context has 36 registers of CPU_SIZEOF_POINTER size */
     39        addi    sp, sp, -1 * 36 * CPU_SIZEOF_POINTER
     40
     41        SREG    x1, (1 * CPU_SIZEOF_POINTER)(sp)
     42        /* Skip x2/sp */
     43        SREG    x3, (3 * CPU_SIZEOF_POINTER)(sp)
     44        SREG    x4, (4 * CPU_SIZEOF_POINTER)(sp)
     45        SREG    x5, (5 * CPU_SIZEOF_POINTER)(sp)
     46        SREG    x6, (6 * CPU_SIZEOF_POINTER)(sp)
     47        SREG    x7, (7 * CPU_SIZEOF_POINTER)(sp)
     48        SREG    x8, (8 * CPU_SIZEOF_POINTER)(sp)
     49        SREG    x9, (9 * CPU_SIZEOF_POINTER)(sp)
     50        SREG    x10, (10 * CPU_SIZEOF_POINTER)(sp)
     51        SREG    x11, (11 * CPU_SIZEOF_POINTER)(sp)
     52        SREG    x12, (12 * CPU_SIZEOF_POINTER)(sp)
     53        SREG    x13, (13 * CPU_SIZEOF_POINTER)(sp)
     54        SREG    x14, (14 * CPU_SIZEOF_POINTER)(sp)
     55        SREG    x15, (15 * CPU_SIZEOF_POINTER)(sp)
     56        SREG    x16, (16 * CPU_SIZEOF_POINTER)(sp)
     57        SREG    x17, (17 * CPU_SIZEOF_POINTER)(sp)
     58        SREG    x18, (18 * CPU_SIZEOF_POINTER)(sp)
     59        SREG    x19, (19 * CPU_SIZEOF_POINTER)(sp)
     60        SREG    x20, (20 * CPU_SIZEOF_POINTER)(sp)
     61        SREG    x21, (21 * CPU_SIZEOF_POINTER)(sp)
     62        SREG    x22, (22 * CPU_SIZEOF_POINTER)(sp)
     63        SREG    x23, (23 * CPU_SIZEOF_POINTER)(sp)
     64        SREG    x24, (24 * CPU_SIZEOF_POINTER)(sp)
     65        SREG    x25, (25 * CPU_SIZEOF_POINTER)(sp)
     66        SREG    x26, (26 * CPU_SIZEOF_POINTER)(sp)
     67        SREG    x27, (27 * CPU_SIZEOF_POINTER)(sp)
     68        SREG    x28, (28 * CPU_SIZEOF_POINTER)(sp)
     69        SREG    x29, (28 * CPU_SIZEOF_POINTER)(sp)
     70        SREG    x30, (30 * CPU_SIZEOF_POINTER)(sp)
     71        SREG    x31, (31 * CPU_SIZEOF_POINTER)(sp)
     72
     73        /* Fill */
     74
     75        /* t0 is used for temporary values */
     76        mv      t0, x0
     77
     78        /* x31 contains the stack pointer */
     79        mv      x31, sp
     80
     81        .macro  fill_register reg
     82        addi    t0,     t0,  1
     83        mv      \reg,   t0
     84        .endm
     85
     86        fill_register   x1
     87        fill_register   x2
     88        fill_register   x3
     89        fill_register   x4
     90        fill_register   x5
     91        fill_register   x6
     92        fill_register   x7
     93        fill_register   x8
     94        fill_register   x9
     95        fill_register   x10
     96        fill_register   x11
     97        fill_register   x12
     98        fill_register   x13
     99        fill_register   x14
     100        fill_register   x15
     101        fill_register   x16
     102        fill_register   x17
     103        fill_register   x18
     104        fill_register   x19
     105        fill_register   x20
     106        fill_register   x21
     107        fill_register   x22
     108        fill_register   x23
     109        fill_register   x24
     110        fill_register   x25
     111        fill_register   x26
     112        fill_register   x27
     113        fill_register   x28
     114        fill_register   x29
     115        fill_register   x30
     116        fill_register   x31
     117
     118        /* Check */
    119119check:
    120120
    121   .macro check_register reg
    122   addi t0, t0, 1
    123   bne \reg, t0, restore
    124   .endm
    125 
    126   bne   x31, sp, restore
    127 
    128   mv t0, x0
    129 
    130   check_register        x1
    131   check_register        x2
    132   check_register        x3
    133   check_register        x4
    134   check_register        x5
    135   check_register        x6
    136   check_register        x7
    137   check_register        x8
    138   check_register        x9
    139   check_register        x10
    140   check_register        x11
    141   check_register        x12
    142   check_register        x13
    143   check_register        x14
    144   check_register        x15
    145   check_register        x16
    146   check_register        x17
    147   check_register        x18
    148   check_register        x19
    149   check_register        x20
    150   check_register        x21
    151   check_register        x22
    152   check_register        x23
    153   check_register        x24
    154   check_register        x25
    155   check_register        x26
    156   check_register        x27
    157   check_register        x28
    158   check_register        x29
    159   check_register        x30
    160   check_register        x31
    161 
    162   j check
    163 
    164   /* Restore */
     121        .macro  check_register reg
     122        addi    t0, t0, 1
     123        bne     \reg, t0, restore
     124        .endm
     125
     126        bne     x31, sp, restore
     127
     128        mv      t0, x0
     129
     130        check_register  x1
     131        check_register  x2
     132        check_register  x3
     133        check_register  x4
     134        check_register  x5
     135        check_register  x6
     136        check_register  x7
     137        check_register  x8
     138        check_register  x9
     139        check_register  x10
     140        check_register  x11
     141        check_register  x12
     142        check_register  x13
     143        check_register  x14
     144        check_register  x15
     145        check_register  x16
     146        check_register  x17
     147        check_register  x18
     148        check_register  x19
     149        check_register  x20
     150        check_register  x21
     151        check_register  x22
     152        check_register  x23
     153        check_register  x24
     154        check_register  x25
     155        check_register  x26
     156        check_register  x27
     157        check_register  x28
     158        check_register  x29
     159        check_register  x30
     160        check_register  x31
     161
     162        j       check
     163
     164        /* Restore */
    165165restore:
    166   LREG x1, (1 * CPU_SIZEOF_POINTER)(sp)
    167   /* Skip sp/x2 */
    168   LREG x3, (3 * CPU_SIZEOF_POINTER)(sp)
    169   LREG x4, (4 * CPU_SIZEOF_POINTER)(sp)
    170   LREG x5, (5 * CPU_SIZEOF_POINTER)(sp)
    171   LREG x6, (6 * CPU_SIZEOF_POINTER)(sp)
    172   LREG x7, (7 * CPU_SIZEOF_POINTER)(sp)
    173   LREG x8, (8 * CPU_SIZEOF_POINTER)(sp)
    174   LREG x9, (9 * CPU_SIZEOF_POINTER)(sp)
    175   LREG x10, (10 * CPU_SIZEOF_POINTER)(sp)
    176   LREG x11, (11 * CPU_SIZEOF_POINTER)(sp)
    177   LREG x12, (12 * CPU_SIZEOF_POINTER)(sp)
    178   LREG x13, (13 * CPU_SIZEOF_POINTER)(sp)
    179   LREG x14, (14 * CPU_SIZEOF_POINTER)(sp)
    180   LREG x15, (15 * CPU_SIZEOF_POINTER)(sp)
    181   LREG x16, (16 * CPU_SIZEOF_POINTER)(sp)
    182   LREG x17, (17 * CPU_SIZEOF_POINTER)(sp)
    183   LREG x18, (18 * CPU_SIZEOF_POINTER)(sp)
    184   LREG x19, (19 * CPU_SIZEOF_POINTER)(sp)
    185   LREG x20, (20 * CPU_SIZEOF_POINTER)(sp)
    186   LREG x21, (21 * CPU_SIZEOF_POINTER)(sp)
    187   LREG x22, (22 * CPU_SIZEOF_POINTER)(sp)
    188   LREG x23, (23 * CPU_SIZEOF_POINTER)(sp)
    189   LREG x24, (24 * CPU_SIZEOF_POINTER)(sp)
    190   LREG x25, (25 * CPU_SIZEOF_POINTER)(sp)
    191   LREG x26, (26 * CPU_SIZEOF_POINTER)(sp)
    192   LREG x27, (27 * CPU_SIZEOF_POINTER)(sp)
    193   LREG x28, (28 * CPU_SIZEOF_POINTER)(sp)
    194   LREG x29, (29 * CPU_SIZEOF_POINTER)(sp)
    195   LREG x30, (30 * CPU_SIZEOF_POINTER)(sp)
    196 
    197   LREG x31, (31 * CPU_SIZEOF_POINTER)(sp)
    198 
    199   addi sp, sp, 36 * CPU_SIZEOF_POINTER
    200   ret
     166        LREG    x1, (1 * CPU_SIZEOF_POINTER)(sp)
     167        /* Skip sp/x2 */
     168        LREG    x3, (3 * CPU_SIZEOF_POINTER)(sp)
     169        LREG    x4, (4 * CPU_SIZEOF_POINTER)(sp)
     170        LREG    x5, (5 * CPU_SIZEOF_POINTER)(sp)
     171        LREG    x6, (6 * CPU_SIZEOF_POINTER)(sp)
     172        LREG    x7, (7 * CPU_SIZEOF_POINTER)(sp)
     173        LREG    x8, (8 * CPU_SIZEOF_POINTER)(sp)
     174        LREG    x9, (9 * CPU_SIZEOF_POINTER)(sp)
     175        LREG    x10, (10 * CPU_SIZEOF_POINTER)(sp)
     176        LREG    x11, (11 * CPU_SIZEOF_POINTER)(sp)
     177        LREG    x12, (12 * CPU_SIZEOF_POINTER)(sp)
     178        LREG    x13, (13 * CPU_SIZEOF_POINTER)(sp)
     179        LREG    x14, (14 * CPU_SIZEOF_POINTER)(sp)
     180        LREG    x15, (15 * CPU_SIZEOF_POINTER)(sp)
     181        LREG    x16, (16 * CPU_SIZEOF_POINTER)(sp)
     182        LREG    x17, (17 * CPU_SIZEOF_POINTER)(sp)
     183        LREG    x18, (18 * CPU_SIZEOF_POINTER)(sp)
     184        LREG    x19, (19 * CPU_SIZEOF_POINTER)(sp)
     185        LREG    x20, (20 * CPU_SIZEOF_POINTER)(sp)
     186        LREG    x21, (21 * CPU_SIZEOF_POINTER)(sp)
     187        LREG    x22, (22 * CPU_SIZEOF_POINTER)(sp)
     188        LREG    x23, (23 * CPU_SIZEOF_POINTER)(sp)
     189        LREG    x24, (24 * CPU_SIZEOF_POINTER)(sp)
     190        LREG    x25, (25 * CPU_SIZEOF_POINTER)(sp)
     191        LREG    x26, (26 * CPU_SIZEOF_POINTER)(sp)
     192        LREG    x27, (27 * CPU_SIZEOF_POINTER)(sp)
     193        LREG    x28, (28 * CPU_SIZEOF_POINTER)(sp)
     194        LREG    x29, (29 * CPU_SIZEOF_POINTER)(sp)
     195        LREG    x30, (30 * CPU_SIZEOF_POINTER)(sp)
     196
     197        LREG    x31, (31 * CPU_SIZEOF_POINTER)(sp)
     198
     199        addi    sp, sp, 36 * CPU_SIZEOF_POINTER
     200        ret
  • cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S

    rfef0a41 r52f4fb6  
    3030#include <rtems/asm.h>
    3131
    32 .section .text
     32        .section        .text, "ax", @progbits
     33        .align  2
    3334
    3435PUBLIC(_CPU_Context_volatile_clobber)
    3536SYM(_CPU_Context_volatile_clobber):
    3637
    37   .macro clobber_register reg
    38   addi t0, t0, -1
    39   mv  \reg, t0
    40   .endm
     38        .macro  clobber_register reg
     39        addi    t0, t0, -1
     40        mv      \reg, t0
     41        .endm
    4142
    42   clobber_register  a0
    43   clobber_register  a1
    44   clobber_register  a2
    45   clobber_register  a3
    46   clobber_register  a4
    47   clobber_register  a5
    48   clobber_register  a6
     43        clobber_register        a0
     44        clobber_register        a1
     45        clobber_register        a2
     46        clobber_register        a3
     47        clobber_register        a4
     48        clobber_register        a5
     49        clobber_register        a6
    4950
    50   ret
     51        ret
  • cpukit/score/cpu/riscv/riscv-exception-handler.S

    rfef0a41 r52f4fb6  
    4646PUBLIC(ISR_Handler)
    4747
    48 .section .text, "ax"
    49 .align 4
     48        .section        .text, "ax", @progbits
     49        .align  2
     50
    5051TYPE_FUNC(ISR_Handler)
    5152SYM(ISR_Handler):
    52   addi sp, sp, -1 * 36 * CPU_SIZEOF_POINTER
    53 
    54   SREG x1, (1 * CPU_SIZEOF_POINTER)(sp)
    55   /* Skip x2/sp */
    56   SREG x3, (3 * CPU_SIZEOF_POINTER)(sp)
    57   SREG x4, (4 * CPU_SIZEOF_POINTER)(sp)
    58   SREG x5, (5 * CPU_SIZEOF_POINTER)(sp)
    59   SREG x6, (6 * CPU_SIZEOF_POINTER)(sp)
    60   SREG x7, (7 * CPU_SIZEOF_POINTER)(sp)
    61   SREG x8, (8 * CPU_SIZEOF_POINTER)(sp)
    62   SREG x9, (9 * CPU_SIZEOF_POINTER)(sp)
    63   SREG x10, (10 * CPU_SIZEOF_POINTER)(sp)
    64   SREG x11, (11 * CPU_SIZEOF_POINTER)(sp)
    65   SREG x12, (12 * CPU_SIZEOF_POINTER)(sp)
    66   SREG x13, (13 * CPU_SIZEOF_POINTER)(sp)
    67   SREG x14, (14 * CPU_SIZEOF_POINTER)(sp)
    68   SREG x15, (15 * CPU_SIZEOF_POINTER)(sp)
    69   SREG x16, (16 * CPU_SIZEOF_POINTER)(sp)
    70   SREG x17, (17 * CPU_SIZEOF_POINTER)(sp)
    71   SREG x18, (18 * CPU_SIZEOF_POINTER)(sp)
    72   SREG x19, (19 * CPU_SIZEOF_POINTER)(sp)
    73   SREG x20, (20 * CPU_SIZEOF_POINTER)(sp)
    74   SREG x21, (21 * CPU_SIZEOF_POINTER)(sp)
    75   SREG x22, (22 * CPU_SIZEOF_POINTER)(sp)
    76   SREG x23, (23 * CPU_SIZEOF_POINTER)(sp)
    77   SREG x24, (24 * CPU_SIZEOF_POINTER)(sp)
    78   SREG x25, (25 * CPU_SIZEOF_POINTER)(sp)
    79   SREG x26, (26 * CPU_SIZEOF_POINTER)(sp)
    80   SREG x27, (27 * CPU_SIZEOF_POINTER)(sp)
    81   SREG x28, (28 * CPU_SIZEOF_POINTER)(sp)
    82   SREG x29, (28 * CPU_SIZEOF_POINTER)(sp)
    83   SREG x30, (30 * CPU_SIZEOF_POINTER)(sp)
    84   SREG x31, (31 * CPU_SIZEOF_POINTER)(sp)
    85 
    86   /* Exception level related registers */
    87   csrr a0, mstatus
    88   SREG a0, (32 * CPU_SIZEOF_POINTER)(sp)
    89   csrr a0, mcause
    90   SREG a0, (33 * CPU_SIZEOF_POINTER)(sp)
    91   csrr a1, mepc
    92   SREG a1, (34 * CPU_SIZEOF_POINTER)(sp)
    93 
    94   /* FIXME Only handle interrupts for now (MSB = 1) */
    95   andi a0, a0, 0xf
    96 
    97   /* Increment nesting level */
    98   la t0, ISR_NEST_LEVEL
    99 
    100   /* Disable multitasking */
    101   la t1, THREAD_DISPATCH_DISABLE_LEVEL
    102 
    103   lw t2, (t0)
    104   lw t3, (t1)
    105   addi t2, t2, 1
    106   addi t3, t3, 1
    107   sw t2, (t0)
    108   sw t3, (t1)
    109 
    110   /* Save interrupted task stack pointer */
    111   addi t4, sp, 36 * CPU_SIZEOF_POINTER
    112   SREG t4, (2 * CPU_SIZEOF_POINTER)(sp)
    113 
    114   /* Keep sp (Exception frame address) in s1 */
    115   mv   s1, sp
    116 
    117   /* Call the exception handler from vector table */
    118 
    119   /* First function arg for C handler is vector number,
    120    * and the second is a pointer to exception frame.
    121    * a0/mcause/vector number is already loaded above */
    122   mv a1, sp
    123 
    124   /* calculate the offset */
    125   la   t5, bsp_start_vector_table_begin
    126 #if __riscv_xlen == 32
    127   slli t6, a0, 2
    128 #else /* xlen = 64 */
    129   slli t6, a0, 3
     53        addi    sp, sp, -1 * 36 * CPU_SIZEOF_POINTER
     54
     55        SREG    x1, (1 * CPU_SIZEOF_POINTER)(sp)
     56        /* Skip x2/sp */
     57        SREG    x3, (3 * CPU_SIZEOF_POINTER)(sp)
     58        SREG    x4, (4 * CPU_SIZEOF_POINTER)(sp)
     59        SREG    x5, (5 * CPU_SIZEOF_POINTER)(sp)
     60        SREG    x6, (6 * CPU_SIZEOF_POINTER)(sp)
     61        SREG    x7, (7 * CPU_SIZEOF_POINTER)(sp)
     62        SREG    x8, (8 * CPU_SIZEOF_POINTER)(sp)
     63        SREG    x9, (9 * CPU_SIZEOF_POINTER)(sp)
     64        SREG    x10, (10 * CPU_SIZEOF_POINTER)(sp)
     65        SREG    x11, (11 * CPU_SIZEOF_POINTER)(sp)
     66        SREG    x12, (12 * CPU_SIZEOF_POINTER)(sp)
     67        SREG    x13, (13 * CPU_SIZEOF_POINTER)(sp)
     68        SREG    x14, (14 * CPU_SIZEOF_POINTER)(sp)
     69        SREG    x15, (15 * CPU_SIZEOF_POINTER)(sp)
     70        SREG    x16, (16 * CPU_SIZEOF_POINTER)(sp)
     71        SREG    x17, (17 * CPU_SIZEOF_POINTER)(sp)
     72        SREG    x18, (18 * CPU_SIZEOF_POINTER)(sp)
     73        SREG    x19, (19 * CPU_SIZEOF_POINTER)(sp)
     74        SREG    x20, (20 * CPU_SIZEOF_POINTER)(sp)
     75        SREG    x21, (21 * CPU_SIZEOF_POINTER)(sp)
     76        SREG    x22, (22 * CPU_SIZEOF_POINTER)(sp)
     77        SREG    x23, (23 * CPU_SIZEOF_POINTER)(sp)
     78        SREG    x24, (24 * CPU_SIZEOF_POINTER)(sp)
     79        SREG    x25, (25 * CPU_SIZEOF_POINTER)(sp)
     80        SREG    x26, (26 * CPU_SIZEOF_POINTER)(sp)
     81        SREG    x27, (27 * CPU_SIZEOF_POINTER)(sp)
     82        SREG    x28, (28 * CPU_SIZEOF_POINTER)(sp)
     83        SREG    x29, (28 * CPU_SIZEOF_POINTER)(sp)
     84        SREG    x30, (30 * CPU_SIZEOF_POINTER)(sp)
     85        SREG    x31, (31 * CPU_SIZEOF_POINTER)(sp)
     86
     87        /* Exception level related registers */
     88        csrr    a0, mstatus
     89        SREG    a0, (32 * CPU_SIZEOF_POINTER)(sp)
     90        csrr    a0, mcause
     91        SREG    a0, (33 * CPU_SIZEOF_POINTER)(sp)
     92        csrr    a1, mepc
     93        SREG    a1, (34 * CPU_SIZEOF_POINTER)(sp)
     94
     95        /* FIXME Only handle interrupts for now (MSB = 1) */
     96        andi    a0, a0, 0xf
     97
     98        /* Increment nesting level */
     99        la      t0, ISR_NEST_LEVEL
     100
     101        /* Disable multitasking */
     102        la      t1, THREAD_DISPATCH_DISABLE_LEVEL
     103
     104        lw      t2, (t0)
     105        lw      t3, (t1)
     106        addi    t2, t2, 1
     107        addi    t3, t3, 1
     108        sw      t2, (t0)
     109        sw      t3, (t1)
     110
     111        /* Save interrupted task stack pointer */
     112        addi    t4, sp, 36 * CPU_SIZEOF_POINTER
     113        SREG    t4, (2 * CPU_SIZEOF_POINTER)(sp)
     114
     115        /* Keep sp (Exception frame address) in s1 */
     116        mv      s1, sp
     117
     118        /* Call the exception handler from vector table */
     119
     120        /* First function arg for C handler is vector number,
     121                * and the second is a pointer to exception frame.
     122                * a0/mcause/vector number is already loaded above */
     123        mv      a1, sp
     124
     125        /* calculate the offset */
     126        la      t5, bsp_start_vector_table_begin
     127#if     __riscv_xlen == 32
     128        slli    t6, a0, 2
     129#else   /* xlen = 64 */
     130        slli    t6, a0, 3
    130131#endif
    131   add  t5, t5, t6
    132   LREG t5, (t5)
    133 
    134   /* Do not switch stacks if we are in a nested interrupt. At
    135    * this point t2 should be holding ISR_NEST_LEVEL value.
    136    */
    137   li   s0, 1
    138   bgtu t2, s0, jump_to_c_handler
    139 
    140   /* Switch to RTEMS dedicated interrupt stack */
    141   la     sp, INTERRUPT_STACK_HIGH
    142   LREG   sp, (sp)
     132        add     t5, t5, t6
     133        LREG    t5, (t5)
     134
     135        /* Do not switch stacks if we are in a nested interrupt. At
     136                * this point t2 should be holding ISR_NEST_LEVEL value.
     137                */
     138        li      s0, 1
     139        bgtu    t2, s0, jump_to_c_handler
     140
     141        /* Switch to RTEMS dedicated interrupt stack */
     142        la      sp, INTERRUPT_STACK_HIGH
     143        LREG    sp, (sp)
    143144
    144145jump_to_c_handler:
    145   jalr t5
    146 
    147   /* Switch back to the interrupted task stack */
    148   mv sp, s1
    149 
    150   /* Decrement nesting level */
    151   la t0, ISR_NEST_LEVEL
    152 
    153   /* Enable multitasking */
    154   la t1, THREAD_DISPATCH_DISABLE_LEVEL
    155 
    156   Lw t2, (t0)
    157   lw t3, (t1)
    158   addi t2, t2, -1
    159   addi t3, t3, -1
    160   sw t2, (t0)
    161   sw t3, (t1)
    162 
    163   /* Check if _ISR_Nest_level > 0 */
    164   bgtz t2, exception_frame_restore
    165 
    166   /* Check if _Thread_Dispatch_disable_level > 0 */
    167   bgtz t3, exception_frame_restore
    168 
    169   /* Check if dispatch needed */
    170   la   x31, DISPATCH_NEEDED
    171   lw x31, (x31)
    172   beqz x31, exception_frame_restore
    173 
    174   la x31, _Thread_Dispatch
    175   jalr x31
    176 
    177   SYM(exception_frame_restore):
    178   LREG x1, (1 * CPU_SIZEOF_POINTER)(sp)
    179   /* Skip sp/x2 */
    180   LREG x3, (3 * CPU_SIZEOF_POINTER)(sp)
    181   LREG x4, (4 * CPU_SIZEOF_POINTER)(sp)
    182   LREG x5, (5 * CPU_SIZEOF_POINTER)(sp)
    183   LREG x6, (6 * CPU_SIZEOF_POINTER)(sp)
    184   LREG x7, (7 * CPU_SIZEOF_POINTER)(sp)
    185   LREG x8, (8 * CPU_SIZEOF_POINTER)(sp)
    186   LREG x9, (9 * CPU_SIZEOF_POINTER)(sp)
    187   LREG x10, (10 * CPU_SIZEOF_POINTER)(sp)
    188   LREG x11, (11 * CPU_SIZEOF_POINTER)(sp)
    189   LREG x12, (12 * CPU_SIZEOF_POINTER)(sp)
    190   LREG x13, (13 * CPU_SIZEOF_POINTER)(sp)
    191   LREG x14, (14 * CPU_SIZEOF_POINTER)(sp)
    192   LREG x15, (15 * CPU_SIZEOF_POINTER)(sp)
    193   LREG x16, (16 * CPU_SIZEOF_POINTER)(sp)
    194   LREG x17, (17 * CPU_SIZEOF_POINTER)(sp)
    195   LREG x18, (18 * CPU_SIZEOF_POINTER)(sp)
    196   LREG x19, (19 * CPU_SIZEOF_POINTER)(sp)
    197   LREG x20, (20 * CPU_SIZEOF_POINTER)(sp)
    198   LREG x21, (21 * CPU_SIZEOF_POINTER)(sp)
    199   LREG x22, (22 * CPU_SIZEOF_POINTER)(sp)
    200   LREG x23, (23 * CPU_SIZEOF_POINTER)(sp)
    201   LREG x24, (24 * CPU_SIZEOF_POINTER)(sp)
    202   LREG x25, (25 * CPU_SIZEOF_POINTER)(sp)
    203   LREG x26, (26 * CPU_SIZEOF_POINTER)(sp)
    204   LREG x27, (27 * CPU_SIZEOF_POINTER)(sp)
    205   LREG x28, (28 * CPU_SIZEOF_POINTER)(sp)
    206   LREG x29, (29 * CPU_SIZEOF_POINTER)(sp)
    207   LREG x30, (30 * CPU_SIZEOF_POINTER)(sp)
    208 
    209   /* Load mstatus */
    210   LREG x31, (32 * CPU_SIZEOF_POINTER)(sp)
    211   csrw mstatus, x31
    212   /* Load mepc */
    213   LREG x31, (34 * CPU_SIZEOF_POINTER)(sp)
    214   csrw mepc, x31
    215 
    216   LREG x31, (31 * CPU_SIZEOF_POINTER)(sp)
    217 
    218   /* Unwind exception frame */
    219   addi sp, sp, 36 * CPU_SIZEOF_POINTER
    220 
    221   mret
     146        jalr    t5
     147
     148        /* Switch back to the interrupted task stack */
     149        mv      sp, s1
     150
     151        /* Decrement nesting level */
     152        la      t0, ISR_NEST_LEVEL
     153
     154        /* Enable multitasking */
     155        la      t1, THREAD_DISPATCH_DISABLE_LEVEL
     156
     157        Lw      t2, (t0)
     158        lw      t3, (t1)
     159        addi    t2, t2, -1
     160        addi    t3, t3, -1
     161        sw      t2, (t0)
     162        sw      t3, (t1)
     163
     164        /* Check if _ISR_Nest_level > 0 */
     165        bgtz    t2, exception_frame_restore
     166
     167        /* Check if _Thread_Dispatch_disable_level > 0 */
     168        bgtz    t3, exception_frame_restore
     169
     170        /* Check if dispatch needed */
     171        la      x31, DISPATCH_NEEDED
     172        lw      x31, (x31)
     173        beqz    x31, exception_frame_restore
     174
     175        la      x31, _Thread_Dispatch
     176        jalr    x31
     177
     178        SYM(exception_frame_restore):
     179        LREG    x1, (1 * CPU_SIZEOF_POINTER)(sp)
     180        /* Skip sp/x2 */
     181        LREG    x3, (3 * CPU_SIZEOF_POINTER)(sp)
     182        LREG    x4, (4 * CPU_SIZEOF_POINTER)(sp)
     183        LREG    x5, (5 * CPU_SIZEOF_POINTER)(sp)
     184        LREG    x6, (6 * CPU_SIZEOF_POINTER)(sp)
     185        LREG    x7, (7 * CPU_SIZEOF_POINTER)(sp)
     186        LREG    x8, (8 * CPU_SIZEOF_POINTER)(sp)
     187        LREG    x9, (9 * CPU_SIZEOF_POINTER)(sp)
     188        LREG    x10, (10 * CPU_SIZEOF_POINTER)(sp)
     189        LREG    x11, (11 * CPU_SIZEOF_POINTER)(sp)
     190        LREG    x12, (12 * CPU_SIZEOF_POINTER)(sp)
     191        LREG    x13, (13 * CPU_SIZEOF_POINTER)(sp)
     192        LREG    x14, (14 * CPU_SIZEOF_POINTER)(sp)
     193        LREG    x15, (15 * CPU_SIZEOF_POINTER)(sp)
     194        LREG    x16, (16 * CPU_SIZEOF_POINTER)(sp)
     195        LREG    x17, (17 * CPU_SIZEOF_POINTER)(sp)
     196        LREG    x18, (18 * CPU_SIZEOF_POINTER)(sp)
     197        LREG    x19, (19 * CPU_SIZEOF_POINTER)(sp)
     198        LREG    x20, (20 * CPU_SIZEOF_POINTER)(sp)
     199        LREG    x21, (21 * CPU_SIZEOF_POINTER)(sp)
     200        LREG    x22, (22 * CPU_SIZEOF_POINTER)(sp)
     201        LREG    x23, (23 * CPU_SIZEOF_POINTER)(sp)
     202        LREG    x24, (24 * CPU_SIZEOF_POINTER)(sp)
     203        LREG    x25, (25 * CPU_SIZEOF_POINTER)(sp)
     204        LREG    x26, (26 * CPU_SIZEOF_POINTER)(sp)
     205        LREG    x27, (27 * CPU_SIZEOF_POINTER)(sp)
     206        LREG    x28, (28 * CPU_SIZEOF_POINTER)(sp)
     207        LREG    x29, (29 * CPU_SIZEOF_POINTER)(sp)
     208        LREG    x30, (30 * CPU_SIZEOF_POINTER)(sp)
     209
     210        /* Load mstatus */
     211        LREG    x31, (32 * CPU_SIZEOF_POINTER)(sp)
     212        csrw    mstatus, x31
     213        /* Load mepc */
     214        LREG    x31, (34 * CPU_SIZEOF_POINTER)(sp)
     215        csrw    mepc, x31
     216
     217        LREG    x31, (31 * CPU_SIZEOF_POINTER)(sp)
     218
     219        /* Unwind exception frame */
     220        addi    sp, sp, 36 * CPU_SIZEOF_POINTER
     221
     222        mret
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