Changeset 52d24b00 in rtems
- Timestamp:
- 11/19/14 13:29:27 (9 years ago)
- Branches:
- 4.11, 5, master
- Children:
- e492e7f8
- Parents:
- 55741886
- git-author:
- Sebastian Huber <sebastian.huber@…> (11/19/14 13:29:27)
- git-committer:
- Sebastian Huber <sebastian.huber@…> (11/20/14 09:30:28)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
r55741886 r52d24b00 91 91 92 92 /* RTL release number as can be read from cache_id register */ 93 typedef enum { 94 L2C_310_RTL_RELEASE_R0_P0 = 0x0, 95 L2C_310_RTL_RELEASE_R1_P0 = 0x2, 96 L2C_310_RTL_RELEASE_R2_P0 = 0x4, 97 L2C_310_RTL_RELEASE_R3_P0 = 0x5, 98 L2C_310_RTL_RELEASE_R3_P1 = 0x6, 99 L2C_310_RTL_RELEASE_R3_P2 = 0x8, 100 L2C_310_RTL_RELEASE_R3_P3 = 0x9 101 } l2c_310_rtl_release; 93 #define L2C_310_RTL_RELEASE_R0_P0 0x0 94 #define L2C_310_RTL_RELEASE_R1_P0 0x2 95 #define L2C_310_RTL_RELEASE_R2_P0 0x4 96 #define L2C_310_RTL_RELEASE_R3_P0 0x5 97 #define L2C_310_RTL_RELEASE_R3_P1 0x6 98 #define L2C_310_RTL_RELEASE_R3_P2 0x8 99 #define L2C_310_RTL_RELEASE_R3_P3 0x9 100 101 #define BSP_ARM_L2C_310_RTL_RELEASE (BSP_ARM_L2C_310_ID & L2C_310_ID_RTL_MASK) 102 102 103 103 /** … … 480 480 * r3 releases Software Developers Errata Notice" 481 481 * Please see this document for more information on these erratas */ 482 static bool l2c_310_errata_is_applicable_753970( 483 l2c_310_rtl_release rtl_release 482 #if BSP_ARM_L2C_310_RTL_RELEASE == L2C_310_RTL_RELEASE_R3_P0 483 #define L2C_310_ERRATA_IS_APPLICABLE_753970 484 #endif 485 486 static bool l2c_310_errata_is_applicable_727913( 487 uint32_t rtl_release 484 488 ) 485 489 { … … 506 510 } 507 511 508 static bool l2c_310_errata_is_applicable_72791 3(509 l2c_310_rtl_releasertl_release512 static bool l2c_310_errata_is_applicable_727914( 513 uint32_t rtl_release 510 514 ) 511 515 { … … 532 536 } 533 537 534 static bool l2c_310_errata_is_applicable_727914(535 l2c_310_rtl_release rtl_release536 )537 {538 bool is_applicable = false;539 540 switch ( rtl_release ) {541 case L2C_310_RTL_RELEASE_R3_P3:542 case L2C_310_RTL_RELEASE_R3_P2:543 case L2C_310_RTL_RELEASE_R3_P1:544 case L2C_310_RTL_RELEASE_R2_P0:545 case L2C_310_RTL_RELEASE_R1_P0:546 case L2C_310_RTL_RELEASE_R0_P0:547 is_applicable = false;548 break;549 case L2C_310_RTL_RELEASE_R3_P0:550 is_applicable = true;551 break;552 default:553 assert( 0 );554 break;555 }556 557 return is_applicable;558 }559 560 538 static bool l2c_310_errata_is_applicable_727915( 561 l2c_310_rtl_releasertl_release539 uint32_t rtl_release 562 540 ) 563 541 { … … 585 563 586 564 static bool l2c_310_errata_is_applicable_729806( 587 l2c_310_rtl_releasertl_release565 uint32_t rtl_release 588 566 ) 589 567 { … … 611 589 612 590 static bool l2c_310_errata_is_applicable_729815( 613 l2c_310_rtl_releasertl_release591 uint32_t rtl_release 614 592 ) 615 593 { … … 637 615 638 616 static bool l2c_310_errata_is_applicable_742884( 639 l2c_310_rtl_releasertl_release617 uint32_t rtl_release 640 618 ) 641 619 { … … 663 641 664 642 static bool l2c_310_errata_is_applicable_752271( 665 l2c_310_rtl_releasertl_release643 uint32_t rtl_release 666 644 ) 667 645 { … … 689 667 690 668 static bool l2c_310_errata_is_applicable_765569( 691 l2c_310_rtl_releasertl_release669 uint32_t rtl_release 692 670 ) 693 671 { … … 713 691 714 692 static bool l2c_310_errata_is_applicable_769419( 715 l2c_310_rtl_releasertl_release693 uint32_t rtl_release 716 694 ) 717 695 { … … 739 717 740 718 static bool l2c_310_errata_is_applicable_588369( 741 l2c_310_rtl_releasertl_release719 uint32_t rtl_release 742 720 ) 743 721 { … … 766 744 #ifdef CACHE_ERRATA_CHECKS_FOR_IMPLEMENTED_ERRATAS 767 745 static bool l2c_310_errata_is_applicable_754670( 768 l2c_310_rtl_releasertl_release746 uint32_t rtl_release 769 747 ) 770 748 { … … 798 776 } \ 799 777 800 static void l2c_310_check_errata( l2c_310_rtl_releasertl_release )778 static void l2c_310_check_errata( uint32_t rtl_release ) 801 779 { 802 780 /* This erratum gets handled within the sources */ … … 887 865 888 866 static inline void 889 l2c_310_sync( void ) 890 { 891 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 892 l2c_310_rtl_release rtl_release = 893 l2cc->cache_id & L2C_310_ID_RTL_MASK; 894 895 if( l2c_310_errata_is_applicable_753970( rtl_release ) ) { 896 l2cc->dummy_cache_sync_reg = 0; 897 } else { 898 l2cc->cache_sync = 0; 899 } 867 l2c_310_sync( volatile L2CC *l2cc ) 868 { 869 #ifdef L2C_310_ERRATA_IS_APPLICABLE_753970 870 l2cc->dummy_cache_sync_reg = 0; 871 #else 872 l2cc->cache_sync = 0; 873 #endif 900 874 } 901 875 … … 916 890 */ 917 891 l2cc->clean_pa = (uint32_t) d_addr; 918 l2c_310_sync( );892 l2c_310_sync( l2cc ); 919 893 l2cc->inv_pa = (uint32_t) d_addr; 920 894 } else { … … 935 909 L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES ); 936 910 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 937 l2c_310_rtl_releasertl_release =911 uint32_t rtl_release = 938 912 l2cc->cache_id & L2C_310_ID_RTL_MASK; 939 913 bool is_errata_588369_applicable = … … 954 928 } 955 929 } 956 l2c_310_sync( );930 l2c_310_sync( l2cc ); 957 931 rtems_interrupt_lock_release( &l2c_310_lock, &lock_context ); 958 932 } … … 976 950 977 951 /* Wait for the flush to complete */ 978 l2c_310_sync( );952 l2c_310_sync( l2cc ); 979 953 980 954 rtems_interrupt_lock_release( &l2c_310_lock, &lock_context ); … … 989 963 990 964 l2cc->inv_pa = (uint32_t) d_addr; 991 l2c_310_sync( );965 l2c_310_sync( l2cc ); 992 966 } 993 967 … … 1005 979 l2cc->inv_pa = adx; 1006 980 } 1007 l2c_310_sync( );981 l2c_310_sync( l2cc ); 1008 982 rtems_interrupt_lock_release( &l2c_310_lock, &lock_context ); 1009 983 } … … 1024 998 1025 999 /* Wait for the invalidate to complete */ 1026 l2c_310_sync( );1000 l2c_310_sync( l2cc ); 1027 1001 } 1028 1002 … … 1045 1019 1046 1020 /* Wait for the invalidate to complete */ 1047 l2c_310_sync( );1021 l2c_310_sync( l2cc ); 1048 1022 1049 1023 rtems_interrupt_lock_release( &l2c_310_lock, &lock_context ); … … 1141 1115 #endif 1142 1116 1143 #if ( (BSP_ARM_L2C_310_ID & L2C_310_ID_RTL_MASK) != 0x8) \1144 && ( (BSP_ARM_L2C_310_ID & L2C_310_ID_RTL_MASK) != 0x9)1117 #if (BSP_ARM_L2C_310_RTL_RELEASE != L2C_310_RTL_RELEASE_R3_P2) \ 1118 && (BSP_ARM_L2C_310_RTL_RELEASE != L2C_310_RTL_RELEASE_R3_P3) 1145 1119 #error "invalid L2-310 cache controller RTL revision" 1146 1120 #endif … … 1151 1125 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 1152 1126 uint32_t cache_id = l2cc->cache_id; 1153 l2c_310_rtl_release rtl_release = 1154 cache_id & L2C_310_ID_RTL_MASK; 1155 uint32_t id_mask = 1156 L2C_310_ID_IMPL_MASK | L2C_310_ID_PART_MASK; 1127 uint32_t rtl_release = cache_id & L2C_310_ID_RTL_MASK; 1128 uint32_t id_mask = L2C_310_ID_IMPL_MASK | L2C_310_ID_PART_MASK; 1157 1129 uint32_t ctrl; 1158 1130 … … 1163 1135 if ( 1164 1136 (BSP_ARM_L2C_310_ID & id_mask) != (cache_id & id_mask) 1165 || rtl_release < (BSP_ARM_L2C_310_ID & L2C_310_ID_RTL_MASK)1137 || rtl_release < BSP_ARM_L2C_310_RTL_RELEASE 1166 1138 ) { 1167 1139 bsp_fatal( ARM_FATAL_L2C_310_UNEXPECTED_ID );
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