Changeset 52c5689e in rtems


Ignore:
Timestamp:
Jul 31, 2002, 12:16:04 AM (17 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
0b93b978
Parents:
219432f
Message:

2002-07-30 Joel Sherrill <joel@…>

  • .cvsignore: Corrected some errors.
  • intr_NOTIMES.t, timeBSP.t: Replaced XXX's with real info.
Location:
doc/supplements/mips
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • doc/supplements/mips/.cvsignore

    r219432f r52c5689e  
    66cputable.texi
    77fatalerr.texi
    8 i386
    9 i386*.html
    10 i386-?
    11 i386-??
    12 i386.aux
    13 i386.cp
    14 i386.dvi
    15 i386.fn
    16 i386.ky
    17 i386.log
    18 i386.pdf
    19 i386.pg
    20 i386.ps
    21 i386.toc
    22 i386.tp
    23 i386.vr
     8mips
     9mips*.html
     10mips-?
     11mips-??
     12mips.aux
     13mips.cp
     14mips.dvi
     15mips.fn
     16mips.ky
     17mips.log
     18mips.pdf
     19mips.pg
     20mips.ps
     21mips.toc
     22mips.tp
     23mips.vr
    2424index.html
    2525intr.t
     
    2727mdate-sh
    2828memmodel.texi
    29 timeFORCE386.texi
    30 timeFORCE386_.t
     29timeBSP_.t
     30timeBSP.texi
    3131timing.t
    3232timing.texi
  • doc/supplements/mips/ChangeLog

    r219432f r52c5689e  
     12002-07-30      Joel Sherrill <joel@OARcorp.com>
     2
     3        * .cvsignore: Corrected some errors.
     4        * intr_NOTIMES.t, timeBSP.t: Replaced XXX's with real info.
     5
    162002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    27
  • doc/supplements/mips/intr_NOTIMES.t

    r219432f r52c5689e  
    168168to insure that interrupts are disabled for less than
    169169RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a
    170 RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz XXX with
     170RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz processor with
    171171zero wait states.  These numbers will vary based the
    172172number of wait states and processor speed present on the target board.
     
    190190process, RTEMS will install its interrupt stack.
    191191
    192 The XXX port of RTEMS supports a software managed
     192The mips port of RTEMS supports a software managed
    193193dedicated interrupt stack on those CPU models which do not
    194194support a separate interrupt stack in hardware.
  • doc/supplements/mips/timeBSP.t

    r219432f r52c5689e  
    1616@section Introduction
    1717
    18 The timing data for the XXX version of RTEMS is
     18The timing data for the MIPS version of RTEMS is
    1919provided along with the target dependent aspects concerning the
    2020gathering of the timing data.  The hardware platform used to
     
    2222understanding of each directive time provided.  Also, provided
    2323is a description of the interrupt latency and the context switch
    24 times as they pertain to the XXX version of RTEMS.
     24times as they pertain to the MIPS version of RTEMS.
    2525
    2626@section Hardware Platform
     
    2828All times reported except for the maximum period
    2929interrupts are disabled by RTEMS were measured using a Motorola
    30 BSP_FOR_TIMES CPU board.  The BSP_FOR_TIMES is a 20Mhz board with one wait
     30BSP_FOR_TIMES CPU board.  The BSP_FOR_TIMES is a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
     31Mhz board with one wait
    3132state dynamic memory and a XXX numeric coprocessor.  The
    3233Zilog 8036 countdown timer on this board was used to measure
     
    4243assumed.  The total CPU cycles executed with interrupts
    4344disabled, including the instructions to disable and enable
    44 interrupts, was divided by 20 to simulate a 20Mhz XXX.  It
     45interrupts, was divided by 20 to simulate a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
     46Mhz processor.  It
    4547should be noted that the worst case instruction times for the
    4648XXX assume that the internal cache is disabled and that no
     
    5961interrupt latency of less than
    6062RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
    61 microseconds at 20Mhz.  [NOTE:  The maximum period with interrupts
     63microseconds at RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
     64Mhz.  [NOTE:  The maximum period with interrupts
    6265disabled was last determined for Release
    6366RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
     
    6669interrupts disabled within RTEMS is hand-timed and based upon
    6770worst case (i.e. CPU cache disabled and no instruction overlap)
    68 times for a 20Mhz XXX.  The interrupt vector and entry
     71times for a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
     72Mhz processor.  The interrupt vector and entry
    6973overhead time was generated on an BSP_FOR_TIMES benchmark platform
    7074using the Multiprocessing Communications registers to generate
     
    9498
    9599The exact amount of time required to save and restore
    96 floating point context is dependent on whether an XXX or
    97 XXX is being used as well as the state of the numeric
     100floating point context is dependent which FPU is being
     101used as well as the state of the numeric
    98102coprocessor.  These numeric coprocessors define three operating
    99103states: initialized, idle, and busy.  RTEMS places the
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