Index: c/src/lib/libbsp/i386/shared/comm/i386_io.h
===================================================================
--- c/src/lib/libbsp/i386/shared/comm/i386_io.h	(revision 9dc999af0107998037d55ddfc2d83b6b53383e64)
+++ c/src/lib/libbsp/i386/shared/comm/i386_io.h	(revision 52943a24710905392c7d4375b204e36bcdd514d7)
@@ -1,2 +1,8 @@
+/**
+ * @file
+ * @ingroup i386_io
+ * @brief I/O
+ */
+
 /*
  * Copyright (c) 2000 - Rosimildo da Silva.  All Rights Reserved.
@@ -9,4 +15,11 @@
  *  by: Rosimildo da Silva:  rdasilva@connecttel.com
  *
+ */
+
+/**
+ * @defgroup i386_io I/O
+ * @ingroup i386_comm
+ * @brief I/O
+ * @{
  */
 
@@ -57,2 +70,4 @@
 
 #endif /* i386_io_h__ */
+
+/** @} */
Index: c/src/lib/libbsp/i386/shared/comm/tty_drv.h
===================================================================
--- c/src/lib/libbsp/i386/shared/comm/tty_drv.h	(revision 9dc999af0107998037d55ddfc2d83b6b53383e64)
+++ c/src/lib/libbsp/i386/shared/comm/tty_drv.h	(revision 52943a24710905392c7d4375b204e36bcdd514d7)
@@ -1,2 +1,8 @@
+/**
+ * @file
+ * @ingroup i386_tty
+ * @brief ttySx driver
+ */
+
 #ifndef __tty_drv__
 #define __tty_drv__
@@ -13,4 +19,10 @@
  ****************************************************************************/
 
+/**
+ * @defgroup i386_tty ttSx
+ * @ingroup i386_comm
+ * @brief i386 tySx driver
+ * @{
+ */
 
 /* functions */
@@ -19,5 +31,5 @@
 #endif
 
-/* ttyS1 entry points */
+/** @brief ttyS1 entry points */
 rtems_device_driver tty1_initialize(
   rtems_device_major_number,
@@ -38,5 +50,5 @@
 );
 
-/* tty1 & tty2 shared entry points */
+/** @brief tty1 & tty2 shared entry points */
 rtems_device_driver tty_close(
   rtems_device_major_number,
@@ -57,5 +69,5 @@
 );
 
-/* tty2 entry points */
+/** @brief tty2 entry points */
 rtems_device_driver tty2_initialize(
   rtems_device_major_number,
@@ -84,4 +96,6 @@
     tty_read, tty_write, tty2_control }
 
+/** @} */
+
 #ifdef __cplusplus
 }
Index: c/src/lib/libbsp/i386/shared/comm/uart.h
===================================================================
--- c/src/lib/libbsp/i386/shared/comm/uart.h	(revision 9dc999af0107998037d55ddfc2d83b6b53383e64)
+++ c/src/lib/libbsp/i386/shared/comm/uart.h	(revision 52943a24710905392c7d4375b204e36bcdd514d7)
@@ -1,2 +1,8 @@
+/**
+ * @file
+ * @ingroup i386_uart
+ * @brief i386 UART definitions
+ */
+
 /*
  * This software is Copyright (C) 1998 by T.sqware - all rights limited
@@ -4,4 +10,11 @@
  * as far as this copyight notice is kept unchanged, but does not imply
  * an endorsement by T.sqware of the product in which it is included.
+ */
+
+/**
+ * @defgroup i386_uart UART
+ * @ingroup i386_comm
+ * @brief i386 UART definitions
+ * @{
  */
 
@@ -35,5 +48,6 @@
 extern int BSPConsolePort;
 extern int BSPBaseBaud;
-/*
+
+/** @brief
  * Command values for BSP_uart_intr_ctrl(),
  * values are strange in order to catch errors
@@ -41,19 +55,19 @@
  */
 #define BSP_UART_INTR_CTRL_DISABLE  (0)
-#define BSP_UART_INTR_CTRL_GDB      (0xaa) /* RX only */
-#define BSP_UART_INTR_CTRL_ENABLE   (0xbb) /* Normal operations */
-#define BSP_UART_INTR_CTRL_TERMIOS  (0xcc) /* RX & line status */
+#define BSP_UART_INTR_CTRL_GDB      (0xaa) ///< RX only
+#define BSP_UART_INTR_CTRL_ENABLE   (0xbb) ///< Normal operations
+#define BSP_UART_INTR_CTRL_TERMIOS  (0xcc) ///< RX & line status
 
-/* Return values for uart_polled_status() */
-#define BSP_UART_STATUS_ERROR    (-1) /* No character */
-#define BSP_UART_STATUS_NOCHAR   (0)  /* No character */
-#define BSP_UART_STATUS_CHAR     (1)  /* Character present */
-#define BSP_UART_STATUS_BREAK    (2)  /* Break point is detected */
+/** @brief Return values for uart_polled_status() */
+#define BSP_UART_STATUS_ERROR    (-1) ///< No character
+#define BSP_UART_STATUS_NOCHAR   (0)  ///< No character
+#define BSP_UART_STATUS_CHAR     (1)  ///< Character present
+#define BSP_UART_STATUS_BREAK    (2)  ///< Break point is detected
 
-/* PC UART definitions */
+/** @brief PC UART definitions */
 #define BSP_UART_COM1            (0)
 #define BSP_UART_COM2            (1)
 
-/*
+/** @brief
  * Base IO for UART
  */
@@ -62,28 +76,28 @@
 #define COM2_BASE_IO	0x2F8
 
-/*
+/** @brief
  * Offsets from base
  */
 
-/* DLAB 0 */
-#define RBR  (0)    /* Rx Buffer Register (read) */
-#define THR  (0)    /* Tx Buffer Register (write) */
-#define IER  (1)    /* Interrupt Enable Register */
+/** @brief DLAB 0 */
+#define RBR  (0)    ///< Rx Buffer Register (read)
+#define THR  (0)    ///< Tx Buffer Register (write)
+#define IER  (1)    ///< Interrupt Enable Register
 
-/* DLAB X */
-#define IIR  (2)    /* Interrupt Ident Register (read) */
-#define FCR  (2)    /* FIFO Control Register (write) */
-#define LCR  (3)    /* Line Control Register */
-#define MCR  (4)    /* Modem Control Register */
-#define LSR  (5)    /* Line Status Register */
-#define MSR  (6)    /* Modem Status  Register */
-#define SCR  (7)    /* Scratch register */
+/** @brief DLAB X */
+#define IIR  (2)    ///< Interrupt Ident Register (read)
+#define FCR  (2)    ///< FIFO Control Register (write)
+#define LCR  (3)    ///< Line Control Register
+#define MCR  (4)    ///< Modem Control Register
+#define LSR  (5)    ///< Line Status Register
+#define MSR  (6)    ///< Modem Status  Register
+#define SCR  (7)    ///< Scratch register
 
-/* DLAB 1 */
-#define DLL  (0)    /* Divisor Latch, LSB */
-#define DLM  (1)    /* Divisor Latch, MSB */
-#define AFR  (2)    /* Alternate Function register */
+/** @brief DLAB 1 */
+#define DLL  (0)    ///< Divisor Latch, LSB
+#define DLM  (1)    ///< Divisor Latch, MSB
+#define AFR  (2)    ///< Alternate Function register
 
-/*
+/** @brief
  * Interrupt source definition via IIR
  */
@@ -95,5 +109,5 @@
 #define CHARACTER_TIMEOUT_INDICATION		12
 
-/*
+/** @brief
  * Bits definition of IER
  */
@@ -104,26 +118,26 @@
 #define INTERRUPT_DISABLE	0x0
 
-/*
+/** @brief
  * Bits definition of the Line Status Register (LSR)
  */
-#define DR	0x01	/* Data Ready */
-#define OE	0x02	/* Overrun Error */
-#define PE	0x04	/* Parity Error */
-#define FE	0x08	/* Framing Error */
-#define BI	0x10	/* Break Interrupt */
-#define THRE	0x20	/* Transmitter Holding Register Empty */
-#define TEMT	0x40	/* Transmitter Empty */
-#define ERFIFO	0x80	/* Error receive Fifo */
+#define DR	0x01	///< Data Ready
+#define OE	0x02	///< Overrun Error
+#define PE	0x04	///< Parity Error
+#define FE	0x08	///< Framing Error
+#define BI	0x10	///< Break Interrupt
+#define THRE	0x20	///< Transmitter Holding Register Empty
+#define TEMT	0x40	///< Transmitter Empty
+#define ERFIFO	0x80	///< Error receive Fifo
 
-/*
+/** @brief
  * Bits definition of the MODEM Control Register (MCR)
  */
-#define DTR	0x01	/* Data Terminal Ready */
-#define RTS 	0x02	/* Request To Send */
-#define OUT_1	0x04	/* Output 1, (reserved on COMPAQ I/O Board) */
-#define OUT_2	0x08	/* Output 2, Enable Asynchronous Port Interrupts */
-#define LB	0x10	/* Enable Internal Loop Back */
+#define DTR	0x01	///< Data Terminal Ready
+#define RTS 	0x02	///< Request To Send
+#define OUT_1	0x04	///< Output 1, (reserved on COMPAQ I/O Board)
+#define OUT_2	0x08	///< Output 2, Enable Asynchronous Port Interrupts
+#define LB	0x10	///< Enable Internal Loop Back
 
-/*
+/** @brief
  * Bits definition of the Line Control Register (LCR)
  */
@@ -133,39 +147,41 @@
 #define CHR_8_BITS 3
 
-#define WL	0x03	/* Word length mask */
-#define STB	0x04	/* 1 Stop Bit, otherwise 2 Stop Bits */
-#define PEN	0x08	/* Parity Enabled */
-#define EPS	0x10	/* Even Parity Select, otherwise Odd */
-#define SP	0x20	/* Stick Parity */
-#define BCB	0x40	/* Break Control Bit */
-#define DLAB	0x80	/* Enable Divisor Latch Access */
+#define WL	0x03	///< Word length mask
+#define STB	0x04	///< 1 Stop Bit, otherwise 2 Stop Bits
+#define PEN	0x08	///< Parity Enabled
+#define EPS	0x10	///< Even Parity Select, otherwise Odd
+#define SP	0x20	///< Stick Parity
+#define BCB	0x40	///< Break Control Bit
+#define DLAB	0x80	///< Enable Divisor Latch Access
 
-/*
+/** @brief
  * Bits definition of the MODEM Status Register (MSR)
  */
-#define DCTS	0x01	/* Delta Clear To Send */
-#define DDSR	0x02	/* Delta Data Set Ready */
-#define TERI	0x04 	/* Trailing Edge Ring Indicator */
-#define DDCD	0x08	/* Delta Carrier Detect Indicator */
-#define CTS  	0x10 	/* Clear To Send (when loop back is active) */
-#define DSR	0x20	/* Data Set Ready (when loop back is active) */
-#define RI  	0x40 	/* Ring Indicator (when loop back is active) */
-#define DCD	0x80	/* Data Carrier Detect (when loop back is active) */
+#define DCTS	0x01	///< Delta Clear To Send
+#define DDSR	0x02	///< Delta Data Set Ready
+#define TERI	0x04 	///< Trailing Edge Ring Indicator
+#define DDCD	0x08	///< Delta Carrier Detect Indicator
+#define CTS  	0x10 	///< Clear To Send (when loop back is active)
+#define DSR	0x20	///< Data Set Ready (when loop back is active)
+#define RI  	0x40 	///< Ring Indicator (when loop back is active)
+#define DCD	0x80	///< Data Carrier Detect (when loop back is active)
 
-/*
+/** @brief
  * Bits definition of the FIFO Control Register : WD16C552 or NS16550
  */
 
-#define FIFO_CTRL   0x01    /* Set to 1 permit access to other bits */
-#define FIFO_EN	    0x01    /* Enable the FIFO */
-#define XMIT_RESET  0x02    /* Transmit FIFO Reset */
-#define RCV_RESET   0x04    /* Receive FIFO Reset */
-#define FCR3	    0x08    /* do not understand manual! */
+#define FIFO_CTRL   0x01    ///< Set to 1 permit access to other bits
+#define FIFO_EN	    0x01    ///< Enable the FIFO
+#define XMIT_RESET  0x02    ///< Transmit FIFO Reset
+#define RCV_RESET   0x04    ///< Receive FIFO Reset
+#define FCR3	    0x08    ///< do not understand manual!
 
-#define RECEIVE_FIFO_TRIGGER1	0x0  /* trigger recieve interrupt after 1 byte  */
-#define RECEIVE_FIFO_TRIGGER4	0x40 /* trigger recieve interrupt after 4 byte  */
-#define RECEIVE_FIFO_TRIGGER8	0x80 /* trigger recieve interrupt after 8 byte  */
-#define RECEIVE_FIFO_TRIGGER12	0xc0 /* trigger recieve interrupt after 12 byte */
-#define TRIG_LEVEL  		0xc0 /* Mask for the trigger level 		*/
+#define RECEIVE_FIFO_TRIGGER1	0x0  ///< trigger recieve interrupt after 1 byte
+#define RECEIVE_FIFO_TRIGGER4	0x40 ///< trigger recieve interrupt after 4 byte
+#define RECEIVE_FIFO_TRIGGER8	0x80 ///< trigger recieve interrupt after 8 byte
+#define RECEIVE_FIFO_TRIGGER12	0xc0 ///< trigger recieve interrupt after 12 byte
+#define TRIG_LEVEL  		0xc0 ///< Mask for the trigger level
+
+/** @} */
 
 #ifdef __cplusplus
Index: c/src/lib/libbsp/i386/shared/doxygen.h
===================================================================
--- c/src/lib/libbsp/i386/shared/doxygen.h	(revision 52943a24710905392c7d4375b204e36bcdd514d7)
+++ c/src/lib/libbsp/i386/shared/doxygen.h	(revision 52943a24710905392c7d4375b204e36bcdd514d7)
@@ -0,0 +1,23 @@
+/**
+ *  @defgroup bsp_i386 i386
+ *  @ingroup bsp_kit
+ *  @brief i386 Board Support Packages
+ */
+
+/**
+ *  @defgroup i386_shared i386 Shared Modules
+ *  @ingroup bsp_i386
+ *  @brief i386 Shared Modules
+ */
+
+/**
+ *  @defgroup i386_comm Comm
+ *  @ingroup i386_shared
+ *  @brief Comm
+ */
+
+/**
+ *  @defgroup i386_pci PCI
+ *  @ingroup i386_shared
+ *  @brief PCI
+ */
Index: c/src/lib/libbsp/i386/shared/irq/apic.h
===================================================================
--- c/src/lib/libbsp/i386/shared/irq/apic.h	(revision 9dc999af0107998037d55ddfc2d83b6b53383e64)
+++ c/src/lib/libbsp/i386/shared/irq/apic.h	(revision 52943a24710905392c7d4375b204e36bcdd514d7)
@@ -1,2 +1,8 @@
+/**
+ * @file
+ * @ingroup i386_apic
+ * @brief Local and I/O APIC definitions
+ */
+
 /*
  * Author: Erich Boleyn  <erich@uruk.org>
@@ -26,4 +32,11 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @defgroup i386_apci
+ * @ingroup i386_pci
+ * @brief Intel Architecture local and I/O APIC definitions
+ * @{
  */
 
@@ -59,8 +72,8 @@
  *  Shared defines for I/O and local APIC definitions
  */
-/* APIC version register */
+/** @brief APIC version register */
 #define APIC_VERSION(x)                         ((x) & 0xFF)
 #define APIC_MAXREDIR(x)                        (((x) >> 16) & 0xFF)
-/* APIC id register */
+/** @brief APIC id register */
 #define APIC_ID(x)                              ((x) >> 24)
 #define APIC_VER_NEW                            0x10
@@ -109,2 +122,4 @@
 
 #endif  /* _APIC_H */
+
+/** @} */
Index: c/src/lib/libbsp/i386/shared/irq/irq.h
===================================================================
--- c/src/lib/libbsp/i386/shared/irq/irq.h	(revision 9dc999af0107998037d55ddfc2d83b6b53383e64)
+++ c/src/lib/libbsp/i386/shared/irq/irq.h	(revision 52943a24710905392c7d4375b204e36bcdd514d7)
@@ -1,2 +1,8 @@
+/**
+ * @file
+ * @ingroup i386_irq
+ * @brief Interrupt handlers
+ */
+
 /* irq.h
  *
@@ -17,4 +23,11 @@
  */
 
+/**
+ * @defgroup i386_irq Interrupt handlers
+ * @ingroup i386_shared
+ * @brief Data structure and the functions to write interrupt handlers
+ * @{
+ */
+
 #ifndef _IRQ_H_
 #define _IRQ_H_
@@ -24,5 +37,5 @@
 #endif
 
-/*
+/** @brief
  * Include some preprocessor value also used by assember code
  */
@@ -38,5 +51,5 @@
 +--------------------------------------------------------------------------*/
 
-    /* Base vector for our IRQ handlers. */
+    /** @brief Base vector for our IRQ handlers. */
 #define BSP_IRQ_VECTOR_BASE		BSP_ASM_IRQ_VECTOR_BASE
 #define BSP_IRQ_LINES_NUMBER    	17
@@ -44,5 +57,5 @@
 #define BSP_MAX_ON_i8259S		(BSP_IRQ_LINES_NUMBER - 2)
 #define BSP_MAX_OFFSET		 	(BSP_IRQ_LINES_NUMBER - 1)
-    /*
+    /** @brief
      * Interrupt offset in comparison to BSP_ASM_IRQ_VECTOR_BASE
      * NB : 1) Interrupt vector number in IDT = offset + BSP_ASM_IRQ_VECTOR_BASE
@@ -63,5 +76,5 @@
 #define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET
 
-/*
+/** @brief
  * Type definition for RTEMS managed interrupts
  */
@@ -77,5 +90,5 @@
  */
 
-/*
+/** @brief
  * function to disable a particular irq at 8259 level. After calling
  * this function, even if the device asserts the interrupt line it will
@@ -83,5 +96,5 @@
  */
 int BSP_irq_disable_at_i8259s        (const rtems_irq_number irqLine);
-/*
+/** @brief
  * function to enable a particular irq at 8259 level. After calling
  * this function, if the device asserts the interrupt line it will
@@ -89,5 +102,5 @@
  */
 int BSP_irq_enable_at_i8259s		(const rtems_irq_number irqLine);
-/*
+/** @brief
  * function to acknoledge a particular irq at 8259 level. After calling
  * this function, if a device asserts an enabled interrupt line it will
@@ -97,8 +110,10 @@
  */
 int BSP_irq_ack_at_i8259s           	(const rtems_irq_number irqLine);
-/*
+/** @brief
  * function to check if a particular irq is enabled at 8259 level. After calling
  */
 int BSP_irq_enabled_at_i8259s        	(const rtems_irq_number irqLine);
+
+/** @} */
 
 #ifdef __cplusplus
Index: c/src/lib/libbsp/i386/shared/irq/irq_asm.h
===================================================================
--- c/src/lib/libbsp/i386/shared/irq/irq_asm.h	(revision 9dc999af0107998037d55ddfc2d83b6b53383e64)
+++ c/src/lib/libbsp/i386/shared/irq/irq_asm.h	(revision 52943a24710905392c7d4375b204e36bcdd514d7)
@@ -1,2 +1,8 @@
+/**
+ * @file
+ * @ingroup i386_irq
+ * @brief
+ */
+
 /* irq_asm.h
  *
@@ -15,13 +21,13 @@
 
 #define BSP_ASM_IRQ_VECTOR_BASE 0x20
-    /* PIC's command and mask registers */
-#define PIC_MASTER_COMMAND_IO_PORT		0x20	/* Master PIC command register */
-#define PIC_SLAVE_COMMAND_IO_PORT		0xa0	/* Slave PIC command register */
-#define PIC_MASTER_IMR_IO_PORT			0x21	/* Master PIC Interrupt Mask Register */
-#define PIC_SLAVE_IMR_IO_PORT		 	0xa1	/* Slave PIC Interrupt Mask Register */
+    /** @brief PIC's command and mask registers */
+#define PIC_MASTER_COMMAND_IO_PORT		0x20	///< Master PIC command register
+#define PIC_SLAVE_COMMAND_IO_PORT		0xa0	///< Slave PIC command register
+#define PIC_MASTER_IMR_IO_PORT			0x21	///< Master PIC Interrupt Mask Register
+#define PIC_SLAVE_IMR_IO_PORT		 	0xa1	///< Slave PIC Interrupt Mask Register
 
-    /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
-#define PIC_EOSI	0x60	/* End of Specific Interrupt (EOSI) */
-#define PIC_EOI		0x20	/* Generic End of Interrupt (EOI) */
+    /** @brief Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
+#define PIC_EOSI	0x60	///< End of Specific Interrupt (EOSI)
+#define PIC_EOI		0x20	///< Generic End of Interrupt (EOI)
 
 #endif
Index: c/src/lib/libbsp/i386/shared/pci/pcibios.h
===================================================================
--- c/src/lib/libbsp/i386/shared/pci/pcibios.h	(revision 9dc999af0107998037d55ddfc2d83b6b53383e64)
+++ c/src/lib/libbsp/i386/shared/pci/pcibios.h	(revision 52943a24710905392c7d4375b204e36bcdd514d7)
@@ -1,2 +1,8 @@
+/**
+ * @file
+ * @ingroup i386_pcibios
+ * @brief
+ */
+
 /*
  * This software is Copyright (C) 1998 by T.sqware - all rights limited
@@ -6,4 +12,11 @@
  */
 
+/**
+ * @defgroup i386_pcibios
+ * @ingroup i386_pci
+ * @brief
+ * @{
+ */
+
 #ifndef _PCIB_H
 #define _PCIB_H
@@ -11,5 +24,5 @@
 #include <rtems/pci.h>
 
-/*
+/** @brief
  * Make device signature from bus number, device numebr and function
  * number
@@ -17,5 +30,5 @@
 #define PCIB_DEVSIG_MAKE(b,d,f) ((b<<8)|(d<<3)|(f))
 
-/*
+/** @brief
  * Extract valrous part from device signature
  */
@@ -41,4 +54,6 @@
                    int instance, int *pbus, int *pdev, int *pfun );
 
+/** @} */
+
 #ifdef __cplusplus
 }
Index: c/src/lib/libbsp/i386/shared/smp/smp-imps.h
===================================================================
--- c/src/lib/libbsp/i386/shared/smp/smp-imps.h	(revision 9dc999af0107998037d55ddfc2d83b6b53383e64)
+++ c/src/lib/libbsp/i386/shared/smp/smp-imps.h	(revision 52943a24710905392c7d4375b204e36bcdd514d7)
@@ -1,2 +1,9 @@
+/**
+ * @file
+ * @ingroup i386_smp
+ * @brief Intel MultiProcessor Specification (MPS)
+ * version 1.1 and 1.4 SMP hardware control
+ */
+
 /*
  * Author: Erich Boleyn  <erich@uruk.org>
@@ -52,4 +59,13 @@
  */
 
+/**
+ *  @defgroup i386_smp SMP
+ *  @ingroup i386_shared
+ *  @brief
+ *  Header file implementing Intel MultiProcessor Specification (MPS)
+ *  version 1.1 and 1.4 SMP hardware control for Intel Architecture CPUs,
+ *  with hooks for running correctly on a standard PC without the hardware.
+ */
+
 #ifndef _SMP_IMPS_H
 #define _SMP_IMPS_H
@@ -75,5 +91,5 @@
 #define IMPS_MAX_CPUS                   APIC_BCAST_ID
 
-/*
+/** @brief
  *  This is the value that must be in the "sig" member of the MP
  *  Floating Pointer Structure.
@@ -83,5 +99,5 @@
 #define IMPS_FPS_DEFAULT_MAX    7
 
-/*
+/** @brief
  *  This is the value that must be in the "sig" member of the MP
  *  Configuration Table Header.
@@ -89,5 +105,5 @@
 #define IMPS_CTH_SIGNATURE      ('P' | ('C'<<8) | ('M'<<16) | ('P'<<24))
 
-/*
+/** @brief
  *  These are the "type" values for Base MP Configuration Table entries.
  */
@@ -109,6 +125,6 @@
  */
 
-typedef struct imps_fps imps_fps;       /* MP floating pointer structure */
-typedef struct imps_cth imps_cth;       /* MP configuration table header */
+typedef struct imps_fps imps_fps;       ///< MP floating pointer structure
+typedef struct imps_cth imps_cth;       ///< MP configuration table header
 typedef struct imps_processor imps_processor;
 typedef struct imps_bus imps_bus;
@@ -121,5 +137,5 @@
  */
 
-/*
+/** @brief
  *  MP Floating Pointer Structure (fps)
  *
@@ -137,5 +153,5 @@
 };
 
-/*
+/** @brief
  *  MP Configuration Table Header  (cth)
  *
@@ -160,5 +176,5 @@
 };
 
-/*
+/** @brief
  *  Base MP Configuration Table Types.  They are sorted according to
  *  type (i.e. all of type 0 come first, etc.).  Look on page 4-6 for
@@ -168,5 +184,5 @@
 struct imps_processor
 {
-  unsigned char type;                     /* must be 0 */
+  unsigned char type;                     ///< must be 0
   unsigned char apic_id;
   unsigned char apic_ver;
@@ -179,5 +195,5 @@
 struct imps_bus
 {
-  unsigned char type;                     /* must be 1 */
+  unsigned char type;                     ///< must be 1
   unsigned char id;
   char bus_type[6];
@@ -186,5 +202,5 @@
 struct imps_ioapic
 {
-  unsigned char type;                     /* must be 2 */
+  unsigned char type;                     ///< must be 2
   unsigned char id;
   unsigned char ver;
@@ -195,5 +211,5 @@
 struct imps_interrupt
 {
-  unsigned char type;                     /* must be 3 or 4 */
+  unsigned char type;                     ///< must be 3 or 4
   unsigned char int_type;
   unsigned short flags;
@@ -208,5 +224,5 @@
  */
 
-/*
+/** @brief
  *  These map from virtual cpu numbers to APIC id's and back.
  */
@@ -214,5 +230,5 @@
 extern unsigned char imps_apic_cpu_map[IMPS_MAX_CPUS];
 
-/* base address of application processor reset code at 0x70000 */
+/** @brief base address of application processor reset code at 0x70000 */
 extern char _binary_appstart_bin_start[];
 extern char _binary_appstart_bin_size[];
@@ -227,2 +243,3 @@
 #endif  /* !_SMP_IMPS_H */
 
+/** @} */
