Changeset 51ffa21 in rtems


Ignore:
Timestamp:
07/22/22 06:27:12 (17 months ago)
Author:
Chris Johns <chrisj@…>
Branches:
master
Children:
31036f1d
Parents:
b868d0a
git-author:
Chris Johns <chrisj@…> (07/22/22 06:27:12)
git-committer:
Chris Johns <chrisj@…> (07/27/22 23:04:46)
Message:

aarch64/versal: Support DDRMC0 region 0 and 1

  • Support DDRMC0 region 0 up to 2G in size
  • Support DDRMC0 region 1 with DDR memory greater than 2G up to the DDRMC0 max amount
  • Extend the heap with region 1's memory

Closes #4684

Files:
4 edited

Legend:

Unmodified
Added
Removed

  • bsps/aarch64/xilinx-versal/include/bsp.h

    rb868d0a r51ffa21  
    4848
    4949#include <bsp/default-initial-extension.h>
     50#include <bsp/linker-symbols.h>
    5051#include <bsp/start.h>
    5152
    … …  
    6162
    6263#define BSP_RESET_SMC
     64
     65/*
     66 * DDRMC mapping
     67 */
     68LINKER_SYMBOL(bsp_r0_ram_base)
     69LINKER_SYMBOL(bsp_r0_ram_end)
     70LINKER_SYMBOL(bsp_r1_ram_base)
     71LINKER_SYMBOL(bsp_r1_ram_end)
    6372
    6473/**

  • bsps/aarch64/xilinx-versal/start/bspstartmmu.c

    rb868d0a r51ffa21  
    3939#include <libcpu/mmu-vmsav8-64.h>
    4040
     41#include <rtems/malloc.h>
     42#include <rtems/sysinit.h>
     43
    4144BSP_START_DATA_SECTION static const aarch64_mmu_config_entry
    4245versal_mmu_config_table[] = {
    … …  
    5861    .end = 0xffc00000U,
    5962    .flags = AARCH64_MMU_DEVICE
     63  }, { /* DDRMC0_region1_mem, if not used size is 0 and ignored */
     64    .begin = (uintptr_t) bsp_r1_ram_base,
     65    .end = (uintptr_t) bsp_r1_ram_end,
     66    .flags = AARCH64_MMU_DATA_RW_CACHED
     67  }
     68};
     69
     70/*
     71 * Create an MMU table to get the R1 base and end. This avoids
     72 * relocation errors as the R1 addresses are in the upper A64 address
     73 * space.
     74 *
     75 * The versal_mmu_config_table table cannot be used because the regions
     76 * in that table have no identifiers to indicate which region is the
     77 * the DDRMC0_region1_mem region.
     78 */
     79static const struct mem_region {
     80  uintptr_t begin;
     81  uintptr_t end;
     82} bsp_r1_region[] = {
     83  { /* DDRMC0_region1_mem, if not used size is 0 and ignored */
     84    .begin = (uintptr_t) bsp_r1_ram_base,
     85    .end = (uintptr_t) bsp_r1_ram_end,
    6086  }
    6187};
    … …  
    79105  aarch64_mmu_enable();
    80106}
     107
     108void bsp_r1_heap_extend(void);
     109void bsp_r1_heap_extend(void)
     110{
     111  const struct mem_region* r1 = &bsp_r1_region[0];
     112  if (r1->begin != r1->end) {
     113    rtems_status_code sc =
     114      rtems_heap_extend((void*) r1->begin, r1->end - r1->begin);
     115    if (sc != RTEMS_SUCCESSFUL) {
     116      bsp_fatal(BSP_FATAL_HEAP_EXTEND_ERROR);
     117    }
     118  }
     119}
     120
     121/*
     122 * Initialise after the IDLE thread exists so the protected heap
     123 * extend call has a valid context.
     124 */
     125RTEMS_SYSINIT_ITEM(
     126  bsp_r1_heap_extend,
     127  RTEMS_SYSINIT_IDLE_THREADS,
     128  RTEMS_SYSINIT_ORDER_LAST
     129);

  • bsps/include/bsp/fatal.h

    rb868d0a r51ffa21  
    7474  BSP_FATAL_CONSOLE_REGISTER_DEV_2,
    7575  BSP_FATAL_MMU_ADDRESS_INVALID,
     76  BSP_FATAL_HEAP_EXTEND_ERROR,
    7677
    7778  /* ARM fatal codes */

  • spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml

    rb868d0a r51ffa21  
    55
    66  /*
    7    * Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
     7   * Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
     8   * Copyright (C) 2022 Chris Johns <chrisj@rtems.org>
    89   *
    910   * Redistribution and use in source and binary forms, with or without
    … …  
    2930   */
    3031
     32  /*
     33   * The RAM supports 32G of DDR4 or LPDDR memory using DDRMC0.
     34   *
     35   * The DDR Conroller (DDRC) has two regions R0 and R1. R0 is
     36   * in the A32 address space and R1 is in the A64 address space.
     37   */
     38  DDRMC0_REGION_0_BASE = 0x00000000000;
     39  DDRMC0_REGION_0_LENGTH = 0x00080000000;
     40  DDRMC0_REGION_1_BASE = 0x00800000000;
     41  DDRMC0_REGION_1_LENGTH = 0x01000000000;
     42
     43  BSP_RAM_BASE = ${BSP_XILINX_VERSAL_RAM_BASE};
     44
     45  BSP_R0_RAM_BASE = DDRMC0_REGION_0_BASE;
     46  BSP_R0_RAM_LENGTH =
     47     ${BSP_XILINX_VERSAL_RAM_LENGTH} >= DDRMC0_REGION_0_LENGTH ?
     48         DDRMC0_REGION_0_LENGTH - BSP_RAM_BASE : ${BSP_XILINX_VERSAL_RAM_LENGTH};
     49  BSP_R0_RAM_END = BSP_RAM_BASE + BSP_R0_RAM_LENGTH;
     50
     51  BSP_R1_RAM_BASE = DDRMC0_REGION_1_BASE;
     52  BSP_R1_RAM_LENGTH =
     53     ${BSP_XILINX_VERSAL_RAM_LENGTH} >= DDRMC0_REGION_0_LENGTH ?
     54         ${BSP_XILINX_VERSAL_RAM_LENGTH} - DDRMC0_REGION_0_LENGTH : 0;
     55
     56  AARCH64_MMU_TT_PAGES_SIZE = 0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES};
     57
    3158  MEMORY {
    32     RAM       : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH} - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
    33     NOCACHE   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
    34     RAM_MMU   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
     59    RAM       : ORIGIN = BSP_RAM_BASE + ${BSP_XILINX_VERSAL_LOAD_OFFSET},
     60                LENGTH = BSP_R0_RAM_LENGTH - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} - AARCH64_MMU_TT_PAGES_SIZE
     61    RAM1      : ORIGIN = BSP_R1_RAM_BASE,
     62                LENGTH = BSP_R1_RAM_LENGTH
     63    NOCACHE   : ORIGIN = BSP_RAM_BASE + BSP_R0_RAM_LENGTH - AARCH64_MMU_TT_PAGES_SIZE - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH},
     64                LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
     65    RAM_MMU   : ORIGIN = BSP_R0_RAM_END - AARCH64_MMU_TT_PAGES_SIZE,
     66                LENGTH = AARCH64_MMU_TT_PAGES_SIZE
    3567  }
    3668
    … …  
    5991  bsp_vector_table_in_start_section = 1;
    6092
     93  bsp_r0_ram_base = DDRMC0_REGION_0_BASE;
     94  bsp_r0_ram_end = ORIGIN (RAM) + LENGTH (RAM);
     95  bsp_r1_ram_base = ORIGIN (RAM1);
     96  bsp_r1_ram_end = ORIGIN (RAM1) + LENGTH (RAM1);
     97
    6198  bsp_translation_table_base = ORIGIN (RAM_MMU);
    6299  bsp_translation_table_end = ORIGIN (RAM_MMU) + LENGTH (RAM_MMU);
    … …  
    67104  INCLUDE linkcmds.base
    68105copyrights:
    69 - Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
     106- Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
     107- Copyright (C) 2022 Chris Johns <chrisj@rtems.org>
    70108enabled-by: true
    71109install-path: ${BSP_LIBDIR}
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