Changeset 518edef in rtems for c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c
- Timestamp:
- 01/31/05 19:03:41 (17 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- fa5dfe8
- Parents:
- 9be8c2d
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c
r9be8c2d r518edef 110 110 void _CPU_cache_invalidate_1_instruction_line(const void *addr) 111 111 { 112 asm volatile ("cpushl %%ic,(%0)" :: "a" (addr)); 112 /* 113 * Top half of cache is I-space 114 */ 115 addr = (void *)((int)addr | 0x400); 116 asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); 113 117 } 114 118 … … 128 132 129 133 rtems_interrupt_disable(level); 134 rtems_interrupt_disable(level); 130 135 cacr_mode |= MCF5XXX_CACR_DISD; 131 136 m68k_set_cacr(cacr_mode); … … 140 145 void _CPU_cache_invalidate_1_data_line(const void *addr) 141 146 { 142 asm volatile ("cpushl %%dc,(%0)" :: "a" (addr)); 147 /* 148 * Bottom half of cache is D-space 149 */ 150 addr = (void *)((int)addr & ~0x400); 151 asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); 143 152 } 144 153
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