Changeset 513b6c4b in rtems
- Timestamp:
- 09/27/04 21:44:10 (18 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 6a61cf94
- Parents:
- cd38196f
- Location:
- c/src/lib/libbsp/powerpc/shared
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/powerpc/shared/ChangeLog
rcd38196f r513b6c4b 1 2003-11-01 Greg Menke <gregory.menke@gsfc.nasa.gov> 2 3 PR 606/bsps 4 * bootloader/pci.c: Fixed IO remapping so buses >= 1 are remapped. 5 Reduced PCI space to match bat2. Fixed incorrect region size 6 calculation in pci_read_bases. Set PCI latency timers to known 7 sane values. Changed bridge PCI settings to minimum sane instead 8 of whatever sounded neat in the PCI spec. Force pf regions to 9 memory mapped to preserve byte access. 10 1 11 2004-04-09 Greg Menke <gregory.menke@gsfc.nasa.gov> 2 12 PR 608/bsps -
c/src/lib/libbsp/powerpc/shared/bootloader/pci.c
rcd38196f r513b6c4b 29 29 typedef unsigned int u32; 30 30 31 32 31 33 /* 32 34 #define DEBUG … … 224 226 ** 225 227 ** Gregm, 7/16/2003 228 ** 229 ** Gregm, changed 11/2003 so IO devices only on bus 0 zero are not 230 ** remapped. This covers the builtin pc-like io devices- but 231 ** properly maps IO devices on higher busses. 226 232 */ 227 if( r->dev->bus->number <= 1)233 if( r->dev->bus->number == 0 ) 228 234 { 229 235 if ((r->type==PCI_BASE_ADDRESS_SPACE_IO) … … 461 467 #define BUS0_IO_END 0x1ffff 462 468 #define BUS0_MEM_START 0x1000000 463 #define BUS0_MEM_END 0x affffff469 #define BUS0_MEM_END 0x3f00000 464 470 465 471 #define BUSREST_IO_START 0x20000 466 472 #define BUSREST_IO_END 0x7ffff 467 #define BUSREST_MEM_START 0x b000000473 #define BUSREST_MEM_START 0x4000000 468 474 #define BUSREST_MEM_END 0x10000000 469 475 … … 518 524 PCI_BASE_ADDRESS_MEM_TYPE_64)) { 519 525 pci_write_config_dword(r->dev, 520 PCI_BASE_ADDRESS_1+ 521 (r->reg<<2), 526 PCI_BASE_ADDRESS_1+(r->reg<<2), 522 527 0); 523 528 } … … 746 751 r->type = l&~PCI_BASE_ADDRESS_IO_MASK; 747 752 r->base = l&PCI_BASE_ADDRESS_IO_MASK; 748 r->size = ~(ml&PCI_BASE_ADDRESS_IO_MASK)+1;753 /* r->size = ~(ml&PCI_BASE_ADDRESS_IO_MASK)+1; */ 749 754 } else { 750 755 r->type = l&~PCI_BASE_ADDRESS_MEM_MASK; 751 756 r->base = l&PCI_BASE_ADDRESS_MEM_MASK; 752 r->size = ~(ml&PCI_BASE_ADDRESS_MEM_MASK)+1; 753 } 757 /* r->size = ~(ml&PCI_BASE_ADDRESS_MEM_MASK)+1; */ 758 } 759 760 /* find the first bit set to one after the base 761 address type bits to find length of region */ 762 { 763 unsigned int c= 16 , val= 0; 764 while( !(val= ml & c) ) c <<= 1; 765 r->size = val; 766 } 767 768 #ifdef PCI_DEBUG 769 printk(" readbase bus %d, (%04x:%04x), base %08x, size %08x, type %d\n", 770 r->dev->bus->number, 771 r->dev->vendor, 772 r->dev->device, 773 r->base, 774 r->size, 775 r->type ); 776 #endif 777 754 778 /* Check for the blacklisted entries */ 755 779 insert_resource(r); … … 1067 1091 pdev= childbus->self; 1068 1092 1093 pcibios_write_config_byte(pdev->bus->number, pdev->devfn, PCI_LATENCY_TIMER, 0x80 ); 1094 pcibios_write_config_byte(pdev->bus->number, pdev->devfn, PCI_SEC_LATENCY_TIMER, 0x80 ); 1095 1069 1096 { 1070 1097 struct _addr_start addrhold; … … 1088 1115 1089 1116 /* 1090 **use the current values & the saved ones to figure out1091 ** the address spaces for the bridge1092 */1117 * use the current values & the saved ones to figure out 1118 * the address spaces for the bridge 1119 */ 1093 1120 1094 1121 if( addrhold.start_pciio == astart.start_pciio ) … … 1136 1163 #endif 1137 1164 1165 1138 1166 if( astart.start_prefetch == addrhold.start_prefetch ) 1139 1167 { … … 1155 1183 pcibios_write_config_dword(pdev->bus->number, pdev->devfn, PCI_PREF_LIMIT_UPPER32, 0); 1156 1184 pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_PREF_MEMORY_LIMIT, limit16 ); 1157 1158 1185 #endif 1159 1186 1160 1187 #ifdef WRITE_BRIDGE_ENABLE 1161 pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_BRIDGE_CONTROL, (uint16_t)( PCI_BRIDGE_CTL_PARITY | 1162 PCI_BRIDGE_CTL_SERR )); 1163 1164 pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_COMMAND, (uint16_t)( PCI_COMMAND_IO | 1165 PCI_COMMAND_MEMORY | 1166 PCI_COMMAND_MASTER | 1167 PCI_COMMAND_PARITY | 1168 PCI_COMMAND_SERR )); 1188 pcibios_write_config_word(pdev->bus->number, 1189 pdev->devfn, 1190 PCI_BRIDGE_CONTROL, 1191 (unsigned16)( 0 )); 1192 1193 pcibios_write_config_word(pdev->bus->number, 1194 pdev->devfn, 1195 PCI_COMMAND, 1196 (unsigned16)( PCI_COMMAND_IO | 1197 PCI_COMMAND_MEMORY | 1198 PCI_COMMAND_MASTER )); 1169 1199 #endif 1170 1200 } … … 1197 1227 while( (r= enum_device_resources( pdev, i++ )) ) 1198 1228 { 1199 if( r->type & PCI_BASE_ADDRESS_MEM_PREFETCH ) 1229 /* 1230 ** Force all memory spaces to be non-prefetchable because 1231 ** on the pci bus, byte-wise reads against prefetchable 1232 ** memory are applied as 32 bit reads, which is a pain 1233 ** when you're trying to talk to hardware. This is a 1234 ** little sub-optimal because the algorithm doesn't sort 1235 ** the address regions to pack them in, OTOH, perhaps its 1236 ** not so bad because the inefficient packing will help 1237 ** avoid buffer overflow/underflow problems. 1238 */ 1239 #if 0 1240 if( (r->type & PCI_BASE_ADDRESS_MEM_PREFETCH) ) 1200 1241 { 1201 1242 /* prefetchable space */ … … 1211 1252 #endif 1212 1253 } 1213 else if( r->type & PCI_BASE_ADDRESS_SPACE_IO ) 1254 #endif 1255 if( r->type & PCI_BASE_ADDRESS_SPACE_IO ) 1214 1256 { 1215 1257 /* io space */ … … 1305 1347 1306 1348 print_pci_resources("Allocated PCI resources:\n"); 1349 1350 #if 0 1351 print_pci_info(); 1352 #endif 1307 1353 } 1308 1354 -
c/src/lib/libbsp/powerpc/shared/pci/pci.c
rcd38196f r513b6c4b 22 22 #include <libcpu/io.h> 23 23 #include <bsp/pci.h> 24 #include <rtems/bspIo.h>25 24 26 25 /* allow for overriding these definitions */ … … 339 338 340 339 /* printk("pci : device %d:%02x devid %04x, intpin %d, intline %d\n", pbus, pslot, devid, int_pin, int_name ); */ 340 341 #if 0 342 { 343 unsigned short cmd,stat; 344 unsigned char lat, seclat, csize; 345 346 pci_read_config_word(pbus,pslot,0,PCI_COMMAND, &cmd ); 347 pci_read_config_word(pbus,pslot,0,PCI_STATUS, &stat ); 348 pci_read_config_byte(pbus,pslot,0,PCI_LATENCY_TIMER, &lat ); 349 pci_read_config_byte(pbus,pslot,0,PCI_SEC_LATENCY_TIMER, &seclat ); 350 pci_read_config_byte(pbus,pslot,0,PCI_CACHE_LINE_SIZE, &csize ); 351 352 353 printk("pci : device %d:%02x cmd %04X, stat %04X, latency %d, sec_latency %d, clsize %d\n", pbus, pslot, 354 cmd, 355 stat, 356 lat, 357 seclat, 358 csize); 359 } 360 #endif 341 361 342 362 if( int_pin > 0 ) … … 367 387 if( int_name == -1 ) 368 388 { 369 printk("pci : Unable to resolve device %d:%d w/ swizzled int pin % dto an interrupt_line.\n", pbus, pslot, int_pin );389 printk("pci : Unable to resolve device %d:%d w/ swizzled int pin %i to an interrupt_line.\n", pbus, pslot, int_pin ); 370 390 } 371 391 else … … 435 455 if( int_name == -1 ) 436 456 { 437 printk("pci : Unable to resolve device %d:%d w/ swizzled int pin % dto an interrupt_line.\n", pbus, pslot, int_pin );457 printk("pci : Unable to resolve device %d:%d w/ swizzled int pin %i to an interrupt_line.\n", pbus, pslot, int_pin ); 438 458 } 439 459 else … … 475 495 else 476 496 { 477 printk("pci : No bridge from bus % dtowards root found\n", tbus );497 printk("pci : No bridge from bus %i towards root found\n", tbus ); 478 498 goto donesearch; 479 499 }
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