Changeset 513b6c4b in rtems


Ignore:
Timestamp:
Sep 27, 2004, 9:44:10 PM (15 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
6a61cf94
Parents:
cd38196f
Message:

2003-11-01 Greg Menke <gregory.menke@…>

PR 606/bsps

  • bootloader/pci.c: Fixed IO remapping so buses >= 1 are remapped. Reduced PCI space to match bat2. Fixed incorrect region size calculation in pci_read_bases. Set PCI latency timers to known sane values. Changed bridge PCI settings to minimum sane instead of whatever sounded neat in the PCI spec. Force pf regions to memory mapped to preserve byte access.
Location:
c/src/lib/libbsp/powerpc/shared
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/shared/ChangeLog

    rcd38196f r513b6c4b  
     12003-11-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
     2
     3        PR 606/bsps
     4        * bootloader/pci.c: Fixed IO remapping so buses >= 1 are remapped.
     5        Reduced PCI space to match bat2.  Fixed incorrect region size
     6        calculation in pci_read_bases.  Set PCI latency timers to known
     7        sane values.  Changed bridge PCI settings to minimum sane instead
     8        of whatever sounded neat in the PCI spec.  Force pf regions to
     9        memory mapped to preserve byte access.
     10
    1112004-04-09      Greg Menke <gregory.menke@gsfc.nasa.gov>
    212        PR 608/bsps
  • c/src/lib/libbsp/powerpc/shared/bootloader/pci.c

    rcd38196f r513b6c4b  
    2929typedef unsigned int u32;
    3030
     31
     32
    3133/*
    3234#define DEBUG
     
    224226   **
    225227   ** Gregm, 7/16/2003
     228   **
     229   ** Gregm, changed 11/2003 so IO devices only on bus 0 zero are not
     230   ** remapped.  This covers the builtin pc-like io devices- but
     231   ** properly maps IO devices on higher busses.
    226232   */
    227    if( r->dev->bus->number <= 1 )
     233   if( r->dev->bus->number == 0 )
    228234   {
    229235   if ((r->type==PCI_BASE_ADDRESS_SPACE_IO)
     
    461467#define BUS0_IO_END             0x1ffff
    462468#define BUS0_MEM_START          0x1000000
    463 #define BUS0_MEM_END            0xaffffff
     469#define BUS0_MEM_END            0x3f00000
    464470
    465471#define BUSREST_IO_START        0x20000
    466472#define BUSREST_IO_END          0x7ffff
    467 #define BUSREST_MEM_START       0xb000000
     473#define BUSREST_MEM_START       0x4000000
    468474#define BUSREST_MEM_END        0x10000000
    469475
     
    518524           PCI_BASE_ADDRESS_MEM_TYPE_64)) {
    519525         pci_write_config_dword(r->dev,
    520                                 PCI_BASE_ADDRESS_1+
    521                                 (r->reg<<2),
     526                                PCI_BASE_ADDRESS_1+(r->reg<<2),
    522527                                0);
    523528      }
     
    746751         r->type = l&~PCI_BASE_ADDRESS_IO_MASK;
    747752         r->base = l&PCI_BASE_ADDRESS_IO_MASK;
    748          r->size = ~(ml&PCI_BASE_ADDRESS_IO_MASK)+1;
     753         /* r->size = ~(ml&PCI_BASE_ADDRESS_IO_MASK)+1; */
    749754      } else {
    750755         r->type = l&~PCI_BASE_ADDRESS_MEM_MASK;
    751756         r->base = l&PCI_BASE_ADDRESS_MEM_MASK;
    752          r->size = ~(ml&PCI_BASE_ADDRESS_MEM_MASK)+1;
    753       }
     757         /* r->size = ~(ml&PCI_BASE_ADDRESS_MEM_MASK)+1; */
     758      }
     759
     760      /* find the first bit set to one after the base
     761         address type bits to find length of region */
     762      {
     763         unsigned int c= 16 , val= 0;
     764         while( !(val= ml & c) ) c <<= 1;
     765         r->size = val;
     766      }
     767
     768#ifdef PCI_DEBUG
     769      printk("   readbase bus %d, (%04x:%04x), base %08x, size %08x, type %d\n",
     770             r->dev->bus->number,
     771             r->dev->vendor,
     772             r->dev->device,
     773             r->base,
     774             r->size,
     775             r->type );
     776#endif
     777
    754778      /* Check for the blacklisted entries */
    755779      insert_resource(r);
     
    10671091      pdev= childbus->self;
    10681092
     1093      pcibios_write_config_byte(pdev->bus->number, pdev->devfn, PCI_LATENCY_TIMER,     0x80 );
     1094      pcibios_write_config_byte(pdev->bus->number, pdev->devfn, PCI_SEC_LATENCY_TIMER, 0x80 );
     1095
    10691096      {
    10701097         struct _addr_start   addrhold;
     
    10881115
    10891116         /*
    1090          **use the current values & the saved ones to figure out
    1091          ** the address spaces for the bridge
    1092          */
     1117          * use the current values & the saved ones to figure out
     1118          * the address spaces for the bridge
     1119          */
    10931120
    10941121         if( addrhold.start_pciio == astart.start_pciio )
     
    11361163#endif
    11371164
     1165
    11381166         if( astart.start_prefetch == addrhold.start_prefetch )
    11391167         {
     
    11551183         pcibios_write_config_dword(pdev->bus->number, pdev->devfn, PCI_PREF_LIMIT_UPPER32, 0);
    11561184         pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_PREF_MEMORY_LIMIT, limit16 );
    1157 
    11581185#endif
    11591186
    11601187#ifdef WRITE_BRIDGE_ENABLE
    1161          pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_BRIDGE_CONTROL, (uint16_t)( PCI_BRIDGE_CTL_PARITY |
    1162                                                                                                      PCI_BRIDGE_CTL_SERR ));
    1163 
    1164          pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_COMMAND, (uint16_t)( PCI_COMMAND_IO |
    1165                                                                                               PCI_COMMAND_MEMORY |
    1166                                                                                               PCI_COMMAND_MASTER |
    1167                                                                                               PCI_COMMAND_PARITY |
    1168                                                                                               PCI_COMMAND_SERR ));
     1188         pcibios_write_config_word(pdev->bus->number,
     1189                                   pdev->devfn,
     1190                                   PCI_BRIDGE_CONTROL,
     1191                                   (unsigned16)( 0 ));
     1192
     1193         pcibios_write_config_word(pdev->bus->number,
     1194                                   pdev->devfn,
     1195                                   PCI_COMMAND,
     1196                                   (unsigned16)( PCI_COMMAND_IO |
     1197                                                 PCI_COMMAND_MEMORY |
     1198                                                 PCI_COMMAND_MASTER ));
    11691199#endif
    11701200      }
     
    11971227            while( (r= enum_device_resources( pdev, i++ )) )
    11981228            {
    1199                if( r->type & PCI_BASE_ADDRESS_MEM_PREFETCH )
     1229               /*
     1230               ** Force all memory spaces to be non-prefetchable because
     1231               ** on the pci bus, byte-wise reads against prefetchable
     1232               ** memory are applied as 32 bit reads, which is a pain
     1233               ** when you're trying to talk to hardware.  This is a
     1234               ** little sub-optimal because the algorithm doesn't sort
     1235               ** the address regions to pack them in, OTOH, perhaps its
     1236               ** not so bad because the inefficient packing will help
     1237               ** avoid buffer overflow/underflow problems.
     1238               */
     1239#if 0
     1240               if( (r->type & PCI_BASE_ADDRESS_MEM_PREFETCH) )
    12001241               {
    12011242                  /* prefetchable space */
     
    12111252#endif
    12121253               }
    1213                else if( r->type & PCI_BASE_ADDRESS_SPACE_IO )
     1254#endif
     1255               if( r->type & PCI_BASE_ADDRESS_SPACE_IO )
    12141256               {
    12151257                  /* io space */
     
    13051347
    13061348   print_pci_resources("Allocated PCI resources:\n");
     1349
     1350#if 0
     1351   print_pci_info();
     1352#endif
    13071353}
    13081354
  • c/src/lib/libbsp/powerpc/shared/pci/pci.c

    rcd38196f r513b6c4b  
    2222#include <libcpu/io.h>
    2323#include <bsp/pci.h>
    24 #include <rtems/bspIo.h>
    2524
    2625/* allow for overriding these definitions */
     
    339338
    340339/* printk("pci : device %d:%02x devid %04x, intpin %d, intline  %d\n", pbus, pslot, devid, int_pin, int_name ); */
     340
     341#if 0
     342         {
     343            unsigned short cmd,stat;
     344            unsigned char  lat, seclat, csize;
     345
     346            pci_read_config_word(pbus,pslot,0,PCI_COMMAND, &cmd );
     347            pci_read_config_word(pbus,pslot,0,PCI_STATUS, &stat );
     348            pci_read_config_byte(pbus,pslot,0,PCI_LATENCY_TIMER, &lat );
     349            pci_read_config_byte(pbus,pslot,0,PCI_SEC_LATENCY_TIMER, &seclat );
     350            pci_read_config_byte(pbus,pslot,0,PCI_CACHE_LINE_SIZE, &csize );
     351           
     352
     353            printk("pci : device %d:%02x  cmd %04X, stat %04X, latency %d, sec_latency %d, clsize %d\n", pbus, pslot,
     354                   cmd,
     355                   stat,
     356                   lat,
     357                   seclat,
     358                   csize);
     359         }
     360#endif
    341361
    342362         if( int_pin > 0 )
     
    367387                     if( int_name == -1 )
    368388                     {
    369                         printk("pci : Unable to resolve device %d:%d w/ swizzled int pin %d to an interrupt_line.\n", pbus, pslot, int_pin );
     389                        printk("pci : Unable to resolve device %d:%d w/ swizzled int pin %i to an interrupt_line.\n", pbus, pslot, int_pin );
    370390                     }
    371391                     else
     
    435455                           if( int_name == -1 )
    436456                           {
    437                               printk("pci : Unable to resolve device %d:%d w/ swizzled int pin %d to an interrupt_line.\n", pbus, pslot, int_pin );
     457                              printk("pci : Unable to resolve device %d:%d w/ swizzled int pin %i to an interrupt_line.\n", pbus, pslot, int_pin );
    438458                           }
    439459                           else
     
    475495                     else
    476496                     {
    477                         printk("pci : No bridge from bus %d towards root found\n", tbus );
     497                        printk("pci : No bridge from bus %i towards root found\n", tbus );
    478498                        goto donesearch;
    479499                     }
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