Changeset 51347053 in rtems


Ignore:
Timestamp:
Jul 1, 2013, 1:00:21 PM (6 years ago)
Author:
Daniel Hellstrom <daniel@…>
Branches:
4.11, master
Children:
acf7047e
Parents:
d936c1a
git-author:
Daniel Hellstrom <daniel@…> (07/01/13 13:00:21)
git-committer:
Daniel Hellstrom <daniel@…> (04/16/15 23:10:20)
Message:

LEON PCI: host bridge driver support for probing dev0=AD16

Before the LIBPCI didn't probe device0 (AD16), the host bridge
drivers used bus=dev=func=0 to internally probe the host bridge's
target interface. Now that LIBPCI uses bus=dev=func=0 to access
device0, bus=0xff is introduced internally to identify the
host bridge target configuration space.

Location:
c/src/lib/libbsp/sparc
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sparc/leon2/pci/at697_pci.c

    rd936c1a r51347053  
    162162        int                     minor;
    163163
    164         uint32_t                devVend; /* PCI Device and Vendor ID of Host */
    165164        uint32_t                bar1_pci_adr;
    166165        uint32_t                bar2_pci_adr;
     
    229228        int retval;
    230229
    231         if (slot > 21 || (offset & ~0xfc)) {
     230        if (slot > 15 || (offset & ~0xfc)) {
    232231                *val = 0xffffffff;
    233232                return PCISTS_EINVAL;
     
    240239        if ( bus == 0 ) {
    241240                /* PCI Access - TYPE 0 */
    242                 address = (1<<(11+slot)) | (func << 8) | offset;
     241                address = (1<<(16+slot)) | (func << 8) | offset;
    243242        } else {
    244243                /* PCI access - TYPE 1 */
     
    462461        /* Set Inititator configuration so that AHB slave accesses generate memory read/write commands */
    463462        regs->pciic = 0x41;
    464 
    465         /* Get the AT697PCI Host PCI ID */
    466         at697pci_cfg_r32(host, PCI_VENDOR_ID, &priv->devVend);
    467463
    468464        return 0;
  • c/src/lib/libbsp/sparc/shared/pci/grpci.c

    rd936c1a r51347053  
    8686};
    8787
     88#define HOST_TGT PCI_DEV(0xff, 0, 0)
     89
    8890struct grpci_priv *grpcipriv = NULL;
    8991static int grpci_minor = 0;
     
    169171        struct grpci_priv *priv = grpcipriv;
    170172        volatile uint32_t *pci_conf;
    171         unsigned int devfn = PCI_DEV_DEVFUNC(dev);
     173        uint32_t devfn;
    172174        int retval;
    173175        int bus = PCI_DEV_BUS(dev);
     
    176178                return PCISTS_EINVAL;
    177179
    178         if (PCI_DEV_SLOT(dev) > 21) {
     180        if (PCI_DEV_SLOT(dev) > 15) {
    179181                *val = 0xffffffff;
    180182                return PCISTS_OK;
    181183        }
     184
     185        /* GRPCI can access "non-standard" devices on bus0 (on AD11.AD16),
     186         * but we skip them.
     187         */
     188        if (dev == HOST_TGT)
     189                bus = devfn = 0;
     190        if (bus == 0)
     191                devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
     192        else
     193                devfn = PCI_DEV_DEVFUNC(dev);
    182194
    183195        /* Select bus */
     
    241253                return PCISTS_EINVAL;
    242254
    243         if (PCI_DEV_SLOT(dev) > 21)
     255        if (PCI_DEV_SLOT(dev) > 15)
    244256                return PCISTS_MSTABRT;
     257
     258        /* GRPCI can access "non-standard" devices on bus0 (on AD11.AD16),
     259         * but we skip them.
     260         */
     261        if (dev == HOST_TGT)
     262                bus = devfn = 0;
     263        if (bus == 0)
     264                devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
     265        else
     266                devfn = PCI_DEV_DEVFUNC(dev);
    245267
    246268        /* Select bus */
     
    410432        volatile unsigned int *mbar0, *page0;
    411433        uint32_t data, addr, mbar0size;
    412         pci_dev_t host = PCI_DEV(0, 0, 0);
     434        pci_dev_t host = HOST_TGT;
    413435
    414436        mbar0 = (volatile unsigned int *)priv->pci_area;
  • c/src/lib/libbsp/sparc/shared/pci/grpci2.c

    rd936c1a r51347053  
    197197#define CAP9_AHBPREF_OFS 0x3C
    198198
     199/* Used internally for accessing the PCI bridge's configuration space itself */
     200#define HOST_TGT PCI_DEV(0xff, 0, 0)
     201
    199202struct grpci2_priv *grpci2priv = NULL;
    200203
     
    311314         * we skip them.
    312315         */
    313         if (bus == 0 && PCI_DEV_SLOT(dev) != 0)
     316        if (dev == HOST_TGT)
     317                bus = devfn = 0;
     318        else if (bus == 0)
    314319                devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
    315320        else
     
    399404         * we skip them.
    400405         */
    401         if (bus == 0 && PCI_DEV_SLOT(dev) != 0)
     406        if (dev == HOST_TGT)
     407                bus = devfn = 0;
     408        if (bus == 0)
    402409                devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
    403410        else
     
    628635        uint8_t capptr;
    629636        uint32_t data, io_map, ahbadr, pciadr, size;
    630         pci_dev_t host = PCI_DEV(0, 0, 0);
     637        pci_dev_t host = HOST_TGT;
    631638        struct grpci2_pcibar_cfg *barcfg = priv->barcfg;
    632639
  • c/src/lib/libbsp/sparc/shared/pci/pcif.c

    rd936c1a r51347053  
    7474};
    7575
     76/* Used internally for accessing the PCI bridge's configuration space itself */
     77#define HOST_TGT PCI_DEV(0xff, 0, 0)
     78
    7679struct pcif_priv *pcifpriv = NULL;
    7780static int pcif_minor = 0;
     
    155158        struct pcif_priv *priv = pcifpriv;
    156159        volatile uint32_t *pci_conf;
    157         unsigned int devfn = PCI_DEV_DEVFUNC(dev);
     160        uint32_t devfn;
    158161        int retval;
    159162        int bus = PCI_DEV_BUS(dev);
     
    162165                return PCISTS_EINVAL;
    163166
    164         if (PCI_DEV_SLOT(dev) > 21) {
     167        if (PCI_DEV_SLOT(dev) > 15) {
    165168                *val = 0xffffffff;
    166169                return PCISTS_OK;
    167170        }
     171
     172        /* PCIF can access "non-standard" devices on bus0 (on AD11.AD16),
     173         * but we skip them.
     174         */
     175        if (dev == HOST_TGT)
     176                bus = devfn = 0;
     177        if (bus == 0)
     178                devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
     179        else
     180                devfn = PCI_DEV_DEVFUNC(dev);
    168181
    169182        /* Select bus */
     
    215228        struct pcif_priv *priv = pcifpriv;
    216229        volatile uint32_t *pci_conf;
    217         uint32_t devfn = PCI_DEV_DEVFUNC(dev);
     230        uint32_t devfn;
    218231        int bus = PCI_DEV_BUS(dev);
    219232
     
    221234                return PCISTS_EINVAL;
    222235
    223         if (PCI_DEV_SLOT(dev) > 21)
     236        if (PCI_DEV_SLOT(dev) > 15)
    224237                return PCISTS_MSTABRT;
     238
     239        /* PCIF can access "non-standard" devices on bus0 (on AD11.AD16),
     240         * but we skip them.
     241         */
     242        if (dev == HOST_TGT)
     243                bus = devfn = 0;
     244        if (bus == 0)
     245                devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
     246        else
     247                devfn = PCI_DEV_DEVFUNC(dev);
    225248
    226249        /* Select bus */
     
    333356        uint32_t data, size;
    334357        int mst;
    335         pci_dev_t host = PCI_DEV(0, 0, 0);
     358        pci_dev_t host = HOST_TGT;
    336359
    337360        regs = priv->regs;
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