Changeset 511dc4b in rtems for bsps/arm


Ignore:
Timestamp:
Jun 19, 2018, 7:09:51 AM (18 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
9e3bb45
Parents:
715d616
git-author:
Sebastian Huber <sebastian.huber@…> (06/19/18 07:09:51)
git-committer:
Sebastian Huber <sebastian.huber@…> (06/27/18 06:58:16)
Message:

Rework initialization and interrupt stack support

Statically initialize the interrupt stack area
(_Configuration_Interrupt_stack_area_begin,
_Configuration_Interrupt_stack_area_end, and
_Configuration_Interrupt_stack_size) via <rtems/confdefs.h>. Place the
interrupt stack area in a special section ".rtemsstack.interrupt". Let
BSPs define the optimal placement of this section in their linker
command files (e.g. in a fast on-chip memory).

This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and
CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the
low level initialization code has all information available via global
symbols.

This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define
superfluous, since the interrupt stacks are allocated by confdefs.h for
all architectures. There is no need for BSP-specific linker command
file magic (except the section placement), see previous ARM linker
command file as a bad example.

Remove _CPU_Install_interrupt_stack(). Initialize the hardware
interrupt stack in _CPU_Initialize() if necessary (e.g.
m68k_install_interrupt_stack()).

The optional _CPU_Interrupt_stack_setup() is still useful to customize
the registration of the interrupt stack area in the per-CPU information.

The initialization stack can reuse the interrupt stack, since

  • interrupts are disabled during the sequential system initialization, and
  • the boot_card() function does not return.

This stack resuse saves memory.

Changes per architecture:

arm:

  • Mostly replace the linker symbol based configuration of stacks with the standard <rtems/confdefs.h> configuration via CONFIGURE_INTERRUPT_STACK_SIZE. The size of the FIQ, ABT and UND mode stack is still defined via linker symbols. These modes are rarely used in applications and the default values provided by the BSP should be sufficient in most cases.
  • Remove the bsp_processor_count linker symbol hack used for the SMP support. This is possible since the interrupt stack area is now allocated by the linker and not allocated from the heap. This makes some configure.ac stuff obsolete. Remove the now superfluous BSP variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp.

bfin:

  • Remove unused magic linker command file allocation of initialization stack. Maybe a previous linker command file copy and paste problem? In the start.S the initialization stack is set to a hard coded value.

lm32, m32c, mips, nios2, riscv, sh, v850:

  • Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack.

m68k:

  • Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack.

powerpc:

  • Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack.
  • Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt stack on BSPs using the shared linkcmds.base (replacement for REGION_RWEXTRA).

sparc:

  • Remove the hard coded initialization stack. Use the interrupt stack for the initialization stack on the boot processor. This saves 16KiB of RAM.

Update #3459.

Location:
bsps/arm
Files:
4 deleted
13 edited
1 moved

Legend:

Unmodified
Added
Removed
  • bsps/arm/csb336/start/start.S

    r715d616 r511dc4b  
    99 */
    1010
    11 #include <bsp/linker-symbols.h>
    12 
    13 /* Some standard definitions...*/
    14 .equ PSR_MODE_USR,       0x10
    15 .equ PSR_MODE_FIQ,       0x11
    16 .equ PSR_MODE_IRQ,       0x12
    17 .equ PSR_MODE_SVC,       0x13
    18 .equ PSR_MODE_ABT,       0x17
    19 .equ PSR_MODE_UNDEF,     0x1B
    20 .equ PSR_MODE_SYS,       0x1F
    21 
    22 .equ PSR_I,              0x80
    23 .equ PSR_F,              0x40
    24 .equ PSR_T,              0x20
     11#include <rtems/asm.h>
     12#include <rtems/score/cpu.h>
    2513
    2614.section .bsp_start_text,"ax"
     
    3725         * Since I don't plan to return to the bootloader,
    3826         * I don't have to save the registers.
    39          *
    40          * I'll just set the CPSR for SVC mode, interrupts
    41          * off, and ARM instructions.
    4227         */
    43         mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)
     28
     29        /* Set end of interrupt stack area */
     30        ldr     r7, =_Configuration_Interrupt_stack_area_end
     31
     32        /* Enter FIQ mode and set up the FIQ stack pointer */
     33        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
    4434        msr     cpsr, r0
     35        ldr     r1, =bsp_stack_fiq_size
     36        mov     sp, r7
     37        sub     r7, r7, r1
     38
     39        /* Enter ABT mode and set up the ABT stack pointer */
     40        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
     41        msr     cpsr, r0
     42        ldr     r1, =bsp_stack_abt_size
     43        mov     sp, r7
     44        sub     r7, r7, r1
     45
     46        /* Enter UND mode and set up the UND stack pointer */
     47        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
     48        msr     cpsr, r0
     49        ldr     r1, =bsp_stack_und_size
     50        mov     sp, r7
     51        sub     r7, r7, r1
     52
     53        /* Enter IRQ mode and set up the IRQ stack pointer */
     54        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
     55        msr     cpsr, r0
     56        mov     sp, r7
     57
     58        /*
     59         * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
     60         * (interrupts are disabled).
     61         */
     62        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
     63        msr     cpsr, r0
     64        mov     sp, r7
     65
     66        /* Stay in SVC mode */
    4567
    4668        /* zero the bss */
     
    5375        strlot  r2, [r0], #4
    5476        blo     _bss_init        /* loop while r0 < r1 */
    55 
    56 
    57         /* --- Initialize stack pointer registers */
    58         /* Enter IRQ mode and set up the IRQ stack pointer */
    59         mov     r0, #(PSR_MODE_IRQ | PSR_I | PSR_F)     /* No interrupts */
    60         msr     cpsr, r0
    61         ldr     r1, =bsp_stack_irq_size
    62         ldr     sp, =bsp_stack_irq_begin
    63         add     sp, sp, r1
    64 
    65         /* Enter FIQ mode and set up the FIQ stack pointer */
    66         mov     r0, #(PSR_MODE_FIQ | PSR_I | PSR_F)     /* No interrupts */
    67         msr     cpsr, r0
    68         ldr     r1, =bsp_stack_fiq_size
    69         ldr     sp, =bsp_stack_fiq_begin
    70         add     sp, sp, r1
    71 
    72         /* Enter ABT mode and set up the ABT stack pointer */
    73         mov     r0, #(PSR_MODE_ABT | PSR_I | PSR_F)     /* No interrupts */
    74         msr     cpsr, r0
    75         ldr     r1, =bsp_stack_abt_size
    76         ldr     sp, =bsp_stack_abt_begin
    77         add     sp, sp, r1
    78 
    79         /* Enter UNDEF mode and set up the UNDEF stack pointer */
    80         mov     r0, #(PSR_MODE_UNDEF | PSR_I | PSR_F)     /* No interrupts */
    81         msr     cpsr, r0
    82         ldr     r1, =bsp_stack_und_size
    83         ldr     sp, =bsp_stack_und_begin
    84         add     sp, sp, r1
    85 
    86         /* Set up the SVC stack pointer last and stay in SVC mode */
    87         mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)     /* No interrupts */
    88         msr     cpsr, r0
    89         ldr     r1, =bsp_stack_svc_size
    90         ldr     sp, =bsp_stack_svc_begin
    91         add     sp, sp, r1
    92         sub     sp, sp, #0x64
    9377
    9478        /*
  • bsps/arm/csb337/start/start.S

    r715d616 r511dc4b  
    99*/
    1010
    11 #include <bsp/linker-symbols.h>
    12 
    13 /* Some standard definitions...*/
    14 .equ PSR_MODE_USR,       0x10
    15 .equ PSR_MODE_FIQ,       0x11
    16 .equ PSR_MODE_IRQ,       0x12
    17 .equ PSR_MODE_SVC,       0x13
    18 .equ PSR_MODE_ABT,       0x17
    19 .equ PSR_MODE_UNDEF,     0x1B
    20 .equ PSR_MODE_SYS,       0x1F
    21 
    22 .equ PSR_I,              0x80
    23 .equ PSR_F,              0x40
    24 .equ PSR_T,              0x20
     11#include <rtems/asm.h>
     12#include <rtems/score/cpu.h>
    2513
    2614.text
     
    3018         * Since I don't plan to return to the bootloader,
    3119         * I don't have to save the registers.
    32          *
    33          * I'll just set the CPSR for SVC mode, interrupts
    34          * off, and ARM instructions.
    3520         */
    36         mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)
     21
     22        /* Set end of interrupt stack area */
     23        ldr     r7, =_Configuration_Interrupt_stack_area_end
     24
     25        /* Enter FIQ mode and set up the FIQ stack pointer */
     26        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
    3727        msr     cpsr, r0
     28        ldr     r1, =bsp_stack_fiq_size
     29        mov     sp, r7
     30        sub     r7, r7, r1
     31
     32        /* Enter ABT mode and set up the ABT stack pointer */
     33        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
     34        msr     cpsr, r0
     35        ldr     r1, =bsp_stack_abt_size
     36        mov     sp, r7
     37        sub     r7, r7, r1
     38
     39        /* Enter UND mode and set up the UND stack pointer */
     40        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
     41        msr     cpsr, r0
     42        ldr     r1, =bsp_stack_und_size
     43        mov     sp, r7
     44        sub     r7, r7, r1
     45
     46        /* Enter IRQ mode and set up the IRQ stack pointer */
     47        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
     48        msr     cpsr, r0
     49        mov     sp, r7
     50
     51        /*
     52         * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
     53         * (interrupts are disabled).
     54         */
     55        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
     56        msr     cpsr, r0
     57        mov     sp, r7
     58
     59        /* Stay in SVC mode */
    3860
    3961        /* zero the bss */
     
    4668        strlot  r2, [r0], #4
    4769        blo     _bss_init        /* loop while r0 < r1 */
    48 
    49 
    50         /* --- Initialize stack pointer registers */
    51         /* Enter IRQ mode and set up the IRQ stack pointer */
    52         mov     r0, #(PSR_MODE_IRQ | PSR_I | PSR_F)     /* No interrupts */
    53         msr     cpsr, r0
    54         ldr     r1, =bsp_stack_irq_size
    55         ldr     sp, =bsp_stack_irq_begin
    56         add     sp, sp, r1
    57 
    58         /* Enter FIQ mode and set up the FIQ stack pointer */
    59         mov     r0, #(PSR_MODE_FIQ | PSR_I | PSR_F)     /* No interrupts */
    60         msr     cpsr, r0
    61         ldr     r1, =bsp_stack_fiq_size
    62         ldr     sp, =bsp_stack_fiq_begin
    63         add     sp, sp, r1
    64 
    65         /* Enter ABT mode and set up the ABT stack pointer */
    66         mov     r0, #(PSR_MODE_ABT | PSR_I | PSR_F)     /* No interrupts */
    67         msr     cpsr, r0
    68         ldr     r1, =bsp_stack_abt_size
    69         ldr     sp, =bsp_stack_abt_begin
    70         add     sp, sp, r1
    71 
    72         /* Set up the SVC stack pointer last and stay in SVC mode */
    73         mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)     /* No interrupts */
    74         msr     cpsr, r0
    75         ldr     r1, =bsp_stack_svc_size
    76         ldr     sp, =bsp_stack_svc_begin
    77         add     sp, sp, r1
    78         sub     sp, sp, #0x64
    7970
    8071        /*
  • bsps/arm/edb7312/start/start.S

    r715d616 r511dc4b  
    1313*/
    1414
    15 #include <bsp/linker-symbols.h>
    16 
    17 /* Some standard definitions...*/
    18 
    19 .equ Mode_USR,               0x10
    20 .equ Mode_FIQ,               0x11
    21 .equ Mode_IRQ,               0x12
    22 .equ Mode_SVC,               0x13
    23 .equ Mode_ABT,               0x17
    24 .equ Mode_ABORT,             0x17
    25 .equ Mode_UNDEF,             0x1B
    26 .equ Mode_SYS,               0x1F /*only available on ARM Arch. v4*/
    27 
    28 .equ I_Bit,                  0x80
    29 .equ F_Bit,                  0x40
     15#include <rtems/asm.h>
     16#include <rtems/score/cpu.h>
    3017
    3118.section ".bsp_start_text", "ax"
     
    7360        .globl  _start
    7461_start:
    75         /* store the sp */
    76         mov     r12, sp
     62        /* Set end of interrupt stack area */
     63        ldr     r7, =_Configuration_Interrupt_stack_area_end
     64
     65        /* Enter FIQ mode and set up the FIQ stack pointer */
     66        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
     67        msr     cpsr, r0
     68        ldr     r1, =bsp_stack_fiq_size
     69        mov     sp, r7
     70        sub     r7, r7, r1
     71
     72        /* Enter ABT mode and set up the ABT stack pointer */
     73        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
     74        msr     cpsr, r0
     75        ldr     r1, =bsp_stack_abt_size
     76        mov     sp, r7
     77        sub     r7, r7, r1
     78
     79        /* Enter UND mode and set up the UND stack pointer */
     80        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
     81        msr     cpsr, r0
     82        ldr     r1, =bsp_stack_und_size
     83        mov     sp, r7
     84        sub     r7, r7, r1
     85
     86        /* Enter IRQ mode and set up the IRQ stack pointer */
     87        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
     88        msr     cpsr, r0
     89        mov     sp, r7
     90
     91        /*
     92         * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
     93         * (interrupts are disabled).
     94         */
     95        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
     96        msr     cpsr, r0
     97        mov     sp, r7
     98
     99        /* Stay in SVC mode */
    77100/*
    78101 * Here is the code to initialize the low-level BSP environment
     
    90113        BLO     zi_init
    91114
    92 /* --- Initialise stack pointer registers */
    93 
    94 /* Enter IRQ mode and set up the IRQ stack pointer */
    95     MOV     r0, #Mode_IRQ | I_Bit | F_Bit     /* No interrupts */
    96     MSR     cpsr, r0
    97     ldr     r1, =bsp_stack_irq_size
    98     LDR     sp, =bsp_stack_irq_begin
    99     add     sp, sp, r1
    100     sub     sp, sp, #0x64
    101 
    102 /* Enter FIQ mode and set up the FIQ stack pointer */
    103     MOV     r0, #Mode_FIQ | I_Bit | F_Bit     /* No interrupts */
    104     MSR     cpsr, r0
    105     ldr     r1, =bsp_stack_fiq_size
    106     LDR     sp, =bsp_stack_fiq_begin
    107     add     sp, sp, r1
    108     sub     sp, sp, #0x64
    109 
    110 /* Enter ABT mode and set up the ABT stack pointer */
    111     MOV     r0, #Mode_ABT | I_Bit | F_Bit     /* No interrupts */
    112     MSR     cpsr, r0
    113     ldr     r1, =bsp_stack_abt_size
    114     LDR     sp, =bsp_stack_abt_begin
    115     add     sp, sp, r1
    116     sub     sp, sp, #0x64
    117 
    118 /* Set up the SVC stack pointer last and stay in SVC mode */
    119     MOV     r0, #Mode_SVC | I_Bit | F_Bit     /* No interrupts */
    120     MSR     cpsr, r0
    121     ldr     r1, =bsp_stack_svc_size
    122     LDR     sp, =bsp_stack_svc_begin
    123     add     sp, sp, r1
    124     sub     sp, sp, #0x64
    125 
    126         /* save the original registers */
    127         stmdb   sp!, {r4-r12, lr}
    128 
    129115/* --- Now we enter the C code */
    130116
    131117        mov     r0, #0
    132118        bl      boot_card
    133 
    134         ldmia   sp!, {r4-r12, lr}
    135         mov     sp, r12
    136         mov     pc, lr
  • bsps/arm/gumstix/start/start.S

    r715d616 r511dc4b  
    88 */
    99
    10 #include <bsp/linker-symbols.h>
    11 
    12 /* Some standard definitions...*/
    13 .equ PSR_MODE_USR,       0x10
    14 .equ PSR_MODE_FIQ,       0x11
    15 .equ PSR_MODE_IRQ,       0x12
    16 .equ PSR_MODE_SVC,       0x13
    17 .equ PSR_MODE_ABT,       0x17
    18 .equ PSR_MODE_UNDEF,     0x1B
    19 .equ PSR_MODE_SYS,       0x1F
    20 
    21 .equ PSR_I,              0x80
    22 .equ PSR_F,              0x40
    23 .equ PSR_T,              0x20
     10#include <rtems/asm.h>
     11#include <rtems/score/cpu.h>
    2412
    2513.text
     
    2917         * Since I don't plan to return to the bootloader,
    3018         * I don't have to save the registers.
    31          *
    32          * I'll just set the CPSR for SVC mode, interrupts
    33          * off, and ARM instructions.
    3419         */
    35         mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)
     20
     21        /* Set end of interrupt stack area */
     22        ldr     r7, =_Configuration_Interrupt_stack_area_end
     23
     24        /* Enter FIQ mode and set up the FIQ stack pointer */
     25        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
    3626        msr     cpsr, r0
     27        ldr     r1, =bsp_stack_fiq_size
     28        mov     sp, r7
     29        sub     r7, r7, r1
    3730
     31        /* Enter ABT mode and set up the ABT stack pointer */
     32        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
     33        msr     cpsr, r0
     34        ldr     r1, =bsp_stack_abt_size
     35        mov     sp, r7
     36        sub     r7, r7, r1
     37
     38        /* Enter UND mode and set up the UND stack pointer */
     39        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
     40        msr     cpsr, r0
     41        ldr     r1, =bsp_stack_und_size
     42        mov     sp, r7
     43        sub     r7, r7, r1
     44
     45        /* Enter IRQ mode and set up the IRQ stack pointer */
     46        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
     47        msr     cpsr, r0
     48        mov     sp, r7
     49
     50        /*
     51         * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
     52         * (interrupts are disabled).
     53         */
     54        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
     55        msr     cpsr, r0
     56        mov     sp, r7
     57
     58        /* Stay in SVC mode */
    3859
    3960        /* zero the bss */
     
    4667        strlot  r2, [r0], #4
    4768        blo     _bss_init        /* loop while r0 < r1 */
    48 
    49         /* --- Initialize stack pointer registers */
    50         /* Enter IRQ mode and set up the IRQ stack pointer */
    51         mov     r0, #(PSR_MODE_IRQ | PSR_I | PSR_F)     /* No interrupts */
    52         msr     cpsr, r0
    53         ldr     r1, =bsp_stack_irq_size
    54         ldr     sp, =bsp_stack_irq_begin
    55         add     sp, sp, r1
    56 
    57         /* Enter FIQ mode and set up the FIQ stack pointer */
    58         mov     r0, #(PSR_MODE_FIQ | PSR_I | PSR_F)     /* No interrupts */
    59         msr     cpsr, r0
    60         ldr     r1, =bsp_stack_fiq_size
    61         ldr     sp, =bsp_stack_fiq_begin
    62         add     sp, sp, r1
    63 
    64         /* Enter ABT mode and set up the ABT stack pointer */
    65         mov     r0, #(PSR_MODE_ABT | PSR_I | PSR_F)     /* No interrupts */
    66         msr     cpsr, r0
    67         ldr     r1, =bsp_stack_abt_size
    68         ldr     sp, =bsp_stack_abt_begin
    69         add     sp, sp, r1
    70 
    71         /* Set up the SVC stack pointer last and stay in SVC mode */
    72         mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)     /* No interrupts */
    73         msr     cpsr, r0
    74         ldr     r1, =bsp_stack_und_size
    75         ldr     sp, =bsp_stack_und_begin
    76         add     sp, sp, r1
    77         sub     sp, sp, #0x64
    7869
    7970        /*
  • bsps/arm/imx/start/linkcmds.imx7

    r715d616 r511dc4b  
    2323REGION_ALIAS ("REGION_NOCACHE_LOAD", NOCACHE);
    2424
    25 bsp_processor_count = DEFINED (bsp_processor_count) ? bsp_processor_count : 2;
    26 
    27 bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 4096;
    2825bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024;
    2926
  • bsps/arm/include/bsp/linker-symbols.h

    r715d616 r511dc4b  
    4444#endif
    4545
    46 LINKER_SYMBOL(bsp_stack_irq_begin)
    47 LINKER_SYMBOL(bsp_stack_irq_end)
    48 LINKER_SYMBOL(bsp_stack_irq_size)
    49 
    50 LINKER_SYMBOL(bsp_stack_fiq_begin)
    51 LINKER_SYMBOL(bsp_stack_fiq_end)
    52 LINKER_SYMBOL(bsp_stack_irq_size)
    53 
    54 LINKER_SYMBOL(bsp_stack_abt_begin)
    55 LINKER_SYMBOL(bsp_stack_abt_end)
     46LINKER_SYMBOL(bsp_stack_fiq_size)
    5647LINKER_SYMBOL(bsp_stack_abt_size)
    57 
    58 LINKER_SYMBOL(bsp_stack_und_begin)
    59 LINKER_SYMBOL(bsp_stack_und_end)
    6048LINKER_SYMBOL(bsp_stack_und_size)
    61 
    62 LINKER_SYMBOL(bsp_stack_hyp_begin)
    63 LINKER_SYMBOL(bsp_stack_hyp_end)
    6449LINKER_SYMBOL(bsp_stack_hyp_size)
    65 
    66 LINKER_SYMBOL(bsp_stack_svc_begin)
    67 LINKER_SYMBOL(bsp_stack_svc_end)
    68 LINKER_SYMBOL(bsp_stack_svc_size)
    6950
    7051LINKER_SYMBOL(bsp_section_start_begin)
     
    157138  __attribute__((section(".bsp_noload_nocache." # subsection)))
    158139
    159 LINKER_SYMBOL(bsp_processor_count)
    160 
    161140/** @} */
    162141
  • bsps/arm/raspberrypi/start/bspsmp.c

    r715d616 r511dc4b  
    5858uint32_t _CPU_SMP_Initialize(void)
    5959{
    60   uint32_t cpu_count = (uint32_t)bsp_processor_count;
    61 
    62   if ( cpu_count > 4 )
    63     cpu_count = 4;
    64 
    65   return cpu_count;
     60  return 4;
    6661}
    6762
  • bsps/arm/raspberrypi/start/linkcmds

    r715d616 r511dc4b  
    4242}
    4343
    44 bsp_processor_count = DEFINED (bsp_processor_count) ? bsp_processor_count : @RASPBERRYPI_CPUS@;
    45 
    4644REGION_ALIAS ("REGION_START", RAM);
    4745REGION_ALIAS ("REGION_VECTOR", VECTOR_RAM);
     
    6260REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM);
    6361
    64 bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 3008;
    6562bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024;
    6663
  • bsps/arm/rtl22xx/start/start.S

    r715d616 r511dc4b  
    99*/
    1010
    11 #include <bsp/linker-symbols.h>
    12 
    13 /* Some standard definitions...*/
    14 .equ PSR_MODE_USR,       0x10
    15 .equ PSR_MODE_FIQ,       0x11
    16 .equ PSR_MODE_IRQ,       0x12
    17 .equ PSR_MODE_SVC,       0x13
    18 .equ PSR_MODE_ABT,       0x17
    19 .equ PSR_MODE_UNDEF,     0x1B
    20 .equ PSR_MODE_SYS,       0x1F
    21 
    22 .equ PSR_I,              0x80
    23 .equ PSR_F,              0x40
    24 .equ PSR_T,              0x20
     11#include <rtems/asm.h>
     12#include <rtems/score/cpu.h>
    2513
    2614.text
     
    3119         * Since I don't plan to return to the bootloader,
    3220         * I don't have to save the registers.
    33          *
    34          * I'll just set the CPSR for SVC mode, interrupts
    35          * off, and ARM instructions.
    3621         */
    3722
    38         /* --- Initialize stack pointer registers */
    39         /* Enter IRQ mode and set up the IRQ stack pointer */
    40         mov     r0, #(PSR_MODE_IRQ | PSR_I | PSR_F)     /* No interrupts */
    41         bic     r0, r0, #PSR_T
    42         msr     cpsr, r0
    43         ldr     r1, =bsp_stack_irq_size
    44         ldr     sp, =bsp_stack_irq_begin
    45         add     sp, sp, r1
     23        /* Set end of interrupt stack area */
     24        ldr     r7, =_Configuration_Interrupt_stack_area_end
    4625
    4726        /* Enter FIQ mode and set up the FIQ stack pointer */
    48         mov     r0, #(PSR_MODE_FIQ | PSR_I | PSR_F)     /* No interrupts */
    49         bic     r0, r0, #PSR_T
     27        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
    5028        msr     cpsr, r0
    5129        ldr     r1, =bsp_stack_fiq_size
    52         ldr     sp, =bsp_stack_fiq_begin
    53         add     sp, sp, r1
     30        mov     sp, r7
     31        sub     r7, r7, r1
    5432
    5533        /* Enter ABT mode and set up the ABT stack pointer */
    56         mov     r0, #(PSR_MODE_ABT | PSR_I | PSR_F)     /* No interrupts */
    57         bic     r0, r0, #PSR_T
     34        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
    5835        msr     cpsr, r0
    59         bic     r0, r0, #PSR_T
    6036        ldr     r1, =bsp_stack_abt_size
    61         ldr     sp, =bsp_stack_abt_begin
    62         add     sp, sp, r1
     37        mov     sp, r7
     38        sub     r7, r7, r1
    6339
    64         /* Set up the SVC stack pointer last and stay in SVC mode */
    65         mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)     /* No interrupts */
    66         bic     r0, r0, #PSR_T
     40        /* Enter UND mode and set up the UND stack pointer */
     41        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
    6742        msr     cpsr, r0
    68         ldr     r1, =bsp_stack_svc_size
    69         ldr     sp, =bsp_stack_svc_begin
    70         add     sp, sp, r1
    71         sub     sp, sp, #0x64
     43        ldr     r1, =bsp_stack_und_size
     44        mov     sp, r7
     45        sub     r7, r7, r1
     46
     47        /* Enter IRQ mode and set up the IRQ stack pointer */
     48        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
     49        msr     cpsr, r0
     50        mov     sp, r7
     51
     52        /*
     53         * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
     54         * (interrupts are disabled).
     55         */
     56        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
     57        msr     cpsr, r0
     58        mov     sp, r7
     59
     60        /* Stay in SVC mode */
    7261
    7362        /*
  • bsps/arm/shared/start/arm-a9mpcore-smp.c

    r715d616 r511dc4b  
    11/*
    2  * Copyright (c) 2013-2015 embedded brains GmbH.  All rights reserved.
     2 * Copyright (c) 2013, 2018 embedded brains GmbH.  All rights reserved.
    33 *
    44 *  embedded brains GmbH
     
    2020
    2121#include <bsp/irq.h>
    22 #include <bsp/linker-symbols.h>
    2322
    2423static void bsp_inter_processor_interrupt(void *arg)
     
    2928uint32_t _CPU_SMP_Initialize(void)
    3029{
    31   uint32_t hardware_count = arm_gic_irq_processor_count();
    32   uint32_t linker_count = (uint32_t) bsp_processor_count;
    33 
    34   return hardware_count <= linker_count ? hardware_count : linker_count;
     30  return arm_gic_irq_processor_count();
    3531}
    3632
  • bsps/arm/shared/start/linkcmds.base

    r715d616 r511dc4b  
    4646bsp_stack_fiq_size = ALIGN (bsp_stack_fiq_size, bsp_stack_align);
    4747
    48 bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 0;
    49 bsp_stack_irq_size = ALIGN (bsp_stack_irq_size, bsp_stack_align);
    50 
    51 bsp_stack_svc_size = DEFINED (bsp_stack_svc_size) ? bsp_stack_svc_size : 0;
    52 bsp_stack_svc_size = ALIGN (bsp_stack_svc_size, bsp_stack_align);
    53 
    5448bsp_stack_und_size = DEFINED (bsp_stack_und_size) ? bsp_stack_und_size : 0;
    5549bsp_stack_und_size = ALIGN (bsp_stack_und_size, bsp_stack_align);
     
    5751bsp_stack_hyp_size = DEFINED (bsp_stack_hyp_size) ? bsp_stack_hyp_size : 0;
    5852bsp_stack_hyp_size = ALIGN (bsp_stack_hyp_size, bsp_stack_align);
    59 
    60 bsp_stack_main_size = DEFINED (bsp_stack_main_size) ? bsp_stack_main_size : 0;
    61 bsp_stack_main_size = ALIGN (bsp_stack_main_size, bsp_stack_align);
    62 
    63 bsp_stack_all_size = bsp_stack_abt_size + bsp_stack_fiq_size + bsp_stack_irq_size + bsp_stack_svc_size + bsp_stack_und_size + bsp_stack_hyp_size + bsp_stack_main_size;
    64 
    65 bsp_processor_count = DEFINED (bsp_processor_count) ? bsp_processor_count : 1;
    6653
    6754MEMORY {
     
    298285        .vector : ALIGN_WITH_INPUT {
    299286                bsp_section_vector_begin = .;
    300 
    301287                . = . + DEFINED (bsp_vector_table_in_start_section) ? 0 : bsp_vector_table_size;
    302 
    303                 . = ALIGN (bsp_stack_align);
    304 
    305                 bsp_stack_irq_begin = .;
    306                 . = . + bsp_stack_irq_size;
    307                 bsp_stack_irq_end = .;
    308 
    309                 bsp_stack_svc_begin = .;
    310                 . = . + bsp_stack_svc_size;
    311                 bsp_stack_svc_end = .;
    312 
    313                 bsp_stack_fiq_begin = .;
    314                 . = . + bsp_stack_fiq_size;
    315                 bsp_stack_fiq_end = .;
    316 
    317                 bsp_stack_und_begin = .;
    318                 . = . + bsp_stack_und_size;
    319                 bsp_stack_und_end = .;
    320 
    321                 bsp_stack_hyp_begin = .;
    322                 . = . + bsp_stack_hyp_size;
    323                 bsp_stack_hyp_end = .;
    324 
    325                 bsp_stack_abt_begin = .;
    326                 . = . + bsp_stack_abt_size;
    327                 bsp_stack_abt_end = .;
    328 
    329                 bsp_stack_main_begin = .;
    330                 . = . + bsp_stack_main_size;
    331                 bsp_stack_main_end = .;
    332 
    333                 bsp_stack_secondary_processors_begin = .;
    334                 . = . + (bsp_processor_count - 1) * bsp_stack_all_size;
    335                 bsp_stack_secondary_processors_end = .;
    336 
    337                 *(.bsp_vector)
    338288        } > REGION_VECTOR AT > REGION_VECTOR
    339289        .rtemsstack (NOLOAD) : {
  • bsps/arm/shared/start/start.S

    r715d616 r511dc4b  
    66
    77/*
    8  * Copyright (c) 2008, 2016 embedded brains GmbH.  All rights reserved.
     8 * Copyright (c) 2008, 2018 embedded brains GmbH.  All rights reserved.
    99 *
    1010 *  embedded brains GmbH
     
    2020
    2121#include <rtems/asm.h>
    22 #include <rtems/system.h>       
    2322#include <rtems/score/percpu.h>
    24        
     23
    2524#include <bspopts.h>
    2625#include <bsp/irq.h>
    27 #include <bsp/linker-symbols.h>
    28 
    29         /* External symbols */
    30         .extern bsp_reset
    31         .extern boot_card
    32         .extern bsp_start_hook_0
    33         .extern bsp_start_hook_1
    34         .extern bsp_stack_irq_end
    35         .extern bsp_stack_fiq_end
    36         .extern bsp_stack_abt_end
    37         .extern bsp_stack_und_end
    38         .extern bsp_stack_svc_end
    39 #ifdef RTEMS_SMP
    40         .extern bsp_stack_all_size
    41 #endif
    42         .extern _ARMV4_Exception_undef_default
    43         .extern _ARMV4_Exception_swi_default
    44         .extern _ARMV4_Exception_data_abort_default
    45         .extern _ARMV4_Exception_pref_abort_default
    46         .extern _ARMV4_Exception_reserved_default
    47         .extern _ARMV4_Exception_interrupt
    48         .extern _ARMV4_Exception_fiq_default
    49         .extern _ARMV7M_Exception_default
    50 
    51 #ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
    52         .extern bsp_start_init_registers_core
    53         .extern bsp_start_init_registers_banked_fiq
    54         .extern bsp_start_init_registers_vfp
    55 #endif
    56 
    57 #ifdef BSP_START_IN_HYP_SUPPORT
    58         .extern bsp_start_arm_drop_hyp_mode
    59         .globl  bsp_start_hyp_vector_table_begin
    60 #endif
    6126
    6227        /* Global symbols */
     
    6631        .globl  bsp_start_vector_table_size
    6732        .globl  bsp_vector_table_size
     33
     34        .section        ".bsp_start_text", "ax"
     35
     36#if defined(ARM_MULTILIB_ARCH_V4)
     37
    6838        .globl  bsp_start_hook_0_done
    6939
    70         .section        ".bsp_start_text", "ax"
    71 
    72 #if defined(ARM_MULTILIB_ARCH_V4)
     40#ifdef BSP_START_IN_HYP_SUPPORT
     41        .globl  bsp_start_hyp_vector_table_begin
     42#endif
    7343
    7444        .arm
     
    209179        mcr     p15, 0, r1, c13, c0, 4
    210180
    211         /* Calculate stack offset */
    212         ldr     r1, =bsp_stack_all_size
    213         mul     r1, r7
    214 #endif
    215 
    216         mrs     r4, cpsr        /* save original procesor status value  */
     181#endif
     182
     183        /* Calculate interrupt stack area end for current processor */
     184        ldr     r1, =_Configuration_Interrupt_stack_size
     185#ifdef RTEMS_SMP
     186        add     r7, #1
     187        mul     r1, r1, r7
     188#endif
     189        ldr     r2, =_Configuration_Interrupt_stack_area_begin
     190        add     r7, r1, r2
     191
     192        /* Save original CPSR value */
     193        mrs     r4, cpsr
     194
    217195#ifdef BSP_START_IN_HYP_SUPPORT
    218196        orr     r0, r4, #(ARM_PSR_I | ARM_PSR_F)
     
    223201        bne     bsp_start_skip_hyp_svc_switch
    224202
    225         /* Boot loader stats kernel in HYP mode, switch to SVC necessary */
    226         ldr     sp, =bsp_stack_hyp_end
    227 #ifdef RTEMS_SMP
    228         add     sp, r1
    229 #endif
     203        /* Boot loader starts kernel in HYP mode, switch to SVC necessary */
     204        ldr     r1, =bsp_stack_hyp_size
     205        mov     sp, r7
     206        sub     r7, r7, r1
    230207        bl      bsp_start_arm_drop_hyp_mode
    231208
    232209bsp_start_skip_hyp_svc_switch:
    233210#endif
    234         /*
    235          * Set SVC mode, disable interrupts and enable ARM instructions.
    236         */
    237         mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
     211        /* Initialize stack pointer registers for the various modes */
     212
     213        /* Enter FIQ mode and set up the FIQ stack pointer */
     214        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
    238215        msr     cpsr, r0
    239 
    240         /* Initialize stack pointer registers for the various modes */
     216        ldr     r1, =bsp_stack_fiq_size
     217        mov     sp, r7
     218        sub     r7, r7, r1
     219
     220#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
     221        bl bsp_start_init_registers_banked_fiq
     222#endif
     223
     224        /* Enter ABT mode and set up the ABT stack pointer */
     225        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
     226        msr     cpsr, r0
     227        ldr     r1, =bsp_stack_abt_size
     228        mov     sp, r7
     229        sub     r7, r7, r1
     230
     231        /* Enter UND mode and set up the UND stack pointer */
     232        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
     233        msr     cpsr, r0
     234        ldr     r1, =bsp_stack_und_size
     235        mov     sp, r7
     236        sub     r7, r7, r1
    241237
    242238        /* Enter IRQ mode and set up the IRQ stack pointer */
    243239        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
    244240        msr     cpsr, r0
    245         ldr     sp, =bsp_stack_irq_end
    246 #ifdef RTEMS_SMP
    247         add     sp, r1
    248 #endif
    249 
    250         /* Enter FIQ mode and set up the FIQ stack pointer */
    251         mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
    252         msr     cpsr, r0
    253         ldr     sp, =bsp_stack_fiq_end
    254 #ifdef RTEMS_SMP
    255         add     sp, r1
    256 #endif
    257 
    258 #ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
    259         bl bsp_start_init_registers_banked_fiq
    260 #endif
    261 
    262         /* Enter ABT mode and set up the ABT stack pointer */
    263         mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
    264         msr     cpsr, r0
    265         ldr     sp, =bsp_stack_abt_end
    266 #ifdef RTEMS_SMP
    267         add     sp, r1
    268 #endif
    269 
    270         /* Enter UND mode and set up the UND stack pointer */
    271         mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
    272         msr     cpsr, r0
    273         ldr     sp, =bsp_stack_und_end
    274 #ifdef RTEMS_SMP
    275         add     sp, r1
    276 #endif
    277 
    278         /* Enter SVC mode and set up the SVC stack pointer */
     241        mov     sp, r7
     242
     243        /*
     244         * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
     245         * (interrupts are disabled).
     246         */
    279247        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
    280248        msr     cpsr, r0
    281         ldr     sp, =bsp_stack_svc_end
    282 #ifdef RTEMS_SMP
    283         add     sp, r1
    284 #endif
     249        mov     sp, r7
    285250
    286251        /* Stay in SVC mode */
     
    334299        SWITCH_FROM_ARM_TO_THUMB        r0
    335300
    336         mov     r0, r4          /* original cpsr value */
     301        mov     r0, r4          /* original CPSR value */
    337302        mov     r1, r5          /* machine type number or ~0 for DT boot */
    338303        mov     r2, r6          /* physical address of ATAGs or DTB */
     
    386351        .syntax unified
    387352
    388         .extern bsp_stack_main_end
    389 
    390353        .thumb
    391354
    392355bsp_start_vector_table_begin:
    393356
    394         .word   bsp_stack_main_end
     357        .word   _Configuration_Interrupt_stack_area_end
    395358        .word   _start /* Reset */
    396359        .word   _ARMV7M_Exception_default /* NMI */
     
    442405#endif /* ARM_MULTILIB_VFP */
    443406
    444         ldr     sp, =bsp_stack_main_end
     407        ldr     sp, =_Configuration_Interrupt_stack_area_end
    445408        ldr     lr, =bsp_start_hook_0_done + 1
    446409        b       bsp_start_hook_0
  • bsps/arm/smdk2410/start/start.S

    r715d616 r511dc4b  
    99 */
    1010
    11 #include <bsp/linker-symbols.h>
    12 
    13 /* Some standard definitions...*/
    14 .equ PSR_MODE_USR,       0x10
    15 .equ PSR_MODE_FIQ,       0x11
    16 .equ PSR_MODE_IRQ,       0x12
    17 .equ PSR_MODE_SVC,       0x13
    18 .equ PSR_MODE_ABT,       0x17
    19 .equ PSR_MODE_UNDEF,     0x1B
    20 .equ PSR_MODE_SYS,       0x1F
    21 
    22 .equ PSR_I,              0x80
    23 .equ PSR_F,              0x40
    24 .equ PSR_T,              0x20
     11#include <rtems/asm.h>
     12#include <rtems/score/cpu.h>
    2513
    2614.text
     
    6654         * Since I don't plan to return to the bootloader,
    6755         * I don't have to save the registers.
    68          *
    69          * I'll just set the CPSR for SVC mode, interrupts
    70          * off, and ARM instructions.
    7156         */
    72         mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)
    73         msr     cpsr, r0
    7457
    75         /* --- Initialize stack pointer registers */
    76         /* Enter IRQ mode and set up the IRQ stack pointer */
    77         mov     r0, #(PSR_MODE_IRQ | PSR_I | PSR_F)     /* No interrupts */
    78         msr     cpsr, r0
    79         ldr     r1, =bsp_stack_irq_size
    80         ldr     sp, =bsp_stack_irq_begin
    81         add     sp, sp, r1
     58        /* Set end of interrupt stack area */
     59        ldr     r7, =_Configuration_Interrupt_stack_area_end
    8260
    8361        /* Enter FIQ mode and set up the FIQ stack pointer */
    84         mov     r0, #(PSR_MODE_FIQ | PSR_I | PSR_F)     /* No interrupts */
     62        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
    8563        msr     cpsr, r0
    8664        ldr     r1, =bsp_stack_fiq_size
    87         ldr     sp, =bsp_stack_fiq_begin
    88         add     sp, sp, r1
     65        mov     sp, r7
     66        sub     r7, r7, r1
    8967
    9068        /* Enter ABT mode and set up the ABT stack pointer */
    91         mov     r0, #(PSR_MODE_ABT | PSR_I | PSR_F)     /* No interrupts */
     69        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
    9270        msr     cpsr, r0
    9371        ldr     r1, =bsp_stack_abt_size
    94         ldr     sp, =bsp_stack_abt_begin
    95         add     sp, sp, r1
     72        mov     sp, r7
     73        sub     r7, r7, r1
    9674
    97         /* Set up the SVC stack pointer last and stay in SVC mode */
    98         mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)     /* No interrupts */
     75        /* Enter UND mode and set up the UND stack pointer */
     76        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
    9977        msr     cpsr, r0
    100         ldr     r1, =bsp_stack_svc_size
    101         ldr     sp, =bsp_stack_svc_begin
    102         add     sp, sp, r1
    103         sub     sp, sp, #0x64
     78        ldr     r1, =bsp_stack_und_size
     79        mov     sp, r7
     80        sub     r7, r7, r1
    10481
     82        /* Enter IRQ mode and set up the IRQ stack pointer */
     83        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
     84        msr     cpsr, r0
     85        mov     sp, r7
     86
     87        /*
     88         * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
     89         * (interrupts are disabled).
     90         */
     91        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
     92        msr     cpsr, r0
     93        mov     sp, r7
     94
     95        /* Stay in SVC mode */
    10596
    10697        /* disable mmu, I and D caches*/
  • bsps/arm/xilinx-zynq/start/linkcmds.in

    r715d616 r511dc4b  
    66   NOCACHE   : ORIGIN = @ZYNQ_RAM_ORIGIN_AVAILABLE@ + @ZYNQ_RAM_LENGTH_AVAILABLE@ - @ZYNQ_RAM_NOCACHE_LENGTH@, LENGTH = @ZYNQ_RAM_NOCACHE_LENGTH@
    77}
    8 
    9 bsp_processor_count = DEFINED (bsp_processor_count) ? bsp_processor_count : @ZYNQ_CPUS@;
    108
    119REGION_ALIAS ("REGION_START",          RAM);
     
    2725REGION_ALIAS ("REGION_NOCACHE_LOAD",   NOCACHE);
    2826
    29 bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 4096;
    3027bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024;
    3128
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