Changeset 511dc4b in rtems


Ignore:
Timestamp:
06/19/18 07:09:51 (5 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
5, master
Children:
9e3bb45
Parents:
715d616
git-author:
Sebastian Huber <sebastian.huber@…> (06/19/18 07:09:51)
git-committer:
Sebastian Huber <sebastian.huber@…> (06/27/18 06:58:16)
Message:

Rework initialization and interrupt stack support

Statically initialize the interrupt stack area
(_Configuration_Interrupt_stack_area_begin,
_Configuration_Interrupt_stack_area_end, and
_Configuration_Interrupt_stack_size) via <rtems/confdefs.h>. Place the
interrupt stack area in a special section ".rtemsstack.interrupt". Let
BSPs define the optimal placement of this section in their linker
command files (e.g. in a fast on-chip memory).

This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and
CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the
low level initialization code has all information available via global
symbols.

This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define
superfluous, since the interrupt stacks are allocated by confdefs.h for
all architectures. There is no need for BSP-specific linker command
file magic (except the section placement), see previous ARM linker
command file as a bad example.

Remove _CPU_Install_interrupt_stack(). Initialize the hardware
interrupt stack in _CPU_Initialize() if necessary (e.g.
m68k_install_interrupt_stack()).

The optional _CPU_Interrupt_stack_setup() is still useful to customize
the registration of the interrupt stack area in the per-CPU information.

The initialization stack can reuse the interrupt stack, since

  • interrupts are disabled during the sequential system initialization, and
  • the boot_card() function does not return.

This stack resuse saves memory.

Changes per architecture:

arm:

  • Mostly replace the linker symbol based configuration of stacks with the standard <rtems/confdefs.h> configuration via CONFIGURE_INTERRUPT_STACK_SIZE. The size of the FIQ, ABT and UND mode stack is still defined via linker symbols. These modes are rarely used in applications and the default values provided by the BSP should be sufficient in most cases.
  • Remove the bsp_processor_count linker symbol hack used for the SMP support. This is possible since the interrupt stack area is now allocated by the linker and not allocated from the heap. This makes some configure.ac stuff obsolete. Remove the now superfluous BSP variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp.

bfin:

  • Remove unused magic linker command file allocation of initialization stack. Maybe a previous linker command file copy and paste problem? In the start.S the initialization stack is set to a hard coded value.

lm32, m32c, mips, nios2, riscv, sh, v850:

  • Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack.

m68k:

  • Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack.

powerpc:

  • Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack.
  • Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt stack on BSPs using the shared linkcmds.base (replacement for REGION_RWEXTRA).

sparc:

  • Remove the hard coded initialization stack. Use the interrupt stack for the initialization stack on the boot processor. This saves 16KiB of RAM.

Update #3459.

Files:
4 deleted
161 edited
1 moved

Legend:

Unmodified
Added
Removed

  • bsps/arm/csb336/start/start.S

    r715d616 r511dc4b  
    99 */
    1010
    11 #include <bsp/linker-symbols.h>
    12 
    13 /* Some standard definitions...*/
    14 .equ PSR_MODE_USR,       0x10
    15 .equ PSR_MODE_FIQ,       0x11
    16 .equ PSR_MODE_IRQ,       0x12
    17 .equ PSR_MODE_SVC,       0x13
    18 .equ PSR_MODE_ABT,       0x17
    19 .equ PSR_MODE_UNDEF,     0x1B
    20 .equ PSR_MODE_SYS,       0x1F
    21 
    22 .equ PSR_I,              0x80
    23 .equ PSR_F,              0x40
    24 .equ PSR_T,              0x20
     11#include <rtems/asm.h>
     12#include <rtems/score/cpu.h>
    2513
    2614.section .bsp_start_text,"ax"
    … …  
    3725         * Since I don't plan to return to the bootloader,
    3826         * I don't have to save the registers.
    39          *
    40          * I'll just set the CPSR for SVC mode, interrupts
    41          * off, and ARM instructions.
    4227         */
    43         mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)
     28
     29        /* Set end of interrupt stack area */
     30        ldr     r7, =_Configuration_Interrupt_stack_area_end
     31
     32        /* Enter FIQ mode and set up the FIQ stack pointer */
     33        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
    4434        msr     cpsr, r0
     35        ldr     r1, =bsp_stack_fiq_size
     36        mov     sp, r7
     37        sub     r7, r7, r1
     38
     39        /* Enter ABT mode and set up the ABT stack pointer */
     40        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
     41        msr     cpsr, r0
     42        ldr     r1, =bsp_stack_abt_size
     43        mov     sp, r7
     44        sub     r7, r7, r1
     45
     46        /* Enter UND mode and set up the UND stack pointer */
     47        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
     48        msr     cpsr, r0
     49        ldr     r1, =bsp_stack_und_size
     50        mov     sp, r7
     51        sub     r7, r7, r1
     52
     53        /* Enter IRQ mode and set up the IRQ stack pointer */
     54        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
     55        msr     cpsr, r0
     56        mov     sp, r7
     57
     58        /*
     59         * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
     60         * (interrupts are disabled).
     61         */
     62        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
     63        msr     cpsr, r0
     64        mov     sp, r7
     65
     66        /* Stay in SVC mode */
    4567
    4668        /* zero the bss */
    … …  
    5375        strlot  r2, [r0], #4
    5476        blo     _bss_init        /* loop while r0 < r1 */
    55 
    56 
    57         /* --- Initialize stack pointer registers */
    58         /* Enter IRQ mode and set up the IRQ stack pointer */
    59         mov     r0, #(PSR_MODE_IRQ | PSR_I | PSR_F)     /* No interrupts */
    60         msr     cpsr, r0
    61         ldr     r1, =bsp_stack_irq_size
    62         ldr     sp, =bsp_stack_irq_begin
    63         add     sp, sp, r1
    64 
    65         /* Enter FIQ mode and set up the FIQ stack pointer */
    66         mov     r0, #(PSR_MODE_FIQ | PSR_I | PSR_F)     /* No interrupts */
    67         msr     cpsr, r0
    68         ldr     r1, =bsp_stack_fiq_size
    69         ldr     sp, =bsp_stack_fiq_begin
    70         add     sp, sp, r1
    71 
    72         /* Enter ABT mode and set up the ABT stack pointer */
    73         mov     r0, #(PSR_MODE_ABT | PSR_I | PSR_F)     /* No interrupts */
    74         msr     cpsr, r0
    75         ldr     r1, =bsp_stack_abt_size
    76         ldr     sp, =bsp_stack_abt_begin
    77         add     sp, sp, r1
    78 
    79         /* Enter UNDEF mode and set up the UNDEF stack pointer */
    80         mov     r0, #(PSR_MODE_UNDEF | PSR_I | PSR_F)     /* No interrupts */
    81         msr     cpsr, r0
    82         ldr     r1, =bsp_stack_und_size
    83         ldr     sp, =bsp_stack_und_begin
    84         add     sp, sp, r1
    85 
    86         /* Set up the SVC stack pointer last and stay in SVC mode */
    87         mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)     /* No interrupts */
    88         msr     cpsr, r0
    89         ldr     r1, =bsp_stack_svc_size
    90         ldr     sp, =bsp_stack_svc_begin
    91         add     sp, sp, r1
    92         sub     sp, sp, #0x64
    9377
    9478        /*

  • bsps/arm/csb337/start/start.S

    r715d616 r511dc4b  
    99*/
    1010
    11 #include <bsp/linker-symbols.h>
    12 
    13 /* Some standard definitions...*/
    14 .equ PSR_MODE_USR,       0x10
    15 .equ PSR_MODE_FIQ,       0x11
    16 .equ PSR_MODE_IRQ,       0x12
    17 .equ PSR_MODE_SVC,       0x13
    18 .equ PSR_MODE_ABT,       0x17
    19 .equ PSR_MODE_UNDEF,     0x1B
    20 .equ PSR_MODE_SYS,       0x1F
    21 
    22 .equ PSR_I,              0x80
    23 .equ PSR_F,              0x40
    24 .equ PSR_T,              0x20
     11#include <rtems/asm.h>
     12#include <rtems/score/cpu.h>
    2513
    2614.text
    … …  
    3018         * Since I don't plan to return to the bootloader,
    3119         * I don't have to save the registers.
    32          *
    33          * I'll just set the CPSR for SVC mode, interrupts
    34          * off, and ARM instructions.
    3520         */
    36         mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)
     21
     22        /* Set end of interrupt stack area */
     23        ldr     r7, =_Configuration_Interrupt_stack_area_end
     24
     25        /* Enter FIQ mode and set up the FIQ stack pointer */
     26        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
    3727        msr     cpsr, r0
     28        ldr     r1, =bsp_stack_fiq_size
     29        mov     sp, r7
     30        sub     r7, r7, r1
     31
     32        /* Enter ABT mode and set up the ABT stack pointer */
     33        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
     34        msr     cpsr, r0
     35        ldr     r1, =bsp_stack_abt_size
     36        mov     sp, r7
     37        sub     r7, r7, r1
     38
     39        /* Enter UND mode and set up the UND stack pointer */
     40        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
     41        msr     cpsr, r0
     42        ldr     r1, =bsp_stack_und_size
     43        mov     sp, r7
     44        sub     r7, r7, r1
     45
     46        /* Enter IRQ mode and set up the IRQ stack pointer */
     47        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
     48        msr     cpsr, r0
     49        mov     sp, r7
     50
     51        /*
     52         * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
     53         * (interrupts are disabled).
     54         */
     55        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
     56        msr     cpsr, r0
     57        mov     sp, r7
     58
     59        /* Stay in SVC mode */
    3860
    3961        /* zero the bss */
    … …  
    4668        strlot  r2, [r0], #4
    4769        blo     _bss_init        /* loop while r0 < r1 */
    48 
    49 
    50         /* --- Initialize stack pointer registers */
    51         /* Enter IRQ mode and set up the IRQ stack pointer */
    52         mov     r0, #(PSR_MODE_IRQ | PSR_I | PSR_F)     /* No interrupts */
    53         msr     cpsr, r0
    54         ldr     r1, =bsp_stack_irq_size
    55         ldr     sp, =bsp_stack_irq_begin
    56         add     sp, sp, r1
    57 
    58         /* Enter FIQ mode and set up the FIQ stack pointer */
    59         mov     r0, #(PSR_MODE_FIQ | PSR_I | PSR_F)     /* No interrupts */
    60         msr     cpsr, r0
    61         ldr     r1, =bsp_stack_fiq_size
    62         ldr     sp, =bsp_stack_fiq_begin
    63         add     sp, sp, r1
    64 
    65         /* Enter ABT mode and set up the ABT stack pointer */
    66         mov     r0, #(PSR_MODE_ABT | PSR_I | PSR_F)     /* No interrupts */
    67         msr     cpsr, r0
    68         ldr     r1, =bsp_stack_abt_size
    69         ldr     sp, =bsp_stack_abt_begin
    70         add     sp, sp, r1
    71 
    72         /* Set up the SVC stack pointer last and stay in SVC mode */
    73         mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)     /* No interrupts */
    74         msr     cpsr, r0
    75         ldr     r1, =bsp_stack_svc_size
    76         ldr     sp, =bsp_stack_svc_begin
    77         add     sp, sp, r1
    78         sub     sp, sp, #0x64
    7970
    8071        /*

  • bsps/arm/edb7312/start/start.S

    r715d616 r511dc4b  
    1313*/
    1414
    15 #include <bsp/linker-symbols.h>
    16 
    17 /* Some standard definitions...*/
    18 
    19 .equ Mode_USR,               0x10
    20 .equ Mode_FIQ,               0x11
    21 .equ Mode_IRQ,               0x12
    22 .equ Mode_SVC,               0x13
    23 .equ Mode_ABT,               0x17
    24 .equ Mode_ABORT,             0x17
    25 .equ Mode_UNDEF,             0x1B
    26 .equ Mode_SYS,               0x1F /*only available on ARM Arch. v4*/
    27 
    28 .equ I_Bit,                  0x80
    29 .equ F_Bit,                  0x40
     15#include <rtems/asm.h>
     16#include <rtems/score/cpu.h>
    3017
    3118.section ".bsp_start_text", "ax"
    … …  
    7360        .globl  _start
    7461_start:
    75         /* store the sp */
    76         mov     r12, sp
     62        /* Set end of interrupt stack area */
     63        ldr     r7, =_Configuration_Interrupt_stack_area_end
     64
     65        /* Enter FIQ mode and set up the FIQ stack pointer */
     66        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
     67        msr     cpsr, r0
     68        ldr     r1, =bsp_stack_fiq_size
     69        mov     sp, r7
     70        sub     r7, r7, r1
     71
     72        /* Enter ABT mode and set up the ABT stack pointer */
     73        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
     74        msr     cpsr, r0
     75        ldr     r1, =bsp_stack_abt_size
     76        mov     sp, r7
     77        sub     r7, r7, r1
     78
     79        /* Enter UND mode and set up the UND stack pointer */
     80        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
     81        msr     cpsr, r0
     82        ldr     r1, =bsp_stack_und_size
     83        mov     sp, r7
     84        sub     r7, r7, r1
     85
     86        /* Enter IRQ mode and set up the IRQ stack pointer */
     87        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
     88        msr     cpsr, r0
     89        mov     sp, r7
     90
     91        /*
     92         * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
     93         * (interrupts are disabled).
     94         */
     95        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
     96        msr     cpsr, r0
     97        mov     sp, r7
     98
     99        /* Stay in SVC mode */
    77100/*
    78101 * Here is the code to initialize the low-level BSP environment
    … …  
    90113        BLO     zi_init
    91114
    92 /* --- Initialise stack pointer registers */
    93 
    94 /* Enter IRQ mode and set up the IRQ stack pointer */
    95     MOV     r0, #Mode_IRQ | I_Bit | F_Bit     /* No interrupts */
    96     MSR     cpsr, r0
    97     ldr     r1, =bsp_stack_irq_size
    98     LDR     sp, =bsp_stack_irq_begin
    99     add     sp, sp, r1
    100     sub     sp, sp, #0x64
    101 
    102 /* Enter FIQ mode and set up the FIQ stack pointer */
    103     MOV     r0, #Mode_FIQ | I_Bit | F_Bit     /* No interrupts */
    104     MSR     cpsr, r0
    105     ldr     r1, =bsp_stack_fiq_size
    106     LDR     sp, =bsp_stack_fiq_begin
    107     add     sp, sp, r1
    108     sub     sp, sp, #0x64
    109 
    110 /* Enter ABT mode and set up the ABT stack pointer */
    111     MOV     r0, #Mode_ABT | I_Bit | F_Bit     /* No interrupts */
    112     MSR     cpsr, r0
    113     ldr     r1, =bsp_stack_abt_size
    114     LDR     sp, =bsp_stack_abt_begin
    115     add     sp, sp, r1
    116     sub     sp, sp, #0x64
    117 
    118 /* Set up the SVC stack pointer last and stay in SVC mode */
    119     MOV     r0, #Mode_SVC | I_Bit | F_Bit     /* No interrupts */
    120     MSR     cpsr, r0
    121     ldr     r1, =bsp_stack_svc_size
    122     LDR     sp, =bsp_stack_svc_begin
    123     add     sp, sp, r1
    124     sub     sp, sp, #0x64
    125 
    126         /* save the original registers */
    127         stmdb   sp!, {r4-r12, lr}
    128 
    129115/* --- Now we enter the C code */
    130116
    131117        mov     r0, #0
    132118        bl      boot_card
    133 
    134         ldmia   sp!, {r4-r12, lr}
    135         mov     sp, r12
    136         mov     pc, lr

  • bsps/arm/gumstix/start/start.S

    r715d616 r511dc4b  
    88 */
    99
    10 #include <bsp/linker-symbols.h>
    11 
    12 /* Some standard definitions...*/
    13 .equ PSR_MODE_USR,       0x10
    14 .equ PSR_MODE_FIQ,       0x11
    15 .equ PSR_MODE_IRQ,       0x12
    16 .equ PSR_MODE_SVC,       0x13
    17 .equ PSR_MODE_ABT,       0x17
    18 .equ PSR_MODE_UNDEF,     0x1B
    19 .equ PSR_MODE_SYS,       0x1F
    20 
    21 .equ PSR_I,              0x80
    22 .equ PSR_F,              0x40
    23 .equ PSR_T,              0x20
     10#include <rtems/asm.h>
     11#include <rtems/score/cpu.h>
    2412
    2513.text
    … …  
    2917         * Since I don't plan to return to the bootloader,
    3018         * I don't have to save the registers.
    31          *
    32          * I'll just set the CPSR for SVC mode, interrupts
    33          * off, and ARM instructions.
    3419         */
    35         mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)
     20
     21        /* Set end of interrupt stack area */
     22        ldr     r7, =_Configuration_Interrupt_stack_area_end
     23
     24        /* Enter FIQ mode and set up the FIQ stack pointer */
     25        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
    3626        msr     cpsr, r0
     27        ldr     r1, =bsp_stack_fiq_size
     28        mov     sp, r7
     29        sub     r7, r7, r1
    3730
     31        /* Enter ABT mode and set up the ABT stack pointer */
     32        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
     33        msr     cpsr, r0
     34        ldr     r1, =bsp_stack_abt_size
     35        mov     sp, r7
     36        sub     r7, r7, r1
     37
     38        /* Enter UND mode and set up the UND stack pointer */
     39        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
     40        msr     cpsr, r0
     41        ldr     r1, =bsp_stack_und_size
     42        mov     sp, r7
     43        sub     r7, r7, r1
     44
     45        /* Enter IRQ mode and set up the IRQ stack pointer */
     46        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
     47        msr     cpsr, r0
     48        mov     sp, r7
     49
     50        /*
     51         * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
     52         * (interrupts are disabled).
     53         */
     54        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
     55        msr     cpsr, r0
     56        mov     sp, r7
     57
     58        /* Stay in SVC mode */
    3859
    3960        /* zero the bss */
    … …  
    4667        strlot  r2, [r0], #4
    4768        blo     _bss_init        /* loop while r0 < r1 */
    48 
    49         /* --- Initialize stack pointer registers */
    50         /* Enter IRQ mode and set up the IRQ stack pointer */
    51         mov     r0, #(PSR_MODE_IRQ | PSR_I | PSR_F)     /* No interrupts */
    52         msr     cpsr, r0
    53         ldr     r1, =bsp_stack_irq_size
    54         ldr     sp, =bsp_stack_irq_begin
    55         add     sp, sp, r1
    56 
    57         /* Enter FIQ mode and set up the FIQ stack pointer */
    58         mov     r0, #(PSR_MODE_FIQ | PSR_I | PSR_F)     /* No interrupts */
    59         msr     cpsr, r0
    60         ldr     r1, =bsp_stack_fiq_size
    61         ldr     sp, =bsp_stack_fiq_begin
    62         add     sp, sp, r1
    63 
    64         /* Enter ABT mode and set up the ABT stack pointer */
    65         mov     r0, #(PSR_MODE_ABT | PSR_I | PSR_F)     /* No interrupts */
    66         msr     cpsr, r0
    67         ldr     r1, =bsp_stack_abt_size
    68         ldr     sp, =bsp_stack_abt_begin
    69         add     sp, sp, r1
    70 
    71         /* Set up the SVC stack pointer last and stay in SVC mode */
    72         mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)     /* No interrupts */
    73         msr     cpsr, r0
    74         ldr     r1, =bsp_stack_und_size
    75         ldr     sp, =bsp_stack_und_begin
    76         add     sp, sp, r1
    77         sub     sp, sp, #0x64
    7869
    7970        /*

  • bsps/arm/imx/start/linkcmds.imx7

    r715d616 r511dc4b  
    2323REGION_ALIAS ("REGION_NOCACHE_LOAD", NOCACHE);
    2424
    25 bsp_processor_count = DEFINED (bsp_processor_count) ? bsp_processor_count : 2;
    26 
    27 bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 4096;
    2825bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024;
    2926

  • bsps/arm/include/bsp/linker-symbols.h

    r715d616 r511dc4b  
    4444#endif
    4545
    46 LINKER_SYMBOL(bsp_stack_irq_begin)
    47 LINKER_SYMBOL(bsp_stack_irq_end)
    48 LINKER_SYMBOL(bsp_stack_irq_size)
    49 
    50 LINKER_SYMBOL(bsp_stack_fiq_begin)
    51 LINKER_SYMBOL(bsp_stack_fiq_end)
    52 LINKER_SYMBOL(bsp_stack_irq_size)
    53 
    54 LINKER_SYMBOL(bsp_stack_abt_begin)
    55 LINKER_SYMBOL(bsp_stack_abt_end)
     46LINKER_SYMBOL(bsp_stack_fiq_size)
    5647LINKER_SYMBOL(bsp_stack_abt_size)
    57 
    58 LINKER_SYMBOL(bsp_stack_und_begin)
    59 LINKER_SYMBOL(bsp_stack_und_end)
    6048LINKER_SYMBOL(bsp_stack_und_size)
    61 
    62 LINKER_SYMBOL(bsp_stack_hyp_begin)
    63 LINKER_SYMBOL(bsp_stack_hyp_end)
    6449LINKER_SYMBOL(bsp_stack_hyp_size)
    65 
    66 LINKER_SYMBOL(bsp_stack_svc_begin)
    67 LINKER_SYMBOL(bsp_stack_svc_end)
    68 LINKER_SYMBOL(bsp_stack_svc_size)
    6950
    7051LINKER_SYMBOL(bsp_section_start_begin)
    … …  
    157138  __attribute__((section(".bsp_noload_nocache." # subsection)))
    158139
    159 LINKER_SYMBOL(bsp_processor_count)
    160 
    161140/** @} */
    162141

  • bsps/arm/raspberrypi/start/bspsmp.c

    r715d616 r511dc4b  
    5858uint32_t _CPU_SMP_Initialize(void)
    5959{
    60   uint32_t cpu_count = (uint32_t)bsp_processor_count;
    61 
    62   if ( cpu_count > 4 )
    63     cpu_count = 4;
    64 
    65   return cpu_count;
     60  return 4;
    6661}
    6762

  • bsps/arm/raspberrypi/start/linkcmds

    r715d616 r511dc4b  
    4242}
    4343
    44 bsp_processor_count = DEFINED (bsp_processor_count) ? bsp_processor_count : @RASPBERRYPI_CPUS@;
    45 
    4644REGION_ALIAS ("REGION_START", RAM);
    4745REGION_ALIAS ("REGION_VECTOR", VECTOR_RAM);
    … …  
    6260REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM);
    6361
    64 bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 3008;
    6562bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024;
    6663

  • bsps/arm/rtl22xx/start/start.S

    r715d616 r511dc4b  
    99*/
    1010
    11 #include <bsp/linker-symbols.h>
    12 
    13 /* Some standard definitions...*/
    14 .equ PSR_MODE_USR,       0x10
    15 .equ PSR_MODE_FIQ,       0x11
    16 .equ PSR_MODE_IRQ,       0x12
    17 .equ PSR_MODE_SVC,       0x13
    18 .equ PSR_MODE_ABT,       0x17
    19 .equ PSR_MODE_UNDEF,     0x1B
    20 .equ PSR_MODE_SYS,       0x1F
    21 
    22 .equ PSR_I,              0x80
    23 .equ PSR_F,              0x40
    24 .equ PSR_T,              0x20
     11#include <rtems/asm.h>
     12#include <rtems/score/cpu.h>
    2513
    2614.text
    … …  
    3119         * Since I don't plan to return to the bootloader,
    3220         * I don't have to save the registers.
    33          *
    34          * I'll just set the CPSR for SVC mode, interrupts
    35          * off, and ARM instructions.
    3621         */
    3722
    38         /* --- Initialize stack pointer registers */
    39         /* Enter IRQ mode and set up the IRQ stack pointer */
    40         mov     r0, #(PSR_MODE_IRQ | PSR_I | PSR_F)     /* No interrupts */
    41         bic     r0, r0, #PSR_T
    42         msr     cpsr, r0
    43         ldr     r1, =bsp_stack_irq_size
    44         ldr     sp, =bsp_stack_irq_begin
    45         add     sp, sp, r1
     23        /* Set end of interrupt stack area */
     24        ldr     r7, =_Configuration_Interrupt_stack_area_end
    4625
    4726        /* Enter FIQ mode and set up the FIQ stack pointer */
    48         mov     r0, #(PSR_MODE_FIQ | PSR_I | PSR_F)     /* No interrupts */
    49         bic     r0, r0, #PSR_T
     27        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
    5028        msr     cpsr, r0
    5129        ldr     r1, =bsp_stack_fiq_size
    52         ldr     sp, =bsp_stack_fiq_begin
    53         add     sp, sp, r1
     30        mov     sp, r7
     31        sub     r7, r7, r1
    5432
    5533        /* Enter ABT mode and set up the ABT stack pointer */
    56         mov     r0, #(PSR_MODE_ABT | PSR_I | PSR_F)     /* No interrupts */
    57         bic     r0, r0, #PSR_T
     34        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
    5835        msr     cpsr, r0
    59         bic     r0, r0, #PSR_T
    6036        ldr     r1, =bsp_stack_abt_size
    61         ldr     sp, =bsp_stack_abt_begin
    62         add     sp, sp, r1
     37        mov     sp, r7
     38        sub     r7, r7, r1
    6339
    64         /* Set up the SVC stack pointer last and stay in SVC mode */
    65         mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)     /* No interrupts */
    66         bic     r0, r0, #PSR_T
     40        /* Enter UND mode and set up the UND stack pointer */
     41        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
    6742        msr     cpsr, r0
    68         ldr     r1, =bsp_stack_svc_size
    69         ldr     sp, =bsp_stack_svc_begin
    70         add     sp, sp, r1
    71         sub     sp, sp, #0x64
     43        ldr     r1, =bsp_stack_und_size
     44        mov     sp, r7
     45        sub     r7, r7, r1
     46
     47        /* Enter IRQ mode and set up the IRQ stack pointer */
     48        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
     49        msr     cpsr, r0
     50        mov     sp, r7
     51
     52        /*
     53         * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
     54         * (interrupts are disabled).
     55         */
     56        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
     57        msr     cpsr, r0
     58        mov     sp, r7
     59
     60        /* Stay in SVC mode */
    7261
    7362        /*

  • bsps/arm/shared/start/arm-a9mpcore-smp.c

    r715d616 r511dc4b  
    11/*
    2  * Copyright (c) 2013-2015 embedded brains GmbH.  All rights reserved.
     2 * Copyright (c) 2013, 2018 embedded brains GmbH.  All rights reserved.
    33 *
    44 *  embedded brains GmbH
    … …  
    2020
    2121#include <bsp/irq.h>
    22 #include <bsp/linker-symbols.h>
    2322
    2423static void bsp_inter_processor_interrupt(void *arg)
    … …  
    2928uint32_t _CPU_SMP_Initialize(void)
    3029{
    31   uint32_t hardware_count = arm_gic_irq_processor_count();
    32   uint32_t linker_count = (uint32_t) bsp_processor_count;
    33 
    34   return hardware_count <= linker_count ? hardware_count : linker_count;
     30  return arm_gic_irq_processor_count();
    3531}
    3632

  • bsps/arm/shared/start/linkcmds.base

    r715d616 r511dc4b  
    4646bsp_stack_fiq_size = ALIGN (bsp_stack_fiq_size, bsp_stack_align);
    4747
    48 bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 0;
    49 bsp_stack_irq_size = ALIGN (bsp_stack_irq_size, bsp_stack_align);
    50 
    51 bsp_stack_svc_size = DEFINED (bsp_stack_svc_size) ? bsp_stack_svc_size : 0;
    52 bsp_stack_svc_size = ALIGN (bsp_stack_svc_size, bsp_stack_align);
    53 
    5448bsp_stack_und_size = DEFINED (bsp_stack_und_size) ? bsp_stack_und_size : 0;
    5549bsp_stack_und_size = ALIGN (bsp_stack_und_size, bsp_stack_align);
    … …  
    5751bsp_stack_hyp_size = DEFINED (bsp_stack_hyp_size) ? bsp_stack_hyp_size : 0;
    5852bsp_stack_hyp_size = ALIGN (bsp_stack_hyp_size, bsp_stack_align);
    59 
    60 bsp_stack_main_size = DEFINED (bsp_stack_main_size) ? bsp_stack_main_size : 0;
    61 bsp_stack_main_size = ALIGN (bsp_stack_main_size, bsp_stack_align);
    62 
    63 bsp_stack_all_size = bsp_stack_abt_size + bsp_stack_fiq_size + bsp_stack_irq_size + bsp_stack_svc_size + bsp_stack_und_size + bsp_stack_hyp_size + bsp_stack_main_size;
    64 
    65 bsp_processor_count = DEFINED (bsp_processor_count) ? bsp_processor_count : 1;
    6653
    6754MEMORY {
    … …  
    298285        .vector : ALIGN_WITH_INPUT {
    299286                bsp_section_vector_begin = .;
    300 
    301287                . = . + DEFINED (bsp_vector_table_in_start_section) ? 0 : bsp_vector_table_size;
    302 
    303                 . = ALIGN (bsp_stack_align);
    304 
    305                 bsp_stack_irq_begin = .;
    306                 . = . + bsp_stack_irq_size;
    307                 bsp_stack_irq_end = .;
    308 
    309                 bsp_stack_svc_begin = .;
    310                 . = . + bsp_stack_svc_size;
    311                 bsp_stack_svc_end = .;
    312 
    313                 bsp_stack_fiq_begin = .;
    314                 . = . + bsp_stack_fiq_size;
    315                 bsp_stack_fiq_end = .;
    316 
    317                 bsp_stack_und_begin = .;
    318                 . = . + bsp_stack_und_size;
    319                 bsp_stack_und_end = .;
    320 
    321                 bsp_stack_hyp_begin = .;
    322                 . = . + bsp_stack_hyp_size;
    323                 bsp_stack_hyp_end = .;
    324 
    325                 bsp_stack_abt_begin = .;
    326                 . = . + bsp_stack_abt_size;
    327                 bsp_stack_abt_end = .;
    328 
    329                 bsp_stack_main_begin = .;
    330                 . = . + bsp_stack_main_size;
    331                 bsp_stack_main_end = .;
    332 
    333                 bsp_stack_secondary_processors_begin = .;
    334                 . = . + (bsp_processor_count - 1) * bsp_stack_all_size;
    335                 bsp_stack_secondary_processors_end = .;
    336 
    337                 *(.bsp_vector)
    338288        } > REGION_VECTOR AT > REGION_VECTOR
    339289        .rtemsstack (NOLOAD) : {

  • bsps/arm/shared/start/start.S

    r715d616 r511dc4b  
    66
    77/*
    8  * Copyright (c) 2008, 2016 embedded brains GmbH.  All rights reserved.
     8 * Copyright (c) 2008, 2018 embedded brains GmbH.  All rights reserved.
    99 *
    1010 *  embedded brains GmbH
    … …  
    2020
    2121#include <rtems/asm.h>
    22 #include <rtems/system.h>       
    2322#include <rtems/score/percpu.h>
    24        
     23
    2524#include <bspopts.h>
    2625#include <bsp/irq.h>
    27 #include <bsp/linker-symbols.h>
    28 
    29         /* External symbols */
    30         .extern bsp_reset
    31         .extern boot_card
    32         .extern bsp_start_hook_0
    33         .extern bsp_start_hook_1
    34         .extern bsp_stack_irq_end
    35         .extern bsp_stack_fiq_end
    36         .extern bsp_stack_abt_end
    37         .extern bsp_stack_und_end
    38         .extern bsp_stack_svc_end
    39 #ifdef RTEMS_SMP
    40         .extern bsp_stack_all_size
    41 #endif
    42         .extern _ARMV4_Exception_undef_default
    43         .extern _ARMV4_Exception_swi_default
    44         .extern _ARMV4_Exception_data_abort_default
    45         .extern _ARMV4_Exception_pref_abort_default
    46         .extern _ARMV4_Exception_reserved_default
    47         .extern _ARMV4_Exception_interrupt
    48         .extern _ARMV4_Exception_fiq_default
    49         .extern _ARMV7M_Exception_default
    50 
    51 #ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
    52         .extern bsp_start_init_registers_core
    53         .extern bsp_start_init_registers_banked_fiq
    54         .extern bsp_start_init_registers_vfp
    55 #endif
    56 
    57 #ifdef BSP_START_IN_HYP_SUPPORT
    58         .extern bsp_start_arm_drop_hyp_mode
    59         .globl  bsp_start_hyp_vector_table_begin
    60 #endif
    6126
    6227        /* Global symbols */
    … …  
    6631        .globl  bsp_start_vector_table_size
    6732        .globl  bsp_vector_table_size
     33
     34        .section        ".bsp_start_text", "ax"
     35
     36#if defined(ARM_MULTILIB_ARCH_V4)
     37
    6838        .globl  bsp_start_hook_0_done
    6939
    70         .section        ".bsp_start_text", "ax"
    71 
    72 #if defined(ARM_MULTILIB_ARCH_V4)
     40#ifdef BSP_START_IN_HYP_SUPPORT
     41        .globl  bsp_start_hyp_vector_table_begin
     42#endif
    7343
    7444        .arm
    … …  
    209179        mcr     p15, 0, r1, c13, c0, 4
    210180
    211         /* Calculate stack offset */
    212         ldr     r1, =bsp_stack_all_size
    213         mul     r1, r7
    214 #endif
    215 
    216         mrs     r4, cpsr        /* save original procesor status value  */
     181#endif
     182
     183        /* Calculate interrupt stack area end for current processor */
     184        ldr     r1, =_Configuration_Interrupt_stack_size
     185#ifdef RTEMS_SMP
     186        add     r7, #1
     187        mul     r1, r1, r7
     188#endif
     189        ldr     r2, =_Configuration_Interrupt_stack_area_begin
     190        add     r7, r1, r2
     191
     192        /* Save original CPSR value */
     193        mrs     r4, cpsr
     194
    217195#ifdef BSP_START_IN_HYP_SUPPORT
    218196        orr     r0, r4, #(ARM_PSR_I | ARM_PSR_F)
    … …  
    223201        bne     bsp_start_skip_hyp_svc_switch
    224202
    225         /* Boot loader stats kernel in HYP mode, switch to SVC necessary */
    226         ldr     sp, =bsp_stack_hyp_end
    227 #ifdef RTEMS_SMP
    228         add     sp, r1
    229 #endif
     203        /* Boot loader starts kernel in HYP mode, switch to SVC necessary */
     204        ldr     r1, =bsp_stack_hyp_size
     205        mov     sp, r7
     206        sub     r7, r7, r1
    230207        bl      bsp_start_arm_drop_hyp_mode
    231208
    232209bsp_start_skip_hyp_svc_switch:
    233210#endif
    234         /*
    235          * Set SVC mode, disable interrupts and enable ARM instructions.
    236         */
    237         mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
     211        /* Initialize stack pointer registers for the various modes */
     212
     213        /* Enter FIQ mode and set up the FIQ stack pointer */
     214        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
    238215        msr     cpsr, r0
    239 
    240         /* Initialize stack pointer registers for the various modes */
     216        ldr     r1, =bsp_stack_fiq_size
     217        mov     sp, r7
     218        sub     r7, r7, r1
     219
     220#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
     221        bl bsp_start_init_registers_banked_fiq
     222#endif
     223
     224        /* Enter ABT mode and set up the ABT stack pointer */
     225        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
     226        msr     cpsr, r0
     227        ldr     r1, =bsp_stack_abt_size
     228        mov     sp, r7
     229        sub     r7, r7, r1
     230
     231        /* Enter UND mode and set up the UND stack pointer */
     232        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
     233        msr     cpsr, r0
     234        ldr     r1, =bsp_stack_und_size
     235        mov     sp, r7
     236        sub     r7, r7, r1
    241237
    242238        /* Enter IRQ mode and set up the IRQ stack pointer */
    243239        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
    244240        msr     cpsr, r0
    245         ldr     sp, =bsp_stack_irq_end
    246 #ifdef RTEMS_SMP
    247         add     sp, r1
    248 #endif
    249 
    250         /* Enter FIQ mode and set up the FIQ stack pointer */
    251         mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
    252         msr     cpsr, r0
    253         ldr     sp, =bsp_stack_fiq_end
    254 #ifdef RTEMS_SMP
    255         add     sp, r1
    256 #endif
    257 
    258 #ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
    259         bl bsp_start_init_registers_banked_fiq
    260 #endif
    261 
    262         /* Enter ABT mode and set up the ABT stack pointer */
    263         mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
    264         msr     cpsr, r0
    265         ldr     sp, =bsp_stack_abt_end
    266 #ifdef RTEMS_SMP
    267         add     sp, r1
    268 #endif
    269 
    270         /* Enter UND mode and set up the UND stack pointer */
    271         mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
    272         msr     cpsr, r0
    273         ldr     sp, =bsp_stack_und_end
    274 #ifdef RTEMS_SMP
    275         add     sp, r1
    276 #endif
    277 
    278         /* Enter SVC mode and set up the SVC stack pointer */
     241        mov     sp, r7
     242
     243        /*
     244         * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
     245         * (interrupts are disabled).
     246         */
    279247        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
    280248        msr     cpsr, r0
    281         ldr     sp, =bsp_stack_svc_end
    282 #ifdef RTEMS_SMP
    283         add     sp, r1
    284 #endif
     249        mov     sp, r7
    285250
    286251        /* Stay in SVC mode */
    … …  
    334299        SWITCH_FROM_ARM_TO_THUMB        r0
    335300
    336         mov     r0, r4          /* original cpsr value */
     301        mov     r0, r4          /* original CPSR value */
    337302        mov     r1, r5          /* machine type number or ~0 for DT boot */
    338303        mov     r2, r6          /* physical address of ATAGs or DTB */
    … …  
    386351        .syntax unified
    387352
    388         .extern bsp_stack_main_end
    389 
    390353        .thumb
    391354
    392355bsp_start_vector_table_begin:
    393356
    394         .word   bsp_stack_main_end
     357        .word   _Configuration_Interrupt_stack_area_end
    395358        .word   _start /* Reset */
    396359        .word   _ARMV7M_Exception_default /* NMI */
    … …  
    442405#endif /* ARM_MULTILIB_VFP */
    443406
    444         ldr     sp, =bsp_stack_main_end
     407        ldr     sp, =_Configuration_Interrupt_stack_area_end
    445408        ldr     lr, =bsp_start_hook_0_done + 1
    446409        b       bsp_start_hook_0

  • bsps/arm/smdk2410/start/start.S

    r715d616 r511dc4b  
    99 */
    1010
    11 #include <bsp/linker-symbols.h>
    12 
    13 /* Some standard definitions...*/
    14 .equ PSR_MODE_USR,       0x10
    15 .equ PSR_MODE_FIQ,       0x11
    16 .equ PSR_MODE_IRQ,       0x12
    17 .equ PSR_MODE_SVC,       0x13
    18 .equ PSR_MODE_ABT,       0x17
    19 .equ PSR_MODE_UNDEF,     0x1B
    20 .equ PSR_MODE_SYS,       0x1F
    21 
    22 .equ PSR_I,              0x80
    23 .equ PSR_F,              0x40
    24 .equ PSR_T,              0x20
     11#include <rtems/asm.h>
     12#include <rtems/score/cpu.h>
    2513
    2614.text
    … …  
    6654         * Since I don't plan to return to the bootloader,
    6755         * I don't have to save the registers.
    68          *
    69          * I'll just set the CPSR for SVC mode, interrupts
    70          * off, and ARM instructions.
    7156         */
    72         mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)
    73         msr     cpsr, r0
    7457
    75         /* --- Initialize stack pointer registers */
    76         /* Enter IRQ mode and set up the IRQ stack pointer */
    77         mov     r0, #(PSR_MODE_IRQ | PSR_I | PSR_F)     /* No interrupts */
    78         msr     cpsr, r0
    79         ldr     r1, =bsp_stack_irq_size
    80         ldr     sp, =bsp_stack_irq_begin
    81         add     sp, sp, r1
     58        /* Set end of interrupt stack area */
     59        ldr     r7, =_Configuration_Interrupt_stack_area_end
    8260
    8361        /* Enter FIQ mode and set up the FIQ stack pointer */
    84         mov     r0, #(PSR_MODE_FIQ | PSR_I | PSR_F)     /* No interrupts */
     62        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
    8563        msr     cpsr, r0
    8664        ldr     r1, =bsp_stack_fiq_size
    87         ldr     sp, =bsp_stack_fiq_begin
    88         add     sp, sp, r1
     65        mov     sp, r7
     66        sub     r7, r7, r1
    8967
    9068        /* Enter ABT mode and set up the ABT stack pointer */
    91         mov     r0, #(PSR_MODE_ABT | PSR_I | PSR_F)     /* No interrupts */
     69        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
    9270        msr     cpsr, r0
    9371        ldr     r1, =bsp_stack_abt_size
    94         ldr     sp, =bsp_stack_abt_begin
    95         add     sp, sp, r1
     72        mov     sp, r7
     73        sub     r7, r7, r1
    9674
    97         /* Set up the SVC stack pointer last and stay in SVC mode */
    98         mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)     /* No interrupts */
     75        /* Enter UND mode and set up the UND stack pointer */
     76        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
    9977        msr     cpsr, r0
    100         ldr     r1, =bsp_stack_svc_size
    101         ldr     sp, =bsp_stack_svc_begin
    102         add     sp, sp, r1
    103         sub     sp, sp, #0x64
     78        ldr     r1, =bsp_stack_und_size
     79        mov     sp, r7
     80        sub     r7, r7, r1
    10481
     82        /* Enter IRQ mode and set up the IRQ stack pointer */
     83        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
     84        msr     cpsr, r0
     85        mov     sp, r7
     86
     87        /*
     88         * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
     89         * (interrupts are disabled).
     90         */
     91        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
     92        msr     cpsr, r0
     93        mov     sp, r7
     94
     95        /* Stay in SVC mode */
    10596
    10697        /* disable mmu, I and D caches*/

  • bsps/arm/xilinx-zynq/start/linkcmds.in

    r715d616 r511dc4b  
    66   NOCACHE   : ORIGIN = @ZYNQ_RAM_ORIGIN_AVAILABLE@ + @ZYNQ_RAM_LENGTH_AVAILABLE@ - @ZYNQ_RAM_NOCACHE_LENGTH@, LENGTH = @ZYNQ_RAM_NOCACHE_LENGTH@
    77}
    8 
    9 bsp_processor_count = DEFINED (bsp_processor_count) ? bsp_processor_count : @ZYNQ_CPUS@;
    108
    119REGION_ALIAS ("REGION_START",          RAM);
    … …  
    2725REGION_ALIAS ("REGION_NOCACHE_LOAD",   NOCACHE);
    2826
    29 bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 4096;
    3027bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024;
    3128

  • bsps/bfin/TLL6527M/start/linkcmds

    r715d616 r511dc4b  
    1212_RamSize    = DEFINED(_RamSize)   ? _RamSize : 0x04000000;
    1313_HeapSize   = DEFINED(_HeapSize)  ? _HeapSize : 0x10000;
    14 _StackSize  = DEFINED(_StackSize) ? _StackSize : 0x10000;
    1514
    1615MEMORY
    … …  
    124123        *(COMMON)
    125124        . = ALIGN (64);
    126         _stack_init = .;
    127         . += _StackSize;
    128125        _clear_end = .;
    129126         _end = .;
    … …  
    171168  .debug_typenames 0 : { *(.debug_typenames) }
    172169  .debug_varnames  0 : { *(.debug_varnames) }
    173   /*.stack 0x80000 : { _stack = .; *(.stack) }*/
    174170  /* These must appear regardless of  .  */   
    175171}

  • bsps/bfin/bf537Stamp/start/linkcmds

    r715d616 r511dc4b  
    1616_RamSize = DEFINED(_RamSize) ? _RamSize : 0x03400000;
    1717_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0;
    18 _StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
    1918
    2019MEMORY
    … …  
    132131        *(COMMON)
    133132        . = ALIGN (64);
    134         _stack_init = .;
    135         . += _StackSize;
    136133        _clear_end = .;
    137134         _end = .;
    … …  
    179176  .debug_typenames 0 : { *(.debug_typenames) }
    180177  .debug_varnames  0 : { *(.debug_varnames) }
    181   /*.stack 0x80000 : { _stack = .; *(.stack) }*/
    182178  /* These must appear regardless of  .  */   
    183179}

  • bsps/bfin/eZKit533/start/linkcmds

    r715d616 r511dc4b  
    1212_RamSize = DEFINED(_RamSize) ? _RamSize : 0x01000000;
    1313_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0;
    14 _StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
    1514
    1615MEMORY
    … …  
    121120        *(COMMON)
    122121        . = ALIGN (64);
    123         _stack_init = .;
    124         . += _StackSize;
    125122        _clear_end = .;
    126123         _end = .;
    … …  
    168165  .debug_typenames 0 : { *(.debug_typenames) }
    169166  .debug_varnames  0 : { *(.debug_varnames) }
    170   /*.stack 0x80000 : { _stack = .; *(.stack) }*/
    171167  /* These must appear regardless of  .  */   
    172168}

  • bsps/lm32/lm32_evr/start/linkcmds

    r715d616 r511dc4b  
    1313RamSize = DEFINED(RamSize) ? RamSize : 32M;
    1414HeapSize = DEFINED(HeapSize) ? HeapSize : 2M;
    15 _StackSize = DEFINED(_StackSize) ? _StackSize : 0x2000;
    16 
    17 PROVIDE (__stack = 0);
     15
    1816MEMORY {
    1917        ebr     : ORIGIN = 0x04000000 , LENGTH = 32k
    … …  
    250248  PROVIDE (end = .);
    251249
    252   . += _StackSize;
    253   _fstack = .;
    254 
    255250    . = ALIGN (16);
    256     _stack_init = .;
    257251    _clear_end = .;
    258252

  • bsps/lm32/milkymist/start/linkcmds

    r715d616 r511dc4b  
    1313RamSize = DEFINED(RamSize) ? RamSize : 128M;
    1414HeapSize = DEFINED(HeapSize) ? HeapSize : 92M;
    15 _StackSize = DEFINED(_StackSize) ? _StackSize : 0x2000;
    16 
    17 PROVIDE (__stack = 0);
     15
    1816MEMORY {
    1917        sdram   : ORIGIN = 0x40000000 , LENGTH = 128M
    … …  
    249247  PROVIDE (end = .);
    250248
    251   . += _StackSize;
    252   _fstack = .;
    253 
    254249    . = ALIGN (16);
    255     _stack_init = .;
    256250    _clear_end = .;
    257251  } > sdram

  • bsps/lm32/shared/start/start.S

    r715d616 r511dc4b  
    127127        nop
    128128        /* Initialize stack pointer */
    129         mvhi    sp, hi(_fstack-4)
    130         ori     sp, sp, lo(_fstack-4)
     129        mvhi    sp, hi(_Configuration_Interrupt_stack_area_end-4)
     130        ori     sp, sp, lo(_Configuration_Interrupt_stack_area_end-4)
    131131        /* Initialize global pointer */
    132132        mvhi    gp, hi(_edata)

  • bsps/m32c/m32cbsp/start/linkcmds

    r715d616 r511dc4b  
    55_RamSize = DEFINED(_RamSize) ? _RamSize : 0x800000;
    66_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0;
    7 _StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
    8 
    97
    108/* Default linker script, for normal executables */
    … …  
    154152  } > RAM
    155153  PROVIDE (__bsssize = 0);
    156   . = ALIGN(16);
    157 
    158   . += _StackSize;
    159   PROVIDE (__stack = .);
    160154
    161155  .rtemsstack (NOLOAD) : {
    … …  
    167161  PROVIDE (_WorkAreaEnd = .);
    168162  PROVIDE (_WorkAreaSize = _WorkAreaEnd - _WorkAreaBase);
    169 
    170 /*
    171   .stack (0x200000 + 0x800000 - 2) :
    172   {
    173     PROVIDE (__stack = .);
    174     *(.stack)
    175   }
    176 */
    177163
    178164  .vec : {

  • bsps/m32c/m32cbsp/start/start.S

    r715d616 r511dc4b  
    4949.LFB2:
    5050        fset    U       /* User stack */
    51         ldc     #__stack,sp
     51        ldc     #__Configuration_Interrupt_stack_area_end,sp
    5252
    5353#ifdef A16

  • bsps/m68k/gen68340/start/linkcmds

    r715d616 r511dc4b  
    2222RamSize = DEFINED(RamSize) ? RamSize : 4M;
    2323HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
    24 _StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
    2524
    2625/*
    … …  
    187186                . = ALIGN (16);
    188187                PROVIDE (end = .);
    189 
    190                 . += _StackSize;
    191                 . = ALIGN (16);
    192                 _stack_init = .;
    193188                _clear_end = .;
    194189        } >ram

  • bsps/m68k/gen68340/start/start.S

    r715d616 r511dc4b  
    851851        bcs.s   ZEROLOOP                                        | No, skip
    852852
    853         movel   #_stack_init,a7                                 | set master stack pointer
     853        movel   #_Configuration_Interrupt_stack_area_end,a7             | set master stack pointer
    854854        movel   d0,a7@-                                         | command line
    855855        jsr     SYM(boot_card)                                  | Call C main

  • bsps/m68k/gen68360/start/linkcmds

    r715d616 r511dc4b  
    1717RamSize = DEFINED(RamSize) ? RamSize : 64M;
    1818HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
    19 _StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
    2019
    2120/*
    … …  
    151150                . = ALIGN (16);
    152151                PROVIDE (end = .);
    153 
    154                 . += _StackSize;
    155                 . = ALIGN (16);
    156                 _stack_init = .;
    157152                _clear_end = .;
    158153        } >ram

  • bsps/m68k/gen68360/start/linkcmds.bootp

    r715d616 r511dc4b  
    2121RamSize = DEFINED(RamSize) ? RamSize : 64M;
    2222HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
    23 _StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
    2423
    2524/*
    … …  
    153152                . = ALIGN (16);
    154153                PROVIDE (end = .);
    155 
    156                 . += _StackSize;
    157                 . = ALIGN (16);
    158                 _stack_init = .;
    159154                _clear_end = .;
    160155        } >myram

  • bsps/m68k/gen68360/start/linkcmds.prom

    r715d616 r511dc4b  
    2121RamSize = DEFINED(RamSize) ? RamSize : 64M;
    2222HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
    23 _StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
    2423
    2524/*
    … …  
    151150                . = ALIGN (16);
    152151                PROVIDE (end = .);
    153 
    154                 . += _StackSize;
    155                 . = ALIGN (16);
    156                 _stack_init = .;
    157152                _clear_end = .;
    158153        } >ram

  • bsps/m68k/gen68360/start/start.S

    r715d616 r511dc4b  
    391391        bcs.s   ZEROLOOP                | No, skip
    392392
    393         movel   #_stack_init,a7         | set master stack pointer
     393        movel   #_Configuration_Interrupt_stack_area_end,a7 | set master stack pointer
    394394        movel   d0,a7@-                 | command line
    395395        jsr     boot_card               | Call C main

  • bsps/m68k/genmcf548x/start/linkcmds.COBRA5475

    r715d616 r511dc4b  
    6363_BootFlashSize  = DEFINED(_BootFlashSize)  ? _BootFlashSize : (32 * 1024*1024);
    6464
    65 bsp_initstack_size = DEFINED(StackSize)    ? StackSize  : 0x800;  /* 2 kB   */
    66 
    6765_VBR            = DEFINED(_VBR)            ? _VBR       : _SdramBase;
    6866

  • bsps/m68k/genmcf548x/start/linkcmds.m5484FireEngine

    r715d616 r511dc4b  
    6464_CodeFlashSize  = DEFINED(_CodeFlashSize)  ? _CodeFlashSize : (16 * 1024*1024);
    6565
    66 bsp_initstack_size = DEFINED(StackSize)    ? StackSize  : 0x800;  /* 2 kB   */
    67 
    6866_VBR            = DEFINED(_VBR)            ? _VBR       : _SdramBase;
    6967

  • bsps/m68k/genmcf548x/start/linkcmds.m5484FireEngine.flash

    r715d616 r511dc4b  
    6464_CodeFlashSize = DEFINED(_CodeFlashSize)  ? _CodeFlashSize : (16 * 1024 * 1024);
    6565
    66 bsp_initstack_size = DEFINED(StackSize)    ? StackSize  : 0x800;  /* 2 kB   */
    67 
    6866_VBR            = DEFINED(_VBR)            ? _VBR       : _SdramBase;
    6967

  • bsps/m68k/genmcf548x/start/start.S

    r715d616 r511dc4b  
    7676PUBLIC (InterruptVectorTable)
    7777SYM(InterruptVectorTable):
    78 INITSP:         .long   bsp_initstack_end       /* Initial SP             */
     78INITSP:         .long   _Configuration_Interrupt_stack_area_end /* Initial SP             */
    7979INITPC:         .long   start                   /* Initial PC             */
    8080vector002:      .long   asm_default_interrupt   /* Access Error           */
    … …  
    412412    jsr     mcf548x_init                /* Initialize mcf548x peripherals */
    413413
    414     move.l  #bsp_initstack_end,sp       /* relocate sp */
     414    move.l  #_Configuration_Interrupt_stack_area_end,sp /* relocate sp */
    415415
    416416    clrl    d0                          /* clear d0 */

  • bsps/m68k/mcf52235/start/linkcmds

    r715d616 r511dc4b  
    1717RamSize = DEFINED(RamSize) ? RamSize : 32K;
    1818HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
    19 _StackSize = DEFINED(_StackSize) ? _StackSize : 0x400;
    2019_FlashBase = DEFINED(_FlashBase) ? _FlashBase : 0x00000000;
    2120
    … …  
    172171    } >sram
    173172
    174     .stack :
    175     {
    176         /*
    177          * Starting Stack
    178          */
    179         . += _StackSize;
    180         . = ALIGN (16);
    181         PROVIDE(_StackInit = .);
    182     } >sram
    183 
    184173    .rtemsstack (NOLOAD) : {
    185174        *(SORT(.rtemsstack.*))

  • bsps/m68k/mcf52235/start/start.S

    r715d616 r511dc4b  
    1717#include <rtems/asm.h>
    1818
    19 .extern _StackInit
    20 
    2119BEGIN_CODE
    2220
    … …  
    2422SYM(_INTERRUPT_VECTOR):
    2523
    26     .long   _StackInit /* 00 Initial 'SSP' */
     24    .long   _Configuration_Interrupt_stack_area_end /* 00 Initial 'SSP' */
    2725    .long   SYM(start) /* 01 Initial PC */
    2826    .long   SYM(_uhoh) /* 02 Access Error */
    … …  
    358356
    359357    /* Locate Stack Pointer */
    360     move.l  #_StackInit, sp
     358    move.l  #_Configuration_Interrupt_stack_area_end, sp
    361359
    362360    /* Initialize FLASHBAR */
    … …  
    370368
    371369    /* Locate Stack Pointer */
    372     move.l  #_StackInit, sp
     370    move.l  #_Configuration_Interrupt_stack_area_end, sp
    373371
    374372    /* Save off intial D0 and D1 to RAM */

  • bsps/m68k/mcf5225x/start/linkcmds

    r715d616 r511dc4b  
    1717RamSize = DEFINED(RamSize) ? RamSize : 64K;
    1818HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
    19 _StackSize = DEFINED(_StackSize) ? _StackSize : 0x400;
    2019_FlashBase = DEFINED(_FlashBase) ? _FlashBase : 0x00000000;
    2120
    … …  
    172171    } >sram
    173172
    174     .stack :
    175     {
    176         /*
    177          * Starting Stack
    178          */
    179         . += _StackSize;
    180         . = ALIGN (16);
    181         PROVIDE(_StackInit = .);
    182     } >sram
    183 
    184173    .rtemsstack (NOLOAD) : {
    185174        *(SORT(.rtemsstack.*))

  • bsps/m68k/mcf5225x/start/start.S

    r715d616 r511dc4b  
    1717#include <rtems/asm.h>
    1818
    19 .extern _StackInit
    20 
    2119BEGIN_CODE
    2220   
    … …  
    2422SYM(_INTERRUPT_VECTOR):
    2523
    26     .long   _StackInit /* 00 Initial 'SSP' */
     24    .long   _Configuration_Interrupt_stack_area_end /* 00 Initial 'SSP' */
    2725    .long   SYM(start) /* 01 Initial PC */
    2826    .long   SYM(_uhoh) /* 02 Access Error */
    … …  
    362360
    363361    /* Locate Stack Pointer */
    364     move.l  #_StackInit, sp
     362    move.l  #_Configuration_Interrupt_stack_area_end, sp
    365363
    366364    /* Initialize FLASHBAR */
    … …  
    374372
    375373    /* Locate Stack Pointer */
    376 //    move.l  #_StackInit, sp           //is done automatically by the CPU
     374//    move.l  #_Configuration_Interrupt_stack_area_end, sp              //is done automatically by the CPU
    377375
    378376    /*

  • bsps/m68k/mcf5329/start/linkcmds

    r715d616 r511dc4b  
    2424
    2525HeapSize = DEFINED(HeapSize) ? HeapSize : 0;
    26 _StackSize = DEFINED(_StackSize) ? _StackSize : 0x400;
    2726
    2827_VBR = 0x40000000;
    … …  
    179178        . = ALIGN (16);
    180179        PROVIDE (_end = .);
    181 
    182180        _clear_end = .;
     181        WorkAreaBase = .;
    183182    } > dram
    184183
    185184    .rtemsstack (NOLOAD) : {
    186185        *(SORT(.rtemsstack.*))
    187         WorkAreaBase = .;
    188     } > dram
    189 
    190     .start_stack :
    191     {
    192         /*
    193          * Starting Stack
    194          */
    195         . += _StackSize;
    196         . = ALIGN (16);
    197         PROVIDE(_StackInit = .);
    198186    } > core_sram
    199187

  • bsps/m68k/mcf5329/start/linkcmdsflash

    r715d616 r511dc4b  
    2424
    2525HeapSize = DEFINED(HeapSize) ? HeapSize : 0;
    26 _StackSize = DEFINED(_StackSize) ? _StackSize : 0x400;
    2726
    2827_VBR = 0x40000000;
    … …  
    175174        . = ALIGN (16);
    176175        PROVIDE (_end = .);
    177 
    178176        _clear_end = .;
     177        WorkAreaBase = .;
    179178    } > dram
    180179
    181180    .rtemsstack (NOLOAD) : {
    182181        *(SORT(.rtemsstack.*))
    183         WorkAreaBase = .;
    184     } > dram
    185 
    186     .start_stack :
    187     {
    188         /*
    189          * Starting Stack
    190          */
    191         . += _StackSize;
    192         . = ALIGN (16);
    193         PROVIDE(_StackInit = .);
    194182    } > core_sram
    195183

  • bsps/m68k/mcf5329/start/start.S

    r715d616 r511dc4b  
    1717#include <rtems/asm.h>
    1818
    19 .extern _StackInit
    20 
    2119BEGIN_CODE
    2220
    … …  
    2422SYM(_INTERRUPT_VECTOR):
    2523
    26     .long   _StackInit /* 00 Initial 'SSP' */
     24    .long   _Configuration_Interrupt_stack_area_end /* 00 Initial 'SSP' */
    2725    .long   SYM(start) /* 01 Initial PC */
    2826    .long   SYM(_uhoh) /* 02 Access Error */
    … …  
    347345
    348346    /* Locate Stack Pointer */
    349     move.l  #_StackInit,sp
     347    move.l  #_Configuration_Interrupt_stack_area_end,sp
    350348
    351349    /*

  • bsps/m68k/mrm332/start/linkcmds

    r715d616 r511dc4b  
    3333 * |        _ENDHEAP    |
    3434 * |    stack space     |
    35  * |        __stack     | top of stack
    3635 * +--------------------+ <- high memory
    3736 */
    … …  
    5352_copy_data_from_rom = 1;
    5453HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
    55 _StackSize = DEFINED(_StackSize) ? _StackSize : 0x2000;
    5654
    5755
    … …  
    195193    . = ALIGN (16);
    196194    PROVIDE (end = .);
    197     . += _StackSize;
    198     . = ALIGN (16);
    199     _stack_init = .;
    200195    _clear_end = .;
    201196  } > ram

  • bsps/m68k/mrm332/start/start.S

    r715d616 r511dc4b  
    3838        movecl  d0,vbr
    3939
    40         movel  #end, d0                         /* Next 3 instructions set stack pointer    */
    41         addl   #_StackSize,d0       /* sp = end + _StackSize from linker script */
    42         movel  d0,sp
    43         movel  d0,a6                   
     40        /* Set stack pointer */
     41        movel   #_Configuration_Interrupt_stack_area_end,d0
     42        movel   d0,sp
     43        movel   d0,a6
    4444
    4545  /* include in ram_init.S */

  • bsps/m68k/shared/start/linkcmds.base

    r715d616 r511dc4b  
    11/*
    2  * Copyright (c) 2008-2013 embedded brains GmbH.  All rights reserved.
     2 * Copyright (c) 2008, 2018 embedded brains GmbH.  All rights reserved.
    33 *
    44 *  embedded brains GmbH
    … …  
    1919ENTRY(start)
    2020STARTUP(start.o)
    21 
    22 bsp_initstack_size = DEFINED (bsp_initstack_size) ? bsp_initstack_size : 2048;
    2321
    2422MEMORY {
    … …  
    226224        } > REGION_DATA AT > REGION_DATA
    227225        bsp_vector1_size = bsp_vector1_end - bsp_vector1_begin;
    228 
    229         .initstack : ALIGN_WITH_INPUT {
    230                 bsp_initstack_begin = .;
    231                 . = . + bsp_initstack_size;
    232                 bsp_initstack_end = .;
    233         } > REGION_DATA AT > REGION_DATA
    234226
    235227        .data : ALIGN_WITH_INPUT {

  • bsps/m68k/shared/start/start.S

    r715d616 r511dc4b  
    7575        jlt     loop                    | loop until _end reached
    7676
    77         movel   # SYM (_stack_init),d0 | d0 = stop of stack
     77        movel   # SYM (_Configuration_Interrupt_stack_area_end),d0 | d0 = stop of stack
    7878        movw    #0x3700,sr              | SUPV MODE,INTERRUPTS OFF!!!
    7979        movel   d0,a7                   | set master stack pointer
    … …  
    136136        .space  2
    137137
    138         .align 16
    139          PUBLIC (starting_stack)
    140 SYM (starting_stack):
    141         .space  0x1000
    142          PUBLIC (_stack_init)
    143 SYM (_stack_init):
    144 
    145138END_DATA
    146139#endif

  • bsps/mips/csb350/start/linkcmds

    r715d616 r511dc4b  
    1616RamSize = _sdram_size;
    1717HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
    18 _StackSize = DEFINED(_StackSize) ? _StackSize : 0x4000;
    1918
    2019ENTRY(_start)
    … …  
    188187    *(COMMON)
    189188    . = ALIGN (64);
    190     _stack_limit = .;
    191     . += _StackSize;
    192     __stack = .;
    193     _stack_init = .;
    194189    _clear_end = .;
    195190    end = .;

  • bsps/mips/csb350/start/start.S

    r715d616 r511dc4b  
    6868        addiu   v0,v0,4                 /* executed in delay slot */
    6969
    70         la      t0, _stack_init         /* initialize stack so we */
     70        la      t0, _Configuration_Interrupt_stack_area_end /* initialize stack so we */
    7171        /* We must subtract 24 bytes for the 3 8 byte arguments to main, in
    7272           case main wants to write them back to the stack.  The caller is

  • bsps/mips/hurricane/start/linkcmds

    r715d616 r511dc4b  
    99RamSize = DEFINED(RamSize) ? RamSize : 4M;
    1010HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
    11 _StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
    1211
    1312ENTRY(start)
    … …  
    167166    *(COMMON)
    168167    . = ALIGN (64);
    169     _stack_limit = .;
    170     . += _StackSize;
    171     __stack = .;
    172     _stack_init = .;
    173168     end = .;
    174169    _end = .;

  • bsps/mips/jmr3904/start/linkcmds

    r715d616 r511dc4b  
    99RamSize = DEFINED(RamSize) ? RamSize : 4M;
    1010HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
    11 _StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
    1211
    1312ENTRY(_start)
    … …  
    165164    *(COMMON)
    166165    . = ALIGN (64);
    167     _stack_limit = .;
    168     . += _StackSize;
    169     __stack = .;
    170     _stack_init = .;
    171166    _clear_end = .;
    172167  }
    … …  
    182177
    183178
    184 /* Put starting stack in SRAM (8 Kb); this size is the same as the stack from
    185       the original script (when everything was in SRAM). */
    186    /* __stack = 0x8000A000; */
    187179  /* DWARF debug sections.
    188180     Symbols in the DWARF debugging sections are relative to

  • bsps/mips/jmr3904/start/start.S

    r715d616 r511dc4b  
    140140        addiu   v0,v0,4                         # executed in delay slot
    141141
    142         la      t0, _stack_init                 # initialize stack so we
     142        la      t0, _Configuration_Interrupt_stack_area_end # initialize stack so we
    143143        /* We must subtract 24 bytes for the 3 8 byte arguments to main, in
    144144           case main wants to write them back to the stack.  The caller is

  • bsps/mips/malta/start/linkcmds

    r715d616 r511dc4b  
    99RamSize = DEFINED(RamSize) ? RamSize : 128M;
    1010HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
    11 _StackSize = DEFINED(_StackSize) ? _StackSize : 0x2000;
    1211
    1312ENTRY(_start)
    … …  
    166165    *(COMMON)
    167166    . = ALIGN (64);
    168     _stack_limit = .;
    169     . += _StackSize;
    170     __stack = .;
    171     _stack_init = .;
    172167    _clear_end = .;
    173168  }
    … …  
    183178
    184179
    185 /* Put starting stack in SRAM (8 Kb); this size is the same as the stack from
    186       the original script (when everything was in SRAM). */
    187    /* __stack = 0x8000A000; */
    188180  /* DWARF debug sections.
    189181     Symbols in the DWARF debugging sections are relative to

  • bsps/mips/malta/start/start.S

    r715d616 r511dc4b  
    167167        addiu   v0,v0,4                         # executed in delay slot
    168168
    169         la      t0, _stack_init                 # initialize stack so we
     169        la      t0, _Configuration_Interrupt_stack_area_end # initialize stack so we
    170170        /* We must subtract 24 bytes for the 3 8 byte arguments to main, in
    171171           case main wants to write them back to the stack.  The caller is

  • bsps/mips/rbtx4925/start/linkcmds

    r715d616 r511dc4b  
    99RamSize = DEFINED(RamSize) ? RamSize : 4M;
    1010HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
    11 _StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
    1211
    1312ENTRY(start)
    … …  
    167166    *(COMMON)
    168167    . = ALIGN (64);
    169     _stack_limit = .;
    170     . += _StackSize;
    171     __stack = .;
    172     _stack_init = .;
    173168     end = .;
    174169    _end = .;

  • bsps/mips/rbtx4938/start/linkcmds

    r715d616 r511dc4b  
    99RamSize = DEFINED(RamSize) ? RamSize : 4M;
    1010HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
    11 _StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
    1211
    1312ENTRY(start)
    … …  
    167166    *(COMMON)
    168167    . = ALIGN (64);
    169     _stack_limit = .;
    170     . += _StackSize;
    171     __stack = .;
    172     _stack_init = .;
    173168     end = .;
    174169    _end = .;

  • bsps/mips/shared/irq/exception.S

    r715d616 r511dc4b  
    215215  /*
    216216   *
    217    *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
    218    *    if ( _ISR_Nest_level == 0 )
    219    *      switch to software interrupt stack
    220    *  #endif
     217   *  if ( _ISR_Nest_level == 0 )
     218   *    switch to software interrupt stack
    221219   */
    222220
    … …  
    308306
    309307  /*
    310    *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
    311    *    restore stack
    312    *  #endif
     308   *  restore stack
    313309   *
    314310   *  if ( !_Thread_Dispatch_necessary )

  • bsps/nios2/nios2_iss/start/linkcmds

    r715d616 r511dc4b  
    2525RamSize = DEFINED(RamSize) ? RamSize : 0x00800000;
    2626HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
    27 StackSize = DEFINED(StackSize) ? HeapSize : 1024;
    2827
    2928MEMORY
    … …  
    266265        . = ALIGN(32 / 8);
    267266        __bss_end = ABSOLUTE(.);
     267    } > onchip_memory_0
     268
     269    .rtemsstack (NOLOAD) : {
    268270        _stack_low = ABSOLUTE(.);
    269         . += StackSize;
     271        *(SORT(.rtemsstack.*))
    270272        _stack_high = ABSOLUTE(.);
    271     } > onchip_memory_0
    272 
    273     .rtemsstack (NOLOAD) : {
    274         *(SORT(.rtemsstack.*))
    275273        WorkAreaBase = .;
    276274    } > onchip_memory_0

  • bsps/powerpc/beatnik/start/bspstart.c

    r715d616 r511dc4b  
    178178  unsigned char  *stack;
    179179  char           *chpt;
    180   uint32_t       intrStackStart;
    181   uint32_t       intrStackSize;
     180  uintptr_t       intrStackStart;
     181  uintptr_t       intrStackSize;
    182182
    183183  Triv121PgTbl  pt=0;
    … …  
    240240   * some settings below...
    241241   */
    242   intrStackStart = (uint32_t)__rtems_end;
     242  intrStackStart = (uintptr_t)_Configuration_Interrupt_stack_area_begin;
    243243  intrStackSize  = rtems_configuration_get_interrupt_stack_size();
    244244

  • bsps/powerpc/gen5200/include/bsp.h

    r715d616 r511dc4b  
    5656LINKER_SYMBOL(bsp_section_bss_size);
    5757
    58 LINKER_SYMBOL(bsp_interrupt_stack_start);
    59 LINKER_SYMBOL(bsp_interrupt_stack_end);
    60 LINKER_SYMBOL(bsp_interrupt_stack_size);
    61 
    6258LINKER_SYMBOL(bsp_work_area_start);
    6359

  • bsps/powerpc/gen5200/start/bspstart.c

    r715d616 r511dc4b  
    155155  ppc_exc_cache_wb_check = 0;
    156156  ppc_exc_initialize(
    157     (uintptr_t) bsp_interrupt_stack_start,
    158     (uintptr_t) bsp_interrupt_stack_size
     157    (uintptr_t) _Configuration_Interrupt_stack_area_begin,
     158    rtems_configuration_get_interrupt_stack_size()
    159159  );
    160160  ppc_exc_set_handler(ASM_ALIGN_VECTOR, ppc_exc_alignment_handler);

  • bsps/powerpc/gen5200/start/linkcmds.gen5200_base

    r715d616 r511dc4b  
    288288        bsp_section_data_size = bsp_section_data_end - bsp_section_data_start;
    289289        bsp_section_bss_size = bsp_section_bss_end - bsp_section_bss_start;
    290 
    291         /*
    292          * BSP: Interrupt stack
    293          */
    294         bsp_interrupt_stack_start = bsp_section_bss_end;
    295         bsp_interrupt_stack_end = bsp_interrupt_stack_start + 32k;
    296         bsp_interrupt_stack_size = bsp_interrupt_stack_end - bsp_interrupt_stack_start;
    297290
    298291        .rtemsstack (NOLOAD) : {

  • bsps/powerpc/gen83xx/include/bsp.h

    r715d616 r511dc4b  
    5353LINKER_SYMBOL(bsp_section_bss_end);
    5454LINKER_SYMBOL(bsp_section_bss_size);
    55 
    56 LINKER_SYMBOL(bsp_interrupt_stack_start);
    57 LINKER_SYMBOL(bsp_interrupt_stack_end);
    58 LINKER_SYMBOL(bsp_interrupt_stack_size);
    5955
    6056LINKER_SYMBOL(bsp_work_area_start);

  • bsps/powerpc/gen83xx/start/start.S

    r715d616 r511dc4b  
    418418
    419419        /* Set start stack pointer */
    420         LA      r1, start_stack_end
     420        LA      r1, _Configuration_Interrupt_stack_area_end
    421421        stwu    r3, -4(r1)
    422422        stwu    r3, -4(r1)
    … …  
    521521        /* Return */
    522522        blr
    523 
    524 .section ".bsp_rwextra", "aw", @nobits
    525 
    526         /* Start stack area */
    527 .align 4
    528 .space 4096
    529 start_stack_end:

  • bsps/powerpc/haleakala/start/bspstart.c

    r715d616 r511dc4b  
    6767
    6868#include <stdio.h>
    69 
    70 LINKER_SYMBOL(intrStack_start);
    71 LINKER_SYMBOL(intrStack_size);
    7269/*
    7370 *  Driver configuration parameters
    … …  
    189186   */
    190187  ppc_exc_initialize(
    191     (uintptr_t) intrStack_start,
    192     (uintptr_t) intrStack_size
     188    (uintptr_t) _Configuration_Interrupt_stack_area_begin,
     189    rtems_configuration_get_interrupt_stack_size()
    193190  );
    194191

  • bsps/powerpc/haleakala/start/dlentry.S

    r715d616 r511dc4b  
    5555 * see linker command file for section placement
    5656 *
    57  *  The initial stack is set to stack.end
     57 *  The initial stack is set to _Configuration_Interrupt_stack_area_end.
    5858 *
    5959 *  All the entry veneer has to do is to clear the BSS.
    … …  
    9999                .long   sbss.start
    100100stack_top:
    101                 .long   stack.end
     101                .long   _Configuration_Interrupt_stack_area_end
    102102PUBLIC_VAR (text_addr)
    103103text_addr:

  • bsps/powerpc/haleakala/start/linkcmds

    r715d616 r511dc4b  
    1414ENTRY(download_entry)
    1515EXTERN(__vectors)
    16 
    17 kIntrStackSize = 16K;
    18 kMainStackSize = 64K;
    1916
    2017RamBase = DEFINED(RamBase) ? RamBase : 0;
    … …  
    247244    bss.size = bss.end - bss.start;
    248245    sbss.size = sbss.end - sbss.start;
    249                        
    250     /* Interrupt stack: align to a cache-line boundary */
    251     IntrStack_start = ALIGN(0x20);
    252     . += kIntrStackSize;
    253     intrStack = .;
    254     PROVIDE(intrStackPtr = intrStack);
    255     PROVIDE(intrStack_start = IntrStack_start);
    256     PROVIDE(intrStack_size = kIntrStackSize);
    257 
    258         /* Main stack: align to a cache-line boundary */
    259         stack.start = ALIGN(0x20);
    260         . += kMainStackSize;
    261         stack.end   = .;
    262246
    263247    .rtemsstack (NOLOAD) : {

  • bsps/powerpc/motorola_powerpc/start/bspstart.c

    r715d616 r511dc4b  
    221221   * Initialize the interrupt related settings.
    222222   */
    223   intrStackStart = (uintptr_t) __rtems_end;
     223  intrStackStart = (uintptr_t)_Configuration_Interrupt_stack_area_begin;
    224224  intrStackSize = rtems_configuration_get_interrupt_stack_size();
    225225

  • bsps/powerpc/mpc55xxevb/start/start.S

    r715d616 r511dc4b  
    229229
    230230        /* Initialize start stack */
    231         LA      r1, start_stack_end
     231        LA      r1, _Configuration_Interrupt_stack_area_end
    232232        subi    r1, r1, 16
    233233        li      r0, 0
    … …  
    290290        beqlr   cr7
    291291        b       memcpy
    292 
    293         /* Start stack area */
    294 
    295         .section        ".bsp_rwextra", "aw", @nobits
    296         .align  4
    297         .space  4096
    298 
    299 start_stack_end:

  • bsps/powerpc/mpc8260ads/start/bspstart.c

    r715d616 r511dc4b  
    7070uint32_t   bsp_serial_rate;
    7171
    72 extern char IntrStack_start [];
    73 extern char intrStack [];
    74 
    7572static void _BSP_GPLED0_on(void)
    7673{
    … …  
    143140
    144141  /* Initialize exception handler */
    145   /* FIXME: Interrupt stack begin and size */
    146142  ppc_exc_initialize(
    147     (uintptr_t) IntrStack_start,
    148     (uintptr_t) intrStack - (uintptr_t) IntrStack_start
     143    (uintptr_t) _Configuration_Interrupt_stack_area_begin,
     144    rtems_configuration_get_interrupt_stack_size()
    149145  );
    150146

  • bsps/powerpc/mpc8260ads/start/linkcmds

    r715d616 r511dc4b  
    1818 *      the lines marked XXX below to use a constant value.
    1919 */
    20 StackSize   = DEFINED(StackSize) ? StackSize : 0x8000;
    2120RamBase     = DEFINED(RamBase) ? RamBase : 0x0;
    2221RamSize     = DEFINED(RamSize) ? RamDiskSize : 0x0800000; /* 8M program ram */
    … …  
    290289     } >ram
    291290
    292 
    293     /*
    294      * Interrupt stack setup
    295      */
    296     IntrStack_start = ALIGN(0x10);
    297     . += 0x4000;
    298     intrStack = .;
    299     PROVIDE(intrStackPtr = intrStack);
    300 
    301 
    302291    clear_end = .;
    303292

  • bsps/powerpc/mvme3100/start/bspstart.c

    r715d616 r511dc4b  
    256256   * Initialize the interrupt related settings.
    257257   */
    258   intrStackStart = (uintptr_t) __rtems_end;
     258  intrStackStart = (uintptr_t) _Configuration_Interrupt_stack_area_begin;
    259259  intrStackSize = rtems_configuration_get_interrupt_stack_size();
    260260

  • bsps/powerpc/mvme5500/start/bspstart.c

    r715d616 r511dc4b  
    226226   * Initialize the interrupt related settings.
    227227   */
    228   intrStackStart = (uintptr_t) __rtems_end;
     228  intrStackStart = (uintptr_t) _Configuration_Interrupt_stack_area_begin;
    229229  intrStackSize = rtems_configuration_get_interrupt_stack_size();
    230230

  • bsps/powerpc/psim/start/start.S

    r715d616 r511dc4b  
    4848
    4949.Lstack = .-.LCTOC1                     /* stack address if set by user */
    50         .long   __stack
     50        .long   _Configuration_Interrupt_stack_area_end
    5151
    5252        .text
    … …  
    9090.Ldone:
    9191
    92         lwz     r0,.Lstack(r5)          /* stack address or 0 */
     92        lwz     r0,.Lstack(r5)  /* stack area or 0 */
    9393        cmplwi  1,r0,0                  /* equal to 0? */
    9494        bc      12,6,.Lnostack          /* use default stack if == 0 */
    … …  
    134134.Lstart:
    135135        .size   _start,.Lstart-_start
    136 
    137         /* Start stack area */
    138 .section ".bsp_rwextra", "aw", @nobits
    139 .align 4
    140 .space 4096
    141 __stack:

  • bsps/powerpc/qemuppc/start/bspstart.c

    r715d616 r511dc4b  
    4343 */
    4444extern char RamSize[];
    45 extern char bsp_interrupt_stack_start[];
    46 extern char bsp_interrupt_stack_end[];
    4745uint32_t BSP_mem_size = (uint32_t)RamSize;
    4846
    … …  
    9088   * Initialize the interrupt related settings.
    9189   */
    92   intrStackStart = (uintptr_t) bsp_interrupt_stack_start;
    93   intrStackSize =  (uintptr_t) bsp_interrupt_stack_end - intrStackStart;
     90  intrStackStart = (uintptr_t) _Configuration_Interrupt_stack_area_begin;
     91  intrStackSize = rtems_configuration_get_interrupt_stack_size();
    9492
    9593  BSP_mem_size = (uint32_t )RamSize;

  • bsps/powerpc/qemuppc/start/start.S

    r715d616 r511dc4b  
    22#include <rtems/powerpc/powerpc.h>
    33
    4 #include <bspopts.h>
    5 
    6         .global bsp_interrupt_stack_start
    7         .global bsp_interrupt_stack_end
    84        .global _start
    95
    … …  
    117
    128_start:
    13         lis   %r1,bsp_interrupt_stack_start@h
    14         ori   %r1,%r1,bsp_interrupt_stack_start@l
     9        lis   %r1,_Configuration_Interrupt_stack_area_end@h
     10        ori   %r1,%r1,_Configuration_Interrupt_stack_area_end@l
    1511        /* Make sure stack is properly aligned */
    1612        li    %r3, CPU_STACK_ALIGNMENT - 1
    … …  
    4339        b _start
    4440        .size _reset, . - _reset
    45 
    46         /* Start stack area */
    47         .section ".bsp_rwextra", "aw", @nobits
    48         .align 4
    49         .space 4096
    50 bsp_interrupt_stack_start:
    51         .space 32768
    52 bsp_interrupt_stack_end:

  • bsps/powerpc/qoriq/start/start.S

    r715d616 r511dc4b  
    5656
    5757        /* Get start stack */
    58         LA      START_STACK, start_stack_end
     58        LA      START_STACK, _Configuration_Interrupt_stack_area_begin
     59        LA      r3, _Configuration_Interrupt_stack_size
     60        add     START_STACK, START_STACK, r3
    5961
    6062        bl      .Linitmore
    … …  
    227229
    228230        /*
    229          * Initialize start stack.  Make sure that we do not share a cache line
    230          * with the heap block management, since initial stacks for the
    231          * secondary processors are allocated from the workspace.
     231         * Initialize start stack.  The stacks are statically allocated and
     232         * properly aligned.
    232233         */
    233         subi    r1, START_STACK, 2 * PPC_DEFAULT_CACHE_LINE_SIZE
    234         clrrwi  r1, r1, PPC_DEFAULT_CACHE_LINE_POWER
     234        subi    r1, START_STACK, PPC_DEFAULT_CACHE_LINE_SIZE
    235235        li      r0, 0
    236236        PPC_REG_STORE   r0, 0(r1)
    … …  
    541541/* Symbol provided for debugging and tracing */
    542542bsp_exc_vector_end:
    543 
    544         /* Start stack area */
    545         .section ".bsp_rwextra", "aw", @nobits
    546         .align 4
    547         .space 4096
    548 start_stack_end:

  • bsps/powerpc/shared/start/linkcmds.base

    r715d616 r511dc4b  
    322322        .rtemsstack (NOLOAD) : ALIGN_WITH_INPUT {
    323323                bsp_section_rtemsstack_begin = .;
    324                 *(.bsp_rwextra)
    325324                *(SORT(.rtemsstack.*))
    326325                bsp_section_rtemsstack_end = .;

  • bsps/powerpc/ss555/start/bspstart.c

    r715d616 r511dc4b  
    3333SPR_RW(SPRG1)
    3434
    35 extern unsigned long intrStackPtr;
    36 
    3735/*
    3836 *  Driver configuration parameters
    … …  
    6866void bsp_start(void)
    6967{
    70   register unsigned char* intrStack;
     68  char* intrStack;
    7169
    7270  /*
    … …  
    8179   * Initialize some SPRG registers related to irq handling
    8280   */
    83   intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE);
     81  intrStack = (char *)_Configuration_Interrupt_stack_area_end -
     82     PPC_MINIMUM_STACK_FRAME_SIZE;
    8483  _write_SPRG1((unsigned int)intrStack);
    8584

  • bsps/powerpc/ss555/start/linkcmds

    r715d616 r511dc4b  
    233233  PROVIDE(_end = bss.end);
    234234
    235   /*
    236    * Initialization stack
    237    */
    238   InitStack_start = ALIGN(0x10);
    239   . += 0x1000;
    240   initStack = .;
    241   PROVIDE(initStackPtr = initStack);
    242 
    243   /*
    244    * Interrupt stack
    245    */
    246   IntrStack_start = ALIGN(0x10);
    247   . += 0x4000;
    248   intrStack = .;
    249   PROVIDE(intrStackPtr = intrStack);
    250 
    251235  .rtemsstack (NOLOAD) : {
    252236    *(SORT(.rtemsstack.*))

  • bsps/powerpc/ss555/start/start.S

    r715d616 r511dc4b  
    221221 */
    222222stack_top:
    223         .long   initStackPtr
     223        .long   _Configuration_Interrupt_stack_area_end
    224224
    225225toc_pointer:

  • bsps/powerpc/t32mppc/start/start.S

    r715d616 r511dc4b  
    3535
    3636        /* Initialize start stack */
    37         LWI     r1, start_stack_end
     37        LA      r1, _Configuration_Interrupt_stack_area_end
    3838        subi    r1, r1, 16
    3939        li      r0, 0
    … …  
    196196        li      r3, 35
    197197        b       ppc_exc_fatal_normal
    198 
    199         /* Start stack area */
    200         .section ".bsp_rwextra", "aw", @nobits
    201         .align 4
    202         .space 4096
    203 start_stack_end:

  • bsps/powerpc/tqm8xx/include/bsp.h

    r715d616 r511dc4b  
    5353LINKER_SYMBOL( bsp_section_bss_end);
    5454LINKER_SYMBOL( bsp_section_bss_size);
    55 
    56 LINKER_SYMBOL( bsp_interrupt_stack_start);
    57 LINKER_SYMBOL( bsp_interrupt_stack_end);
    58 LINKER_SYMBOL( bsp_interrupt_stack_size);
    5955
    6056LINKER_SYMBOL( bsp_work_area_start);

  • bsps/powerpc/tqm8xx/start/bspstart.c

    r715d616 r511dc4b  
    100100void bsp_start( void)
    101101{
    102 
    103   uintptr_t interrupt_stack_start = (uintptr_t) bsp_interrupt_stack_start;
    104   uintptr_t interrupt_stack_size = (uintptr_t) bsp_interrupt_stack_end
    105     - interrupt_stack_start;
    106 
    107102  /*
    108103   * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
    … …  
    150145
    151146  /* Initialize exception handler */
    152   ppc_exc_initialize(interrupt_stack_start, interrupt_stack_size);
     147  ppc_exc_initialize(
     148    (uintptr_t) _Configuration_Interrupt_stack_area_begin,
     149    rtems_configuration_get_interrupt_stack_size()
     150  );
    153151
    154152  /* Initalize interrupt support */

  • bsps/powerpc/tqm8xx/start/start.S

    r715d616 r511dc4b  
    2727
    2828PUBLIC_VAR (_start)
    29 PUBLIC_VAR (bsp_interrupt_stack_start)
    30 PUBLIC_VAR (bsp_interrupt_stack_end)
    3129
    3230.section ".bsp_start_text", "ax"
    … …  
    120118
    121119        /* Set stack pointer (common for RAM/ROM startup) */
    122         LA      r1, bsp_section_text_begin
    123         addi    r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */
     120        LA      r1, _Configuration_Interrupt_stack_area_end
     121        addi    r1, r1, -0x10
    124122
    125123        /* Create NULL */
    … …  
    286284
    287285end_reloc_startup:
    288 
    289         /* Interrupt stack */
    290         .section ".bsp_rwextra", "aw", @nobits
    291         .align 4
    292 bsp_interrupt_stack_start:
    293         .space 32768
    294 bsp_interrupt_stack_end:

  • bsps/powerpc/virtex4/start/bspstart.c

    r715d616 r511dc4b  
    8686LINKER_SYMBOL(__bsp_ram_end);
    8787LINKER_SYMBOL(__rtems_end);
    88 LINKER_SYMBOL(_stack);
    89 LINKER_SYMBOL(StackSize);
    90 LINKER_SYMBOL(__stack_base);
    9188LINKER_SYMBOL(WorkAreaBase);
    9289LINKER_SYMBOL(MsgAreaBase);
    … …  
    175172   * Initialize the interrupt related settings.
    176173   */
    177   intrStackStart = CPU_UP_ALIGN((uint32_t)__bsp_ram_start);
     174  intrStackStart = (uintptr_t) _Configuration_Interrupt_stack_area_begin;
    178175  intrStackSize  = rtems_configuration_get_interrupt_stack_size();
    179176
    … …  
    185182         "RTEMS:                           %p\n"
    186183         "Interrupt Stack:  0x%08x              0x%x\n"
    187          "Stack:            %p             %p          %p\n"
    188184         "Workspace:        %p             %p\n"
    189185         "MsgArea:          %p             %p\n"
    … …  
    192188         __rtems_end,
    193189         intrStackStart,                intrStackSize,
    194          __stack_base,   _stack,        StackSize,
    195190         WorkAreaBase,   __bsp_ram_end,
    196191         MsgAreaBase,    MsgAreaSize,

  • bsps/powerpc/virtex4/start/linkcmds

    r715d616 r511dc4b  
    1616RamBase           = DEFINED(RamBase)       ? RamBase       : 0x0;
    1717RamSize           = DEFINED(RamSize)       ? RamSize       : 128M - MsgAreaSize;
    18 IntrStackSize     = DEFINED(IntrStackSize) ? IntrStackSize : 16K;
    19 StackSize         = DEFINED(StackSize)     ? StackSize     : 64K;
    2018HeapSize          = DEFINED(HeapSize)      ? HeapSize      : 0; /* 0=Use def */
    2119
    … …  
    252250  PROVIDE(__bsp_ram_start = .);
    253251
    254   /* Interrupt stack: aligned on a cache-line boundary */
    255   .              += IntrStackSize;
    256   __intrStack     = .;
    257 
    258   /* Main stack lives here */
    259   _stack          = ALIGN(0x10);        /* Align to a cache-line boundary */
    260   .              += StackSize;
    261   __stack_base    = .;                  /* Initial stack builds downwards */
    262 
    263252  .rtemsstack (NOLOAD) : {
    264253    *(SORT(.rtemsstack.*))

  • bsps/powerpc/virtex4/start/start.S

    r715d616 r511dc4b  
    8383 *  see linker command file for section placement
    8484 *
    85  *  The initial stack is set to __stack_base.
     85 *  The initial stack is set to _Configuration_Interrupt_stack_area_end.
    8686 *
    8787 */
    … …  
    110110        .long   __bss_start
    111111stack_top:
    112         .long   __stack_base
     112        .long   _Configuration_Interrupt_stack_area_end
    113113dccr_contents:
    114114        .long   __dccr

  • bsps/powerpc/virtex5/start/bspstart.c

    r715d616 r511dc4b  
    8787LINKER_SYMBOL(__bsp_ram_end);
    8888LINKER_SYMBOL(__rtems_end);
    89 LINKER_SYMBOL(_stack);
    90 LINKER_SYMBOL(StackSize);
    91 LINKER_SYMBOL(__stack_base);
    9289LINKER_SYMBOL(WorkAreaBase);
    9390LINKER_SYMBOL(MsgAreaBase);
    … …  
    194191   * Initialize the interrupt related settings.
    195192   */
    196   intrStackStart = CPU_UP_ALIGN((uint32_t)__bsp_ram_start);
     193  intrStackStart = (uintptr_t)_Configuration_Interrupt_stack_area_begin;
    197194  intrStackSize  = rtems_configuration_get_interrupt_stack_size();
    198195
    … …  
    204201         "RTEMS:                           %p\n"
    205202         "Interrupt Stack:  0x%08x              0x%x\n"
    206          "Stack:            %p             %p          %p\n"
    207203         "Workspace:        %p             %p\n"
    208204         "MsgArea:          %p             %p\n"
    … …  
    211207         __rtems_end,
    212208         intrStackStart,                intrStackSize,
    213          __stack_base,   _stack,        StackSize,
    214209         WorkAreaBase,   __bsp_ram_end,
    215210         MsgAreaBase,    MsgAreaSize,

  • bsps/powerpc/virtex5/start/linkcmds

    r715d616 r511dc4b  
    1616RamBase           = DEFINED(RamBase)       ? RamBase       : 0x0;
    1717RamSize           = DEFINED(RamSize)       ? RamSize       : 2048M - MsgAreaSize;
    18 IntrStackSize     = DEFINED(IntrStackSize) ? IntrStackSize : 16K;
    19 StackSize         = DEFINED(StackSize)     ? StackSize     : 64K;
    2018HeapSize          = DEFINED(HeapSize)      ? HeapSize      : 0; /* 0=Use def */
    2119
    … …  
    252250  PROVIDE(__bsp_ram_start = .);
    253251
    254   /* Interrupt stack: aligned on a cache-line boundary */
    255   .              += IntrStackSize;
    256   __intrStack     = .;
    257 
    258   /* Main stack lives here */
    259   _stack          = ALIGN(0x20);        /* Align to a cache-line boundary */
    260   .              += StackSize;
    261   __stack_base    = .;                  /* Initial stack builds downwards */
    262 
    263252  .rtemsstack (NOLOAD) : {
    264253    *(SORT(.rtemsstack.*))

  • bsps/powerpc/virtex5/start/start.S

    r715d616 r511dc4b  
    8787 *  see linker command file for section placement
    8888 *
    89  *  The initial stack is set to __stack_base
     89 *  The initial stack is set to _Configuration_Interrupt_stack_area_end.
    9090 *
    9191 *  All the entry veneer has to do is to clear the BSS.
    … …  
    115115        .long   __bss_start
    116116stack_top:
    117         .long   __stack_base
     117        .long   _Configuration_Interrupt_stack_area_end
    118118
    119119

  • bsps/riscv/riscv_generic/start/start.S

    r715d616 r511dc4b  
    8181
    8282  /* load stack and frame pointers */
    83   la sp, bsp_section_stack_begin
     83  la sp, _Configuration_Interrupt_stack_area_end
    8484
    8585  /* Clearing .bss */

  • bsps/sh/gensh1/include/bsp.h

    r715d616 r511dc4b  
    5050
    5151/*
    52  * Defined in the linker script 'linkcmds'
    53  */
    54 
    55 extern void *CPU_Interrupt_stack_low;
    56 extern void *CPU_Interrupt_stack_high;
    57 
    58 /*
    5952 * BSP methods that cross file boundaries.
    6053 */

  • bsps/sh/gensh1/start/cpu_asm.c

    r715d616 r511dc4b  
    4545extern proc_ptr         _Hardware_isr_Table[];
    4646
    47 #if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
    48   unsigned long    *_old_stack_ptr;
    49 #endif
     47unsigned long *_old_stack_ptr;
    5048
    5149register unsigned long  *stack_ptr __asm__ ("r15");
    … …  
    136134  _Thread_Dispatch_disable();
    137135
    138 #if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
    139136  if ( _ISR_Nest_level == 0 )
    140137    {
    … …  
    143140      stack_ptr = _CPU_Interrupt_stack_high;
    144141    }
    145 
    146 #endif
    147142
    148143  _ISR_Nest_level++;
    … …  
    160155  _ISR_Nest_level--;
    161156
    162 #if(CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
    163 
    164157  if ( _ISR_Nest_level == 0 )
    165158    /* restore old stack pointer */
    166159    stack_ptr = _old_stack_ptr;
    167 #endif
    168160
    169161  _ISR_Local_enable( level );

  • bsps/sh/gensh1/start/linkcmds

    r715d616 r511dc4b  
    193193  } > onchip_ram
    194194
    195   _CPU_Interrupt_stack_low  = 0x0f000000 ;
    196   _CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ;
    197 
    198195  /* Stabs debugging sections.  */
    199196  .stab 0 : { *(.stab) }
    … …  
    229226  .debug_typenames 0 : { *(.debug_typenames) }
    230227  .debug_varnames  0 : { *(.debug_varnames) }
    231 
    232   stack : { _stack = .; *(.stack) } > onchip_ram
    233228  /* These must appear regardless of  .  */
    234229}

  • bsps/sh/gensh1/start/start.S

    r715d616 r511dc4b  
    6767        .align 2
    6868stack_k:
    69         .long   SYM(stack)
     69        .long   SYM(_Configuration_Interrupt_stack_area_end)
    7070edata_k:
    7171        .long   SYM(edata)
    … …  
    8181vects_size:
    8282        .word   255
    83 
    84 #ifdef __ELF__
    85         .section .stack,"aw"
    86 #else
    87         .section .stack
    88 #endif
    89 SYM(stack):
    90         .long   0xdeaddead

  • bsps/sh/gensh2/include/bsp.h

    r715d616 r511dc4b  
    6464
    6565/*
    66  * Defined in the linker script 'linkcmds'
    67  */
    68 extern void *CPU_Interrupt_stack_low;
    69 extern void *CPU_Interrupt_stack_high;
    70 
    71 /*
    7266 * BSP methods that cross file boundaries.
    7367 */

  • bsps/sh/gensh2/start/cpu_asm.c

    r715d616 r511dc4b  
    4343extern proc_ptr         _Hardware_isr_Table[];
    4444
    45 #if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
    46   unsigned long    *_old_stack_ptr;
    47 #endif
     45unsigned long *_old_stack_ptr;
    4846
    4947register unsigned long  *stack_ptr __asm__ ("r15");
    … …  
    137135  _Thread_Dispatch_disable();
    138136
    139 #if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
    140137  if ( _ISR_Nest_level == 0 )
    141138    {
    … …  
    144141      stack_ptr = _CPU_Interrupt_stack_high;
    145142    }
    146 
    147 #endif
    148143
    149144  _ISR_Nest_level++;
    … …  
    161156  _ISR_Nest_level--;
    162157
    163 #if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
    164 
    165158  if ( _ISR_Nest_level == 0 )
    166159    /* restore old stack pointer */
    167160    stack_ptr = _old_stack_ptr;
    168 #endif
    169161
    170162  _ISR_Local_enable( level );

  • bsps/sh/gensh2/start/linkcmds

    r715d616 r511dc4b  
    204204  } > onchip_ram
    205205
    206   _CPU_Interrupt_stack_low  = 0xFFFFF000;
    207   _CPU_Interrupt_stack_high = 0xFFFFFFFF;
    208 
    209206  /* Stabs debugging sections.  */
    210207  .stab 0 : { *(.stab) }
    … …  
    240237  .debug_typenames 0 : { *(.debug_typenames) }
    241238  .debug_varnames  0 : { *(.debug_varnames) }
    242 
    243   .stack 0xFFFFFEC0 : { _stack = .; *(.stack) } > onchip_ram
    244239  /* These must appear regardless of  .  */
    245240}

  • bsps/sh/gensh2/start/linkcmds.ram

    r715d616 r511dc4b  
    206206  } > onchip_ram
    207207
    208   _CPU_Interrupt_stack_low  = 0xFFFFF000;
    209   _CPU_Interrupt_stack_high = 0xFFFFFFFF;
    210 
    211208  /* Stabs debugging sections.  */
    212209  .stab 0 : { *(.stab) }
    … …  
    242239  .debug_typenames 0 : { *(.debug_typenames) }
    243240  .debug_varnames  0 : { *(.debug_varnames) }
    244 
    245   .stack 0xFFFFFEC0 : { _stack = .; *(.stack) } > onchip_ram
    246241  /* These must appear regardless of  .  */
    247242}

  • bsps/sh/gensh2/start/linkcmds.rom

    r715d616 r511dc4b  
    211211  } > onchip_ram
    212212
    213   _CPU_Interrupt_stack_low  = 0xFFFFF000;
    214   _CPU_Interrupt_stack_high = 0xFFFFFFFF;
    215 
    216213  /* Stabs debugging sections.  */
    217214  .stab 0 : { *(.stab) }
    … …  
    247244  .debug_typenames 0 : { *(.debug_typenames) }
    248245  .debug_varnames  0 : { *(.debug_varnames) }
    249 
    250   .stack 0xFFFFFEC0 : { _stack = .; *(.stack) } > onchip_ram
    251246  /* These must appear regardless of  .  */
    252247}

  • bsps/sh/gensh2/start/start.S

    r715d616 r511dc4b  
    156156        .align 2
    157157stack_k:
    158         .long   SYM(stack)
     158        .long   SYM(_Configuration_Interrupt_stack_area_end)
    159159edata_k:
    160160        .long   SYM(edata)
    … …  
    177177
    178178#ifdef __ELF__
    179         .section .stack,"aw"
    180 #else
    181         .section .stack
    182 #endif
    183 SYM(stack):
    184         .long   0xdeaddead
    185 
    186 #ifdef __ELF__
    187179        .section .bss,"aw"
    188180#else

  • bsps/sh/gensh2/start/start.ram

    r715d616 r511dc4b  
    159159        .align 2
    160160stack_k:
    161         .long   SYM(stack)     
     161        .long   SYM(_Configuration_Interrupt_stack_area_end)
    162162edata_k:
    163163        .long   SYM(edata)
    … …  
    180180
    181181#ifdef __ELF__
    182         .section .stack,"aw"
    183 #else
    184         .section .stack
    185 #endif
    186 SYM(stack):
    187         .long   0xdeaddead
    188 
    189 #ifdef __ELF__
    190182        .section .bss,"aw"
    191183#else

  • bsps/sh/gensh2/start/start.rom

    r715d616 r511dc4b  
    6868        .align 2
    6969stack_k:
    70         .long   SYM(stack)     
     70        .long   SYM(_Configuration_Interrupt_stack_area_end)
    7171edata_k:
    7272        .long   SYM(edata)
    … …  
    8282vects_size:
    8383        .word   255
    84 
    85 #ifdef __ELF__
    86         .section .stack,"aw"
    87 #else
    88         .section .stack
    89 #endif
    90 SYM(stack):
    91         .long   0xdeaddead

  • bsps/sh/gensh4/include/bsp.h

    r715d616 r511dc4b  
    5454
    5555/*
    56  * Defined in the linker script 'linkcmds'
    57  */
    58 
    59 extern void *CPU_Interrupt_stack_low;
    60 extern void *CPU_Interrupt_stack_high;
    61 
    62 /*
    6356 * Defined in start.S
    6457 */

  • bsps/sh/gensh4/start/cpu_asm.c

    r715d616 r511dc4b  
    4343extern proc_ptr         _Hardware_isr_Table[];
    4444
    45 #if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
    46   unsigned long    *_old_stack_ptr;
    47 #endif
     45unsigned long *_old_stack_ptr;
    4846
    4947register unsigned long  *stack_ptr __asm__ ("r15");
    … …  
    6159   _Thread_Dispatch_disable();
    6260
    63 #if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
    6461  if ( _ISR_Nest_level == 0 )
    6562    {
    … …  
    6865      stack_ptr = _CPU_Interrupt_stack_high;
    6966    }
    70 
    71 #endif
    7267
    7368  _ISR_Nest_level++;
    … …  
    8580  _ISR_Nest_level--;
    8681
    87 #if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
    8882  if ( _ISR_Nest_level == 0 )
    8983    /* restore old stack pointer */
    9084    stack_ptr = _old_stack_ptr;
    91 #endif
    9285
    9386  _ISR_Local_enable( level );

  • bsps/sh/gensh4/start/linkcmds

    r715d616 r511dc4b  
    145145  } > ram
    146146
    147   .stack : {
    148     . = . + 4096;
    149   } > ram
    150 
    151147  .rtemsstack (NOLOAD) : {
    152148    *(SORT(.rtemsstack.*))
    … …  
    154150
    155151  _WorkAreaBase = . ;
    156 
    157   . = ALIGN(16);
    158   _CPU_Interrupt_stack_low  = . ;
    159   _CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ;
    160152
    161153  /* Stabs debugging sections.  */

  • bsps/sh/gensh4/start/linkcmds.rom

    r715d616 r511dc4b  
    193193
    194194  _WorkAreaBase = . ;
    195 
    196   . = ALIGN(16);
    197   .stack . : {
    198      stack_start = .;
    199      . = . + 4096;
    200      stack_end = .;
    201   }
    202 
    203   . = ALIGN(16);
    204   _CPU_Interrupt_stack_low  = . ;
    205   _CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ;
    206195
    207196  /* Stabs debugging sections.  */
    … …  
    238227  .debug_typenames 0 : { *(.debug_typenames) }
    239228  .debug_varnames  0 : { *(.debug_varnames) }
    240   .stack : { _stack = .; *(.stack) }
    241229  /* These must appear regardless of  .  */
    242230}

  • bsps/sh/gensh4/start/linkcmds.rom2ram

    r715d616 r511dc4b  
    197197
    198198  _WorkAreaBase = . ;
    199 
    200   . = ALIGN(16);
    201   .stack . : {
    202      stack_start = .;
    203      . = . + 4096;
    204      stack_end = .;
    205   }
    206 
    207   . = ALIGN(16);
    208   _CPU_Interrupt_stack_low  = . ;
    209   _CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ;
    210199
    211200  /* Stabs debugging sections.  */
    … …  
    242231  .debug_typenames 0 : { *(.debug_typenames) }
    243232  .debug_varnames  0 : { *(.debug_varnames) }
    244   .stack : { _stack = .; *(.stack) }
    245233  /* These must appear regardless of  .  */
    246234}

  • bsps/sh/gensh4/start/start.S

    r715d616 r511dc4b  
    216216        .long   SYM(_VBR_Saved)
    217217stack_k:
    218         .long   SYM(stack)
     218        .long   SYM(_Configuration_Interrupt_stack_area_end)
    219219__bss_start_k:
    220220        .long   __bss_start
    … …  
    256256
    257257#ifdef __ELF__
    258         .section .stack,"aw"
    259 #else
    260         .section .stack
    261 #endif
    262 SYM(stack):
    263         .long   0xdeaddead
    264 
    265 #ifdef __ELF__
    266258        .section .bss,"aw"
    267259#else

  • bsps/sh/shared/start/bspstart.c

    r715d616 r511dc4b  
    5050
    5151  /*
    52    *  initialize the interrupt stack for this BSP
    53    */
    54   #if ( CPU_ALLOCATE_INTERRUPT_STACK == FALSE )
    55     _CPU_Interrupt_stack_low = &CPU_Interrupt_stack_low;
    56     _CPU_Interrupt_stack_high = &CPU_Interrupt_stack_high;
    57   #endif
    58 
    59   /*
    6052   *  initialize the device driver parameters
    6153   */

  • bsps/sh/shsim/include/bsp.h

    r715d616 r511dc4b  
    4747
    4848/*
    49  * Defined in the linker script 'linkcmds'
    50  */
    51 extern void *CPU_Interrupt_stack_low;
    52 extern void *CPU_Interrupt_stack_high;
    53 
    54 /*
    5549 * BSP methods that cross file boundaries.
    5650 */

  • bsps/sh/shsim/start/cpu_asm.c

    r715d616 r511dc4b  
    1919#include <rtems/score/sh.h>
    2020
    21 #if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
    22   unsigned long    *_old_stack_ptr;
    23 #endif
     21unsigned long  *_old_stack_ptr;
    2422
    2523register unsigned long  *stack_ptr __asm__ ("r15");
    … …  
    3836  _Thread_Dispatch_disable();
    3937
    40 #if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
    4138  if ( _ISR_Nest_level == 0 )
    4239    {
    … …  
    4542      stack_ptr = _CPU_Interrupt_stack_high;
    4643    }
    47 
    48 #endif
    4944
    5045  _ISR_Nest_level++;
    … …  
    6257  _ISR_Nest_level--;
    6358
    64 #if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
    65 
    6659  if ( _ISR_Nest_level == 0 )
    6760    /* restore old stack pointer */
    6861    stack_ptr = _old_stack_ptr;
    69 #endif
    7062
    7163  _ISR_Local_enable( level );

  • bsps/sh/shsim/start/linkcmds

    r715d616 r511dc4b  
    203203  PROVIDE (end = .);
    204204
    205   .stack : {
    206     . += 0x1000;
    207     *(.stack)
    208     _stack = .;
    209   } > ram
    210   _stack = .;
    211 
    212205  .rtemsstack (NOLOAD) : {
    213206    *(SORT(.rtemsstack.*))
    … …  
    215208
    216209  _WorkAreaBase = . ;
    217 
    218   _CPU_Interrupt_stack_low  = 0x00080000 ;
    219   _CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ;
    220210
    221211  /* Stabs debugging sections.  */
    … …  
    252242  .debug_typenames 0 : { *(.debug_typenames) }
    253243  .debug_varnames  0 : { *(.debug_varnames) }
    254 
    255 /*
    256   .stack 0x00081ff0 : { _stack = .; *(.stack) } > onchip_ram
    257 */
    258244  /* These must appear regardless of  .  */
    259245}

  • bsps/sh/shsim/start/start.S

    r715d616 r511dc4b  
    6969        .align 2
    7070stack_k:
    71         .long   SYM(stack)
     71        .long   SYM(_Configuration_Interrupt_stack_area_end)
    7272edata_k:
    7373        .long   SYM(edata)
    … …  
    8383vects_size:
    8484        .word   255
    85 
    86 #ifdef __ELF__
    87         .section .stack,"aw"
    88 #else
    89         .section .stack
    90 #endif
    91 SYM(stack):
    92         .long   0xdeaddead
    93 monvects_k:
    94         .long   SYM(monvects)

  • bsps/sparc/shared/start/bspgetworkarea.c

    r715d616 r511dc4b  
    2828void bsp_work_area_initialize(void)
    2929{
    30   /* must be identical to STACK_SIZE in start.S */
    31   #define STACK_SIZE (16 * 1024)
    32 
    3330  /* Early dynamic memory allocator is placed just above _end  */
    3431  void *work_area_start = (void *)&end;
    35   uintptr_t work_area_size  =
    36     (uintptr_t)rdb_start - (uintptr_t)&end - STACK_SIZE;
     32  uintptr_t work_area_size = (uintptr_t)rdb_start - (uintptr_t)work_area_start;
    3733
    3834  /*

  • bsps/sparc/shared/start/start.S

    r715d616 r511dc4b  
    266266#define PSR_INIT   0x10c0       /* Disable traps, set s and ps */
    267267#define WIM_INIT   2
    268 #define STACK_SIZE 16 * 1024
    269268
    270269        PUBLIC(hard_reset)
    … …  
    318317#endif
    319318
    320         set     (SYM(rdb_start)), %g5   ! End of RAM
     319        set     SYM(rdb_start), %g5     ! End of RAM
    321320        st      %sp, [%g5]
    322         sub     %sp, 4, %sp             ! stack starts at end of RAM - 4
     321        set     SYM(_Configuration_Interrupt_stack_size), %g5
     322#if defined(START_LEON3_ENABLE_SMP)
     323        add     %o0, 1, %o0
     324        smul    %o0, %g5, %g5
     325#endif
     326        set     SYM(_Configuration_Interrupt_stack_area_begin), %sp
     327        add     %sp, %g5, %sp
     328        sub     %sp, 4, %sp             ! stack starts at end of area - 4
    323329        andn    %sp, 0x0f, %sp          ! align stack on 16-byte boundary
    324330        mov     %sp, %fp                ! Set frame pointer

  • bsps/v850/gdbv850sim/start/linkcmds

    r715d616 r511dc4b  
    55_RamSize = DEFINED(_RamSize) ? _RamSize : 0x100000; /* default is 1MB */
    66_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0;
    7 _StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
    87
    98/* Default linker script, for normal executables */
    … …  
    193192        *(COMMON)
    194193  }
    195   . += _StackSize;
    196   _stack = .;
    197194  .rtemsstack (NOLOAD) : {
    198195    *(SORT(.rtemsstack.*))
    … …  
    234231  .debug_typenames 0    : { *(.debug_typenames) }
    235232  .debug_varnames  0    : { *(.debug_varnames) }
    236   /* libgloss - User stack.  */
    237 /*
    238   .stack 0x200000       :
    239   {
    240         __stack = .;
    241         *(.stack)
    242   }
    243 */
    244233}
    245234

  • bsps/v850/gdbv850sim/start/start.S

    r715d616 r511dc4b  
    1010        movea   255,            r0,     r20
    1111        mov     65535,          r21
    12         mov     hilo(_stack),   sp
     12        mov     hilo(__Configuration_Interrupt_stack_area_end), sp
    1313        mov     hilo(__ep),     ep
    1414        mov     hilo(__gp),     gp
    … …  
    3737        mov     r0,             r21
    3838        ori     65535,          r0,     r21
    39         movhi   hi(_stack),     r0,     sp
    40         movea   lo(_stack),     sp,     sp
     39        movhi   hi(__Configuration_Interrupt_stack_area_end),   r0,     sp
     40        movea   lo(__Configuration_Interrupt_stack_area_end),   sp,     sp
    4141        movhi   hi(__ep),       r0,     ep
    4242        movea   lo(__ep),       ep,     ep
    … …  
    6767# endif
    6868
    69 #if 0
    70         .section .stack
    71 _stack: .long   1
    72 #endif
    73 
    7469        .section .data
    7570        .global ___dso_handle

  • c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am

    r715d616 r511dc4b  
    2020dist_project_lib_DATA += ../../../../../../bsps/arm/altera-cyclone-v/start/linkcmds.altcycv
    2121dist_project_lib_DATA += ../../../../../../bsps/arm/altera-cyclone-v/start/linkcmds.altcycv_devkit
    22 dist_project_lib_DATA += ../../../../../../bsps/arm/altera-cyclone-v/start/linkcmds.altcycv_devkit_smp
    2322
    2423project_lib_LIBRARIES = librtemsbsp.a

  • c/src/lib/libbsp/arm/raspberrypi/configure.ac

    r715d616 r511dc4b  
    1111RTEMS_SOURCE_TOP
    1212RTEMS_BUILD_TOP
     13RTEMS_BSP_LINKCMDS
    1314
    1415RTEMS_CANONICAL_TARGET_CPU
    … …  
    3738AM_CONDITIONAL(RTEMS_RPI2,[test "$BSP_IS_RPI2" = "1"])
    3839
    39 # Hom many CPUs are used?
    40 RASPBERRYPI_CPUS="1"
    41 AS_IF([test "$rtems_cv_HAS_SMP" = "yes"],
    42       [RASPBERRYPI_CPUS="4"])
    43 
    44 AC_DEFUN([RASPBERRYPI_LINKCMD],[
    45 AC_ARG_VAR([$1],[$2; default $3])dnl
    46 [$1]=[$]{[$1]:-[$3]}
    47 ])
    48 
    49 RASPBERRYPI_LINKCMD([RASPBERRYPI_CPUS],[Number of active cores],[${RASPBERRYPI_CPUS}])
    50 
    5140RTEMS_BSP_CLEANUP_OPTIONS
    5241
    53 AC_CONFIG_FILES([
    54 Makefile
    55 linkcmds:../../../../../../bsps/arm/raspberrypi/start/linkcmds.in])
     42AC_CONFIG_FILES([Makefile])
    5643AC_OUTPUT

  • c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am

    r715d616 r511dc4b  
    2727project_lib_DATA += linkcmds
    2828dist_project_lib_DATA += ../../../../../../bsps/arm/realview-pbx-a9/start/linkcmds.realview_pbx_a9_qemu
    29 dist_project_lib_DATA += ../../../../../../bsps/arm/realview-pbx-a9/start/linkcmds.realview_pbx_a9_qemu_smp
    3029
    3130###############################################################################

  • c/src/lib/libbsp/arm/xilinx-zynq/configure.ac

    r715d616 r511dc4b  
    5858RTEMS_BSPOPTS_SET([ZYNQ_CONSOLE_USE_INTERRUPTS],[*],[1])
    5959RTEMS_BSPOPTS_HELP([ZYNQ_CONSOLE_USE_INTERRUPTS],[use interrupt driven mode for console devices (used by default)])
    60 
    61 ZYNQ_CPUS="1"
    62 AS_IF([test "$rtems_cv_HAS_SMP" = "yes"],
    63       [ZYNQ_CPUS="2"])
    6460
    6561#
    … …  
    127123])
    128124
    129 ZYNQ_LINKCMD([ZYNQ_CPUS],[Number of active cores],[${ZYNQ_CPUS}])
    130125ZYNQ_LINKCMD([ZYNQ_RAM_ORIGIN],[normal RAM region origin],[${ZYNQ_RAM_ORIGIN}])
    131126ZYNQ_LINKCMD([ZYNQ_RAM_LENGTH],[normal RAM region length],[${BSP_ZYNQ_RAM_LENGTH}])

  • cpukit/include/rtems/confdefs.h

    r715d616 r511dc4b  
    11831183#endif
    11841184
    1185 /**
    1186  * @brief Interrupt stack size configuration.
     1185/*
     1186 * Interrupt stack configuration.
    11871187 *
    11881188 * By default, the interrupt stack will be of minimum size.
    11891189 * The BSP or application may override this value.
    11901190 */
     1191
    11911192#ifndef CONFIGURE_INTERRUPT_STACK_SIZE
    11921193  #ifdef BSP_INTERRUPT_STACK_SIZE
    … …  
    11971198#endif
    11981199
    1199 /**
    1200  * This reserves memory for the interrupt stack if it is to be allocated
    1201  * by RTEMS rather than the BSP.
    1202  *
    1203  * @todo Try to get to the point where all BSPs support allocating the
    1204  *       memory from the Workspace.
    1205  */
    1206 #if (CPU_ALLOCATE_INTERRUPT_STACK == 0)
    1207   #define _CONFIGURE_INTERRUPT_STACK_MEMORY 0
    1208 #else
    1209   #define _CONFIGURE_INTERRUPT_STACK_MEMORY \
    1210      _Configure_From_workspace( CONFIGURE_INTERRUPT_STACK_SIZE )
     1200#if CONFIGURE_INTERRUPT_STACK_SIZE % CPU_INTERRUPT_STACK_ALIGNMENT != 0
     1201  #error "CONFIGURE_INTERRUPT_STACK_SIZE fails to meet the CPU port interrupt stack alignment"
     1202#endif
     1203
     1204#ifdef CONFIGURE_INIT
     1205  RTEMS_DEFINE_GLOBAL_SYMBOL(
     1206    _Configuration_Interrupt_stack_size,
     1207    CONFIGURE_INTERRUPT_STACK_SIZE
     1208  );
     1209
     1210  char _Configuration_Interrupt_stack_area_begin[
     1211    CONFIGURE_MAXIMUM_PROCESSORS * CONFIGURE_INTERRUPT_STACK_SIZE
     1212  ] RTEMS_ALIGNED( CPU_INTERRUPT_STACK_ALIGNMENT )
     1213  RTEMS_SECTION( ".rtemsstack.interrupt.begin" );
     1214
     1215  const char _Configuration_Interrupt_stack_area_end[ 0 ]
     1216    RTEMS_SECTION( ".rtemsstack.interrupt.end" ) = { };
    12111217#endif
    12121218
    … …  
    27212727 */
    27222728#define _CONFIGURE_MEMORY_FOR_SYSTEM_OVERHEAD \
    2723   ( _CONFIGURE_MEMORY_FOR_INTERNAL_TASKS + \
    2724     _CONFIGURE_INTERRUPT_STACK_MEMORY \
    2725   )
     2729  _CONFIGURE_MEMORY_FOR_INTERNAL_TASKS
    27262730
    27272731/**
    … …  
    27522756   _CONFIGURE_MEMORY_FOR_USER_EXTENSIONS(CONFIGURE_MAXIMUM_USER_EXTENSIONS) \
    27532757  )
    2754 
    2755 /*
    2756  * This macro provides a summation of the memory required by SMP as configured.
    2757  */
    2758 #if defined(RTEMS_SMP)
    2759   #define _CONFIGURE_MEMORY_FOR_SMP \
    2760      (CONFIGURE_MAXIMUM_PROCESSORS * \
    2761       _Configure_From_workspace( CONFIGURE_INTERRUPT_STACK_SIZE ) \
    2762      )
    2763 #else
    2764   #define _CONFIGURE_MEMORY_FOR_SMP 0
    2765 #endif
    27662758
    27672759/**
    … …  
    27842776   _CONFIGURE_MEMORY_FOR_STATIC_EXTENSIONS + \
    27852777   _CONFIGURE_MEMORY_FOR_MP + \
    2786    _CONFIGURE_MEMORY_FOR_SMP + \
    27872778   CONFIGURE_MESSAGE_BUFFER_MEMORY + \
    27882779   (CONFIGURE_MEMORY_OVERHEAD * 1024) + \
    … …  
    30833074    CONFIGURE_IDLE_TASK_BODY,                 /* user's IDLE task */
    30843075    CONFIGURE_IDLE_TASK_STACK_SIZE,           /* IDLE task stack size */
    3085     CONFIGURE_INTERRUPT_STACK_SIZE,           /* interrupt stack size */
    30863076    CONFIGURE_TASK_STACK_ALLOCATOR_INIT,      /* stack allocator init */
    30873077    CONFIGURE_TASK_STACK_ALLOCATOR,           /* stack allocator */
    … …  
    32403230
    32413231    /* System overhead pieces */
    3242     uint32_t INTERRUPT_STACK_MEMORY;
    32433232    uint32_t MEMORY_FOR_IDLE_TASK;
    32443233
    … …  
    32893278
    32903279    /* System overhead pieces */
    3291     _CONFIGURE_INTERRUPT_STACK_MEMORY,
    32923280    _CONFIGURE_MEMORY_FOR_INTERNAL_TASKS,
    32933281

  • cpukit/include/rtems/config.h

    r715d616 r511dc4b  
    185185  uint32_t                       idle_task_stack_size;
    186186
    187   /**
    188    * This field specifies the size of the interrupt stack.  If less than or
    189    * equal to the minimum stack size, then the interrupt stack will be of
    190    * minimum stack size.
    191    */
    192   uint32_t                       interrupt_stack_size;
    193 
    194187  /**
    195188   * @brief Optional task stack allocator initialization hook.
    … …  
    314307        (Configuration.idle_task_stack_size)
    315308
     309/**
     310 * @brief Global symbol with a value equal to the configure interrupt stack size.
     311 *
     312 * This global symbol is defined by the application configuration option
     313 * CONFIGURE_INIT_TASK_STACK_SIZE via <rtems/confdefs.h>.
     314 */
     315RTEMS_DECLARE_GLOBAL_SYMBOL( _Configuration_Interrupt_stack_size );
     316
     317/**
     318 * @brief The interrupt stack area begin.
     319 *
     320 * The interrupt stack area is defined by the application configuration via
     321 * <rtems/confdefs.h>.  The size of the area depends on
     322 * CONFIGURE_INIT_TASK_STACK_SIZE and CONFIGURE_MAXIMUM_PROCESSORS.
     323 */
     324extern char _Configuration_Interrupt_stack_area_begin[];
     325
     326/**
     327 * @brief The interrupt stack area end.
     328 *
     329 * The interrupt stack area is defined by the application configuration via
     330 * <rtems/confdefs.h>.  The size of the area depends on
     331 * CONFIGURE_INIT_TASK_STACK_SIZE and CONFIGURE_MAXIMUM_PROCESSORS.
     332 */
     333extern const char _Configuration_Interrupt_stack_area_end[];
     334
    316335#define rtems_configuration_get_interrupt_stack_size() \
    317         (Configuration.interrupt_stack_size)
     336        ((size_t) _Configuration_Interrupt_stack_size)
    318337
    319338#define rtems_configuration_get_stack_allocate_init_hook() \

  • cpukit/include/rtems/score/percpu.h

    r715d616 r511dc4b  
    294294  #endif
    295295
    296   #if (CPU_ALLOCATE_INTERRUPT_STACK == TRUE) || \
    297       (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
    298     /**
    299      * This contains a pointer to the lower range of the interrupt stack for
    300      * this CPU.  This is the address allocated and freed.
    301      */
    302     void  *interrupt_stack_low;
    303 
    304     /**
    305      * This contains a pointer to the interrupt stack pointer for this CPU.
    306      * It will be loaded at the beginning on an ISR.
    307      */
    308     void  *interrupt_stack_high;
    309   #endif
     296  /**
     297   * @brief The interrupt stack low address for this processor.
     298   */
     299  void *interrupt_stack_low;
     300
     301  /**
     302   * @brief The interrupt stack high address for this processor.
     303   */
     304  void *interrupt_stack_high;
    310305
    311306  /**
    … …  
    801796#if defined( ASM ) || defined( _RTEMS_PERCPU_DEFINE_OFFSETS )
    802797
    803 #if (CPU_ALLOCATE_INTERRUPT_STACK == TRUE) || \
    804     (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
    805   /*
    806    *  If this CPU target lets RTEMS allocates the interrupt stack, then
    807    *  we need to have places in the per CPU table to hold them.
    808    */
    809   #define PER_CPU_INTERRUPT_STACK_LOW \
    810     CPU_PER_CPU_CONTROL_SIZE
    811   #define PER_CPU_INTERRUPT_STACK_HIGH \
    812     PER_CPU_INTERRUPT_STACK_LOW + CPU_SIZEOF_POINTER
    813   #define PER_CPU_END_STACK             \
    814     PER_CPU_INTERRUPT_STACK_HIGH + CPU_SIZEOF_POINTER
    815 
    816   #define INTERRUPT_STACK_LOW \
    817     (SYM(_Per_CPU_Information) + PER_CPU_INTERRUPT_STACK_LOW)
    818   #define INTERRUPT_STACK_HIGH \
    819     (SYM(_Per_CPU_Information) + PER_CPU_INTERRUPT_STACK_HIGH)
    820 #else
    821   #define PER_CPU_END_STACK \
    822     CPU_PER_CPU_CONTROL_SIZE
    823 #endif
     798#define PER_CPU_INTERRUPT_STACK_LOW \
     799  CPU_PER_CPU_CONTROL_SIZE
     800#define PER_CPU_INTERRUPT_STACK_HIGH \
     801  PER_CPU_INTERRUPT_STACK_LOW + CPU_SIZEOF_POINTER
     802
     803#define INTERRUPT_STACK_LOW \
     804  (SYM(_Per_CPU_Information) + PER_CPU_INTERRUPT_STACK_LOW)
     805#define INTERRUPT_STACK_HIGH \
     806  (SYM(_Per_CPU_Information) + PER_CPU_INTERRUPT_STACK_HIGH)
    824807
    825808/*
    … …  
    827810 */
    828811#define PER_CPU_ISR_NEST_LEVEL \
    829   PER_CPU_END_STACK
     812  PER_CPU_INTERRUPT_STACK_HIGH + CPU_SIZEOF_POINTER
    830813#define PER_CPU_ISR_DISPATCH_DISABLE \
    831814  PER_CPU_ISR_NEST_LEVEL + 4

  • cpukit/libmisc/stackchk/check.c

    r715d616 r511dc4b  
    182182void rtems_stack_checker_begin_extension( Thread_Control *executing )
    183183{
    184 #if (CPU_ALLOCATE_INTERRUPT_STACK == TRUE)
    185184  Per_CPU_Control *cpu_self;
    186185  uint32_t         cpu_self_index;
    … …  
    214213#if defined(RTEMS_SMP)
    215214  _Thread_Dispatch_enable( cpu_self );
    216 #endif
    217215#endif
    218216}

  • cpukit/score/cpu/arm/include/rtems/score/cpu.h

    r715d616 r511dc4b  
    105105 */
    106106#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
    107 
    108 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
    109 
    110 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
    111 
    112 #define CPU_ALLOCATE_INTERRUPT_STACK FALSE
    113107
    114108#define CPU_ISR_PASSES_FRAME_POINTER FALSE

  • cpukit/score/cpu/bfin/cpu.c

    r715d616 r511dc4b  
    199199    the_context->imask = new_level ? 0 : 0xffff;
    200200}
    201 
    202 
    203 
    204 /*
    205  *  _CPU_Install_interrupt_stack
    206  *
    207  *  NO_CPU Specific Information:
    208  *
    209  *  XXX document implementation including references if appropriate
    210  */
    211 
    212 void _CPU_Install_interrupt_stack( void )
    213 {
    214 }

  • cpukit/score/cpu/bfin/include/rtems/score/cpu.h

    r715d616 r511dc4b  
    3131/* conditional compilation parameters */
    3232
    33 /**
    34  * Does RTEMS manage a dedicated interrupt stack in software?
    35  *
    36  * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
    37  * If FALSE, nothing is done.
    38  *
    39  * If the CPU supports a dedicated interrupt stack in hardware,
    40  * then it is generally the responsibility of the BSP to allocate it
    41  * and set it up.
    42  *
    43  * If the CPU does not support a dedicated interrupt stack, then
    44  * the porter has two options: (1) execute interrupts on the
    45  * stack of the interrupted task, and (2) have RTEMS manage a dedicated
    46  * interrupt stack.
    47  *
    48  * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
    49  *
    50  * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
    51  * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
    52  * possible that both are FALSE for a particular CPU.  Although it
    53  * is unclear what that would imply about the interrupt processing
    54  * procedure on that CPU.
    55  *
    56  * Port Specific Information:
    57  *
    58  * XXX document implementation including references if appropriate
    59  */
    60 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
    61 
    6233/*
    6334 *  Does the CPU follow the simple vectored interrupt model?
    … …  
    7243 */
    7344#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
    74 
    75 /**
    76  * Does this CPU have hardware support for a dedicated interrupt stack?
    77  *
    78  * If TRUE, then it must be installed during initialization.
    79  * If FALSE, then no installation is performed.
    80  *
    81  * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
    82  *
    83  * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
    84  * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
    85  * possible that both are FALSE for a particular CPU.  Although it
    86  * is unclear what that would imply about the interrupt processing
    87  * procedure on that CPU.
    88  *
    89  * Port Specific Information:
    90  *
    91  * XXX document implementation including references if appropriate
    92  */
    93 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
    94 
    95 /**
    96  * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
    97  *
    98  * If TRUE, then the memory is allocated during initialization.
    99  * If FALSE, then the memory is allocated during initialization.
    100  *
    101  * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
    102  *
    103  * Port Specific Information:
    104  *
    105  * XXX document implementation including references if appropriate
    106  */
    107 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE
    10845
    10946/**
    … …  
    403340/**
    404341 * @defgroup CPUInterrupt Processor Dependent Interrupt Management
    405  *
    406  * On some CPUs, RTEMS supports a software managed interrupt stack.
    407  * This stack is allocated by the Interrupt Manager and the switch
    408  * is performed in @ref _ISR_Handler.  These variables contain pointers
    409  * to the lowest and highest addresses in the chunk of memory allocated
    410  * for the interrupt stack.  Since it is unknown whether the stack
    411  * grows up or down (in general), this give the CPU dependent
    412  * code the option of picking the version it wants to use.
    413  *
    414  * @note These two variables are required if the macro
    415  *       @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
    416  *
    417  * Port Specific Information:
    418  *
    419  * XXX document implementation including references if appropriate
    420342 */
    421343/**@{**/
    … …  
    817739
    818740/**
    819  * @ingroup CPUInterrupt
    820  * This routine installs the hardware interrupt stack pointer.
    821  *
    822  * @note  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
    823  *        is TRUE.
    824  *
    825  * Port Specific Information:
    826  *
    827  * XXX document implementation including references if appropriate
    828  */
    829 void _CPU_Install_interrupt_stack( void );
    830 
    831 /**
    832741 * This routine is the CPU dependent IDLE thread body.
    833742 *

  • cpukit/score/cpu/epiphany/cpu.c

    r715d616 r511dc4b  
    8484}
    8585
    86 void _CPU_Install_interrupt_stack( void )
    87 {
    88   /* Do nothing */
    89 }
    90 
    9186CPU_Counter_ticks _CPU_Counter_read( void )
    9287{

  • cpukit/score/cpu/epiphany/include/rtems/score/cpu.h

    r715d616 r511dc4b  
    4949
    5050/* conditional compilation parameters */
    51 
    52 /*
    53  *  Does RTEMS manage a dedicated interrupt stack in software?
    54  *
    55  *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
    56  *  If FALSE, nothing is done.
    57  *
    58  *  If the CPU supports a dedicated interrupt stack in hardware,
    59  *  then it is generally the responsibility of the BSP to allocate it
    60  *  and set it up.
    61  *
    62  *  If the CPU does not support a dedicated interrupt stack, then
    63  *  the porter has two options: (1) execute interrupts on the
    64  *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
    65  *  interrupt stack.
    66  *
    67  *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
    68  *
    69  *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
    70  *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
    71  *  possible that both are FALSE for a particular CPU.  Although it
    72  *  is unclear what that would imply about the interrupt processing
    73  *  procedure on that CPU.
    74  *
    75  *  Currently, for epiphany port, _ISR_Handler is responsible for switching to
    76  *  RTEMS dedicated interrupt task.
    77  *
    78  */
    79 
    80 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
    81 
    82 /*
    83  *  Does this CPU have hardware support for a dedicated interrupt stack?
    84  *
    85  *  If TRUE, then it must be installed during initialization.
    86  *  If FALSE, then no installation is performed.
    87  *
    88  *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
    89  *
    90  *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
    91  *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
    92  *  possible that both are FALSE for a particular CPU.  Although it
    93  *  is unclear what that would imply about the interrupt processing
    94  *  procedure on that CPU.
    95  *
    96  */
    97 
    98 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
    99 
    100 /*
    101  *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
    102  *
    103  *  If TRUE, then the memory is allocated during initialization.
    104  *  If FALSE, then the memory is allocated during initialization.
    105  *
    106  *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
    107  *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
    108  *
    109  */
    110 
    111 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE
    11251
    11352/*
    … …  
    729668
    730669/*
    731  *  _CPU_Install_interrupt_stack
    732  *
    733  *  This routine installs the hardware interrupt stack pointer.
    734  *
    735  *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
    736  *         is TRUE.
    737  *
    738  */
    739 
    740 void _CPU_Install_interrupt_stack( void );
    741 
    742 /*
    743670 *  _CPU_Thread_Idle_body
    744671 *

  • cpukit/score/cpu/i386/include/rtems/score/cpu.h

    r715d616 r511dc4b  
    4949 */
    5050#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
    51 
    52 /*
    53  *  i386 has an RTEMS allocated and managed interrupt stack.
    54  */
    55 
    56 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
    57 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
    58 #define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
    5951
    6052/*

  • cpukit/score/cpu/lm32/cpu.c

    r715d616 r511dc4b  
    102102
    103103/*
    104  *  _CPU_Install_interrupt_stack
    105  *
    106  *  LM32 Specific Information:
    107  *
    108  *  XXX document implementation including references if appropriate
    109  */
    110 
    111 void _CPU_Install_interrupt_stack( void )
    112 {
    113 }
    114 
    115 /*
    116104 *  _CPU_Thread_Idle_body
    117105 *

  • cpukit/score/cpu/lm32/include/rtems/score/cpu.h

    r715d616 r511dc4b  
    3030
    3131/**
    32  * Does RTEMS manage a dedicated interrupt stack in software?
    33  *
    34  * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
    35  * If FALSE, nothing is done.
    36  *
    37  * If the CPU supports a dedicated interrupt stack in hardware,
    38  * then it is generally the responsibility of the BSP to allocate it
    39  * and set it up.
    40  *
    41  * If the CPU does not support a dedicated interrupt stack, then
    42  * the porter has two options: (1) execute interrupts on the
    43  * stack of the interrupted task, and (2) have RTEMS manage a dedicated
    44  * interrupt stack.
    45  *
    46  * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
    47  *
    48  * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
    49  * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
    50  * possible that both are FALSE for a particular CPU.  Although it
    51  * is unclear what that would imply about the interrupt processing
    52  * procedure on that CPU.
    53  *
    54  * Port Specific Information:
    55  *
    56  * XXX document implementation including references if appropriate
    57  */
    58 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
    59 
    60 /**
    6132 * Does the CPU follow the simple vectored interrupt model?
    6233 *
    … …  
    7041 */
    7142#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
    72 
    73 /**
    74  * Does this CPU have hardware support for a dedicated interrupt stack?
    75  *
    76  * If TRUE, then it must be installed during initialization.
    77  * If FALSE, then no installation is performed.
    78  *
    79  * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
    80  *
    81  * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
    82  * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
    83  * possible that both are FALSE for a particular CPU.  Although it
    84  * is unclear what that would imply about the interrupt processing
    85  * procedure on that CPU.
    86  *
    87  * Port Specific Information:
    88  *
    89  * XXX document implementation including references if appropriate
    90  */
    91 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
    92 
    93 /**
    94  * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
    95  *
    96  * If TRUE, then the memory is allocated during initialization.
    97  * If FALSE, then the memory is allocated during initialization.
    98  *
    99  * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
    100  *
    101  * Port Specific Information:
    102  *
    103  * XXX document implementation including references if appropriate
    104  */
    105 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE
    10643
    10744/**
    … …  
    427364/**
    428365 * @defgroup CPUInterrupt Processor Dependent Interrupt Management
    429  *
    430  * On some CPUs, RTEMS supports a software managed interrupt stack.
    431  * This stack is allocated by the Interrupt Manager and the switch
    432  * is performed in @ref _ISR_Handler.  These variables contain pointers
    433  * to the lowest and highest addresses in the chunk of memory allocated
    434  * for the interrupt stack.  Since it is unknown whether the stack
    435  * grows up or down (in general), this give the CPU dependent
    436  * code the option of picking the version it wants to use.
    437  *
    438  * NOTE: These two variables are required if the macro
    439  *       @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
    440  *
    441  * Port Specific Information:
    442  *
    443  * XXX document implementation including references if appropriate
    444366 */
    445367/**@{**/
    … …  
    848770);
    849771
    850 /**
    851  * This routine installs the hardware interrupt stack pointer.
    852  *
    853  * NOTE:  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
    854  *        is TRUE.
    855  *
    856  * Port Specific Information:
    857  *
    858  * XXX document implementation including references if appropriate
    859  */
    860 void _CPU_Install_interrupt_stack( void );
    861 
    862772/** @} */
    863773

  • cpukit/score/cpu/lm32/irq.c

    r715d616 r511dc4b  
    2222#include <rtems/score/threaddispatch.h>
    2323
    24 #if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
    25   unsigned long    *_old_stack_ptr;
    26 #endif
     24unsigned long *_old_stack_ptr;
    2725
    2826void *_exception_stack_frame;
    … …  
    4543  _Thread_Dispatch_disable();
    4644
    47 #if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
    4845  if ( _ISR_Nest_level == 0 ) {
    4946    /* Install irq stack */
    … …  
    5148    stack_ptr = _CPU_Interrupt_stack_high - 4;
    5249  }
    53 #endif
    5450
    5551  _ISR_Nest_level++;
    … …  
    6561  _ISR_Nest_level--;
    6662
    67 #if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
    6863  if( _ISR_Nest_level == 0)
    6964    stack_ptr = _old_stack_ptr;
    70 #endif
    7165
    7266  _Thread_Dispatch_unnest( _Per_CPU_Get() );

  • cpukit/score/cpu/m32c/cpu.c

    r715d616 r511dc4b  
    114114
    115115/*
    116  *  _CPU_Install_interrupt_stack
    117  *
    118  *  NO_CPU Specific Information:
    119  *
    120  *  XXX document implementation including references if appropriate
    121  */
    122 
    123 void _CPU_Install_interrupt_stack( void )
    124 {
    125 }
    126 
    127 /*
    128116 *  _CPU_Thread_Idle_body
    129117 *

  • cpukit/score/cpu/m32c/cpu_asm.c

    r715d616 r511dc4b  
    7474   *  may need to save some special interrupt information for exit
    7575   *
    76    *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
    77    *    if ( _ISR_Nest_level == 0 )
    78    *      switch to software interrupt stack
    79    *  #endif
     76   *  if ( _ISR_Nest_level == 0 )
     77   *    switch to software interrupt stack
    8078   *
    8179   *  _ISR_Nest_level++;
    … …  
    10199   *
    102100   *  LABEL "exit interrupt (simple case):
    103    *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
    104    *    if outermost interrupt
    105    *      restore stack
    106    *  #endif
     101   *  if outermost interrupt
     102   *    restore stack
    107103   *  prepare to get out of interrupt
    108104   *  return from interrupt

  • cpukit/score/cpu/m32c/include/rtems/score/cpu.h

    r715d616 r511dc4b  
    4646
    4747/**
    48  * Does RTEMS manage a dedicated interrupt stack in software?
    49  *
    50  * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
    51  * If FALSE, nothing is done.
    52  *
    53  * If the CPU supports a dedicated interrupt stack in hardware,
    54  * then it is generally the responsibility of the BSP to allocate it
    55  * and set it up.
    56  *
    57  * If the CPU does not support a dedicated interrupt stack, then
    58  * the porter has two options: (1) execute interrupts on the
    59  * stack of the interrupted task, and (2) have RTEMS manage a dedicated
    60  * interrupt stack.
    61  *
    62  * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
    63  *
    64  * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
    65  * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
    66  * possible that both are FALSE for a particular CPU.  Although it
    67  * is unclear what that would imply about the interrupt processing
    68  * procedure on that CPU.
    69  *
    70  * Port Specific Information:
    71  *
    72  * XXX document implementation including references if appropriate
    73  */
    74 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
    75 
    76 /**
    7748 * Does the CPU follow the simple vectored interrupt model?
    7849 *
    … …  
    8657 */
    8758#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
    88 
    89 /**
    90  * Does this CPU have hardware support for a dedicated interrupt stack?
    91  *
    92  * If TRUE, then it must be installed during initialization.
    93  * If FALSE, then no installation is performed.
    94  *
    95  * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
    96  *
    97  * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
    98  * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
    99  * possible that both are FALSE for a particular CPU.  Although it
    100  * is unclear what that would imply about the interrupt processing
    101  * procedure on that CPU.
    102  *
    103  * Port Specific Information:
    104  *
    105  * XXX document implementation including references if appropriate
    106  */
    107 #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
    108 
    109 /**
    110  * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
    111  *
    112  * If TRUE, then the memory is allocated during initialization.
    113  * If FALSE, then the memory is allocated during initialization.
    114  *
    115  * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
    116  *
    117  * Port Specific Information:
    118  *
    119  * XXX document implementation including references if appropriate
    120  */
    121 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE
    12259
    12360/**
    … …  
    410347/**
    411348 * @defgroup CPUInterrupt Processor Dependent Interrupt Management
    412  *
    413  * On some CPUs, RTEMS supports a software managed interrupt stack.
    414  * This stack is allocated by the Interrupt Manager and the switch
    415  * is performed in @ref _ISR_Handler.  These variables contain pointers
    416  * to the lowest and highest addresses in the chunk of memory allocated
    417  * for the interrupt stack.  Since it is unknown whether the stack
    418  * grows up or down (in general), this give the CPU dependent
    419  * code the option of picking the version it wants to use.
    420  *
    421  * NOTE: These two variables are required if the macro
    422  *       @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
    423  *
    424  * Port Specific Information:
    425  *
    426  * XXX document implementation including references if appropriate
    427  *
    428349 */
    429350/**@{**/
    … …  
    837758
    838759/**
    839  * @ingroup CPUInterrupt
    840  *
    841  * This routine installs the hardware interrupt stack pointer.
    842  *
    843  * NOTE:  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
    844  *        is TRUE.
    845  *
    846  * Port Specific Information:
    847  *
    848  * XXX document implementation including references if appropriate
    849  */
    850 void _CPU_Install_interrupt_stack( void );
    851 
    852 /**
    853760 * This routine is the CPU dependent IDLE thread body.
    854761 *

  • cpukit/score/cpu/m68k/cpu.c

    r715d616 r511dc4b  
    2121#include <rtems/score/percpu.h>
    2222#include <rtems/score/tls.h>
     23#include <rtems/config.h>
    2324
    2425#if ( M68K_HAS_VBR == 0 )
    … …  
    5859  uint32_t _CPU_cacr_shadow;
    5960#endif
     61
     62static void m68k_install_interrupt_stack( void )
     63{
     64#if ( M68K_HAS_SEPARATE_STACKS == 1 )
     65  uintptr_t isp = (uintptr_t) _Configuration_Interrupt_stack_area_end;
     66
     67  __asm__ volatile ( "movec %0,%%isp" : "=r" (isp) : "0" (isp) );
     68#endif
     69}
    6070
    6171void _CPU_Initialize(void)
    … …  
    7585  }
    7686#endif /* M68K_HAS_VBR */
     87
     88  m68k_install_interrupt_stack();
    7789}
    7890
    … …  
    150162
    151163  _ISR_Vector_table[ vector ] = new_handler;
    152 }
    153 
    154 
    155 /*
    156  *  _CPU_Install_interrupt_stack
    157  */
    158 
    159 void _CPU_Install_interrupt_stack( void )
    160 {
    161 #if ( M68K_HAS_SEPARATE_STACKS == 1 )
    162   void *isp = _CPU_Interrupt_stack_high;
    163 
    164   __asm__ volatile ( "movec %0,%%isp" : "=r" (isp) : "0" (isp) );
    165 #endif
    166164}
    167165

  • cpukit/score/cpu/m68k/cpu_asm.S

    r715d616 r511dc4b  
    260260
    261261
    262 #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )
     262#if ( M68K_HAS_SEPARATE_STACKS == 0 )
    263263        | Make a0 point just above interrupt stack
    264264        movel   INTERRUPT_STACK_HIGH,a0
    … …  
    273273                                        |     on interrupt stack
    2742742:
    275 #endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */
     275#endif /* M68K_HAS_SEPARATE_STACKS == 0 */
    276276
    277277        addql   #1,ISR_NEST_LEVEL        | one nest level deeper
    … …  
    286286        subql   #1,ISR_NEST_LEVEL        | Reduce interrupt-nesting count
    287287
    288 #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )
     288#if ( M68K_HAS_SEPARATE_STACKS == 0 )
    289289        movel   INTERRUPT_STACK_HIGH,a0
    290290        subql   #4,a0
    … …  
    293293        movel   (a7),a7                 | Restore task stack pointer
    2942941:
    295 #endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */
     295#endif /* M68K_HAS_SEPARATE_STACKS == 0 */
    296296        subql   #1,THREAD_DISPATCH_DISABLE_LEVEL
    297297                                         | unnest multitasking

  • cpukit/score/cpu/m68k/include/rtems/score/cpu.h

    r715d616 r511dc4b  
    4141 */
    4242#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
    43 
    44 /*
    45  *  Use the m68k's hardware interrupt stack support and have the
    46  *  interrupt manager allocate the memory for it.
    47  */
    48 
    49 #if ( M68K_HAS_SEPARATE_STACKS == 1)
    50 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0
    51 #define CPU_HAS_HARDWARE_INTERRUPT_STACK 1
    52 #else
    53 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1
    54 #define CPU_HAS_HARDWARE_INTERRUPT_STACK 0
    55 #endif
    56 #define CPU_ALLOCATE_INTERRUPT_STACK     1
    5743
    5844/*
    … …  
    616602
    617603/*
    618  *  _CPU_Install_interrupt_stack
    619  *
    620  *  This routine installs the hardware interrupt stack pointer.
    621  */
    622 
    623 void _CPU_Install_interrupt_stack( void );
    624 
    625 /*
    626604 *  _CPU_Context_switch
    627605 *

  • cpukit/score/cpu/mips/cpu.c

    r715d616 r511dc4b  
    167167}
    168168
    169 void _CPU_Install_interrupt_stack( void )
    170 {
    171 /* we don't support this yet */
    172 }
    173 
    174169void _CPU_Context_Initialize(
    175170  Context_Control  *the_context,

  • cpukit/score/cpu/mips/cpu_asm.S

    r715d616 r511dc4b  
    873873   *  may need to save some special interrupt information for exit
    874874   *
    875    *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
    876    *    if ( _ISR_Nest_level == 0 )
    877    *      switch to software interrupt stack
    878    *  #endif
     875   *  if ( _ISR_Nest_level == 0 )
     876   *    switch to software interrupt stack
    879877   */
    880878
    … …  
    940938
    941939  /*
    942    *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
    943    *    restore stack
    944    *  #endif
     940   *  restore stack
    945941   *
    946942   *  if !_Thread_Dispatch_necessary

  • cpukit/score/cpu/mips/include/rtems/score/cpu.h

    r715d616 r511dc4b  
    6363
    6464/*
    65  *  Does RTEMS manage a dedicated interrupt stack in software?
    66  *
    67  *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
    68  *  If FALSE, nothing is done.
    69  *
    70  *  If the CPU supports a dedicated interrupt stack in hardware,
    71  *  then it is generally the responsibility of the BSP to allocate it
    72  *  and set it up.
    73  *
    74  *  If the CPU does not support a dedicated interrupt stack, then
    75  *  the porter has two options: (1) execute interrupts on the
    76  *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
    77  *  interrupt stack.
    78  *
    79  *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
    80  *
    81  *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
    82  *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
    83  *  possible that both are FALSE for a particular CPU.  Although it
    84  *  is unclear what that would imply about the interrupt processing
    85  *  procedure on that CPU.
    86  */
    87 
    88 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
    89 
    90 /*
    9165 *  Does the CPU follow the simple vectored interrupt model?
    9266 *
    … …  
    10175 */
    10276#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
    103 
    104 /*
    105  *  Does this CPU have hardware support for a dedicated interrupt stack?
    106  *
    107  *  If TRUE, then it must be installed during initialization.
    108  *  If FALSE, then no installation is performed.
    109  *
    110  *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
    111  *
    112  *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
    113  *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
    114  *  possible that both are FALSE for a particular CPU.  Although it
    115  *  is unclear what that would imply about the interrupt processing
    116  *  procedure on that CPU.
    117  */
    118 
    119 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
    120 
    121 /*
    122  *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
    123  *
    124  *  If TRUE, then the memory is allocated during initialization.
    125  *  If FALSE, then the memory is allocated during initialization.
    126  *
    127  *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
    128  */
    129 
    130 #define CPU_ALLOCATE_INTERRUPT_STACK FALSE
    13177
    13278/*
    … …  
    872818
    873819/*
    874  *  _CPU_Install_interrupt_stack
    875  *
    876  *  This routine installs the hardware interrupt stack pointer.
    877  *
    878  *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
    879  *         is TRUE.
    880  */
    881 
    882 void _CPU_Install_interrupt_stack( void );
    883 
    884 /*
    885820 *  _CPU_Internal_threads_Idle_thread_body
    886821 *

  • cpukit/score/cpu/moxie/cpu.c

    r715d616 r511dc4b  
    106106
    107107/*
    108  *  _CPU_Install_interrupt_stack
    109  */
    110 void _CPU_Install_interrupt_stack( void )
    111 {
    112 }
    113 
    114 /*
    115108 *  _CPU_Thread_Idle_body
    116109 *

  • cpukit/score/cpu/moxie/include/rtems/score/cpu.h

    r715d616 r511dc4b  
    3939
    4040/*
    41  *  Does RTEMS manage a dedicated interrupt stack in software?
    42  *
    43  *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
    44  *  If FALSE, nothing is done.
    45  *
    46  *  If the CPU supports a dedicated interrupt stack in hardware,
    47  *  then it is generally the responsibility of the BSP to allocate it
    48  *  and set it up.
    49  *
    50  *  If the CPU does not support a dedicated interrupt stack, then
    51  *  the porter has two options: (1) execute interrupts on the
    52  *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
    53  *  interrupt stack.
    54  *
    55  *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
    56  *
    57  *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
    58  *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
    59  *  possible that both are FALSE for a particular CPU.  Although it
    60  *  is unclear what that would imply about the interrupt processing
    61  *  procedure on that CPU.
    62  *
    63  *  MOXIE Specific Information:
    64  *
    65  *  XXX
    66  */
    67 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
    68 
    69 /*
    7041 *  Does the CPU follow the simple vectored interrupt model?
    7142 *
    … …  
    7950 */
    8051#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
    81 
    82 /*
    83  *  Does this CPU have hardware support for a dedicated interrupt stack?
    84  *
    85  *  If TRUE, then it must be installed during initialization.
    86  *  If FALSE, then no installation is performed.
    87  *
    88  *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
    89  *
    90  *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
    91  *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
    92  *  possible that both are FALSE for a particular CPU.  Although it
    93  *  is unclear what that would imply about the interrupt processing
    94  *  procedure on that CPU.
    95  *
    96  *  MOXIE Specific Information:
    97  *
    98  *  XXX
    99  */
    100 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
    101 
    102 /*
    103  *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
    104  *
    105  *  If TRUE, then the memory is allocated during initialization.
    106  *  If FALSE, then the memory is allocated during initialization.
    107  *
    108  *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
    109  *
    110  *  MOXIE Specific Information:
    111  *
    112  *  XXX
    113  */
    114 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE
    11552
    11653/*
    … …  
    680617
    681618/*
    682  *  _CPU_Install_interrupt_stack
    683  *
    684  *  This routine installs the hardware interrupt stack pointer.
    685  *
    686  *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
    687  *         is TRUE.
    688  *
    689  *  MOXIE Specific Information:
    690  *
    691  *  XXX
    692  */
    693 void _CPU_Install_interrupt_stack( void );
    694 
    695 /*
    696619 *  _CPU_Internal_threads_Idle_thread_body
    697620 *

  • cpukit/score/cpu/nios2/include/rtems/score/cpu.h

    r715d616 r511dc4b  
    2828#include <rtems/score/nios2.h>
    2929
    30 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
    31 
    3230#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
    3331
    … …  
    3735
    3836#define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE
    39 
    40 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
    41 
    42 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE
    4337
    4438#define CPU_ISR_PASSES_FRAME_POINTER FALSE

  • cpukit/score/cpu/nios2/nios2-iic-irq.c

    r715d616 r511dc4b  
    3333 */
    3434
    35 #if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
    36   unsigned long    *_old_stack_ptr;
    37 #endif
     35unsigned long *_old_stack_ptr;
    3836
    3937/*
    … …  
    9997  /* Interrupts are disabled upon entry to this Handler */
    10098
    101 #if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
    10299  if ( _ISR_Nest_level == 0 ) {
    103100    /* Install irq stack */
    … …  
    105102    stack_ptr = _CPU_Interrupt_stack_high - 4;
    106103  }
    107 #endif
    108104
    109105  _ISR_Nest_level++;
    … …  
    121117
    122118  if( _ISR_Nest_level == 0) {
    123 #if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
    124119    stack_ptr = _old_stack_ptr;
    125 #endif
    126120
    127121    if( _Thread_Dispatch_is_enabled() )

  • cpukit/score/cpu/no_cpu/cpu.c

    r715d616 r511dc4b  
    8888
    8989/*
    90  *  _CPU_Install_interrupt_stack
    91  *
    92  *  NO_CPU Specific Information:
    93  *
    94  *  XXX document implementation including references if appropriate
    95  */
    96 
    97 void _CPU_Install_interrupt_stack( void )
    98 {
    99 }
    100 
    101 /*
    10290 *  _CPU_Thread_Idle_body
    10391 *

  • cpukit/score/cpu/no_cpu/cpu_asm.c

    r715d616 r511dc4b  
    152152   *  may need to save some special interrupt information for exit
    153153   *
    154    *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
    155    *    if ( _ISR_Nest_level == 0 )
    156    *      switch to software interrupt stack
    157    *  #endif
     154   *  if ( _ISR_Nest_level == 0 )
     155   *    switch to software interrupt stack
    158156   *
    159157   *  _ISR_Nest_level++;
    … …  
    179177   *
    180178   *  LABEL "exit interrupt (simple case):
    181    *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
    182    *    if outermost interrupt
    183    *      restore stack
    184    *  #endif
     179   *  if outermost interrupt
     180   *    restore stack
    185181   *  prepare to get out of interrupt
    186182   *  return from interrupt

  • cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h

    r715d616 r511dc4b  
    4747
    4848/**
    49  * Does RTEMS manage a dedicated interrupt stack in software?
    50  *
    51  * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
    52  * If FALSE, nothing is done.
    53  *
    54  * If the CPU supports a dedicated interrupt stack in hardware,
    55  * then it is generally the responsibility of the BSP to allocate it
    56  * and set it up.
    57  *
    58  * If the CPU does not support a dedicated interrupt stack, then
    59  * the porter has two options: (1) execute interrupts on the
    60  * stack of the interrupted task, and (2) have RTEMS manage a dedicated
    61  * interrupt stack.
    62  *
    63  * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
    64  *
    65  * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
    66  * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
    67  * possible that both are FALSE for a particular CPU.  Although it
    68  * is unclear what that would imply about the interrupt processing
    69  * procedure on that CPU.
    70  *
    71  * Port Specific Information:
    72  *
    73  * XXX document implementation including references if appropriate
    74  */
    75 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
    76 
    77 /**
    7849 * Does the CPU follow the simple vectored interrupt model?
    7950 *
    … …  
    8758 */
    8859#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
    89 
    90 /**
    91  * Does this CPU have hardware support for a dedicated interrupt stack?
    92  *
    93  * If TRUE, then it must be installed during initialization.
    94  * If FALSE, then no installation is performed.
    95  *
    96  * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
    97  *
    98  * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
    99  * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
    100  * possible that both are FALSE for a particular CPU.  Although it
    101  * is unclear what that would imply about the interrupt processing
    102  * procedure on that CPU.
    103  *
    104  * Port Specific Information:
    105  *
    106  * XXX document implementation including references if appropriate
    107  */
    108 #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
    109 
    110 /**
    111  * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
    112  *
    113  * If TRUE, then the memory is allocated during initialization.
    114  * If FALSE, then the memory is allocated during initialization.
    115  *
    116  * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
    117  *
    118  * Port Specific Information:
    119  *
    120  * XXX document implementation including references if appropriate
    121  */
    122 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE
    12360
    12461/**
    … …  
    522459 * @defgroup CPUInterrupt Processor Dependent Interrupt Management
    523460 *
    524  * On some CPUs, RTEMS supports a software managed interrupt stack.
    525  * This stack is allocated by the Interrupt Manager and the switch
    526  * is performed in @ref _ISR_Handler.  These variables contain pointers
    527  * to the lowest and highest addresses in the chunk of memory allocated
    528  * for the interrupt stack.  Since it is unknown whether the stack
    529  * grows up or down (in general), this give the CPU dependent
    530  * code the option of picking the version it wants to use.
    531  *
    532  * NOTE: These two variables are required if the macro
    533  *       @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
     461 * RTEMS supports a software managed interrupt stack.  The interrupt stacks
     462 * are statically allocated by <rtems/confdefs.h> and the switch is performed
     463 * by hardware or the interrupt processing code.  These variables contain
     464 * pointers to the lowest and highest addresses in the chunk of memory
     465 * allocated for the interrupt stack.  Since it is unknown whether the stack
     466 * grows up or down (in general), this give the CPU dependent code the option
     467 * of picking the version it wants to use.
    534468 *
    535469 * Port Specific Information:
    … …  
    11271061
    11281062/**
    1129  * @ingroup CPUInterrupt
    1130  * This routine installs the hardware interrupt stack pointer.
    1131  *
    1132  * NOTE:  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
    1133  *        is TRUE.
    1134  *
    1135  * Port Specific Information:
    1136  *
    1137  * XXX document implementation including references if appropriate
    1138  */
    1139 void _CPU_Install_interrupt_stack( void );
    1140 
    1141 /**
    11421063 * This routine is the CPU dependent IDLE thread body.
    11431064 *

  • cpukit/score/cpu/or1k/cpu.c

    r715d616 r511dc4b  
    106106}
    107107
    108 void _CPU_Install_interrupt_stack( void )
    109 {
    110 }
    111 
    112108void *_CPU_Thread_Idle_body( uintptr_t ignored )
    113109{

  • cpukit/score/cpu/or1k/include/rtems/score/cpu.h

    r715d616 r511dc4b  
    3939
    4040/* conditional compilation parameters */
    41 
    42 /*
    43  *  Does RTEMS manage a dedicated interrupt stack in software?
    44  *
    45  *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
    46  *  If FALSE, nothing is done.
    47  *
    48  *  If the CPU supports a dedicated interrupt stack in hardware,
    49  *  then it is generally the responsibility of the BSP to allocate it
    50  *  and set it up.
    51  *
    52  *  If the CPU does not support a dedicated interrupt stack, then
    53  *  the porter has two options: (1) execute interrupts on the
    54  *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
    55  *  interrupt stack.
    56  *
    57  *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
    58  *
    59  *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
    60  *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
    61  *  possible that both are FALSE for a particular CPU.  Although it
    62  *  is unclear what that would imply about the interrupt processing
    63  *  procedure on that CPU.
    64  *
    65  *  Currently, for or1k port, _ISR_Handler is responsible for switching to
    66  *  RTEMS dedicated interrupt task.
    67  *
    68  */
    69 
    70 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
    71 
    72 /*
    73  *  Does this CPU have hardware support for a dedicated interrupt stack?
    74  *
    75  *  If TRUE, then it must be installed during initialization.
    76  *  If FALSE, then no installation is performed.
    77  *
    78  *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
    79  *
    80  *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
    81  *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
    82  *  possible that both are FALSE for a particular CPU.  Although it
    83  *  is unclear what that would imply about the interrupt processing
    84  *  procedure on that CPU.
    85  *
    86  */
    87 
    88 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
    89 
    90 /*
    91  *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
    92  *
    93  *  If TRUE, then the memory is allocated during initialization.
    94  *  If FALSE, then the memory is allocated during initialization.
    95  *
    96  *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
    97  *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
    98  *
    99  */
    100 
    101 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE
    10241
    10342/*
    … …  
    737676
    738677/*
    739  *  _CPU_Install_interrupt_stack
    740  *
    741  *  This routine installs the hardware interrupt stack pointer.
    742  *
    743  *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
    744  *         is TRUE.
    745  *
    746  */
    747 
    748 void _CPU_Install_interrupt_stack( void );
    749 
    750 /*
    751678 *  _CPU_Thread_Idle_body
    752679 *

  • cpukit/score/cpu/powerpc/include/rtems/score/cpu.h

    r715d616 r511dc4b  
    474474
    475475/*
    476  *  Does RTEMS manage a dedicated interrupt stack in software?
    477  *
    478  *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
    479  *  If FALSE, nothing is done.
    480  *
    481  *  If the CPU supports a dedicated interrupt stack in hardware,
    482  *  then it is generally the responsibility of the BSP to allocate it
    483  *  and set it up.
    484  *
    485  *  If the CPU does not support a dedicated interrupt stack, then
    486  *  the porter has two options: (1) execute interrupts on the
    487  *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
    488  *  interrupt stack.
    489  *
    490  *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
    491  *
    492  *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
    493  *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
    494  *  possible that both are FALSE for a particular CPU.  Although it
    495  *  is unclear what that would imply about the interrupt processing
    496  *  procedure on that CPU.
    497  */
    498 
    499 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
    500 
    501 /*
    502  *  Does this CPU have hardware support for a dedicated interrupt stack?
    503  *
    504  *  If TRUE, then it must be installed during initialization.
    505  *  If FALSE, then no installation is performed.
    506  *
    507  *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
    508  *
    509  *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
    510  *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
    511  *  possible that both are FALSE for a particular CPU.  Although it
    512  *  is unclear what that would imply about the interrupt processing
    513  *  procedure on that CPU.
    514  */
    515 
    516 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
    517 
    518 /*
    519  *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
    520  *
    521  *  If TRUE, then the memory is allocated during initialization.
    522  *  If FALSE, then the memory is allocated during initialization.
    523  *
    524  *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
    525  */
    526 
    527 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE
    528 
    529 /*
    530476 *  Does the RTEMS invoke the user's ISR with the vector number and
    531477 *  a pointer to the saved interrupt frame (1) or just the vector

  • cpukit/score/cpu/riscv/cpu.c

    r715d616 r511dc4b  
    111111}
    112112
    113 void _CPU_Install_interrupt_stack( void )
    114 {
    115   /* Do nothing */
    116 }
    117 
    118113void *_CPU_Thread_Idle_body( uintptr_t ignored )
    119114{

  • cpukit/score/cpu/riscv/include/rtems/score/cpu.h

    r715d616 r511dc4b  
    5151#define CPU_INLINE_ENABLE_DISPATCH       FALSE
    5252#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
    53 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
    54 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
    55 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE
    5653#define CPU_ISR_PASSES_FRAME_POINTER 1
    5754#define CPU_HARDWARE_FP                  FALSE
    … …  
    352349
    353350/*
    354  *  _CPU_Install_interrupt_stack
    355  *
    356  *  This routine installs the hardware interrupt stack pointer.
    357  *
    358  *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
    359  *         is TRUE.
    360  *
    361  */
    362 
    363 void _CPU_Install_interrupt_stack( void );
    364 
    365 /*
    366351 *  _CPU_Thread_Idle_body
    367352 *

  • cpukit/score/cpu/sh/include/rtems/score/cpu.h

    r715d616 r511dc4b  
    4949 */
    5050#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
    51 
    52 /*
    53  *  Does RTEMS manage a dedicated interrupt stack in software?
    54  *
    55  *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
    56  *  If FALSE, nothing is done.
    57  *
    58  *  If the CPU supports a dedicated interrupt stack in hardware,
    59  *  then it is generally the responsibility of the BSP to allocate it
    60  *  and set it up.
    61  *
    62  *  If the CPU does not support a dedicated interrupt stack, then
    63  *  the porter has two options: (1) execute interrupts on the
    64  *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
    65  *  interrupt stack.
    66  *
    67  *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
    68  *
    69  *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
    70  *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
    71  *  possible that both are FALSE for a particular CPU.  Although it
    72  *  is unclear what that would imply about the interrupt processing
    73  *  procedure on that CPU.
    74  */
    75 
    76 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
    77 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
    78 
    79 /*
    80  * We define the interrupt stack in the linker script
    81  */
    82 #define CPU_ALLOCATE_INTERRUPT_STACK FALSE
    8351
    8452/*
    … …  
    642610
    643611/*
    644  *  _CPU_Install_interrupt_stack
    645  *
    646  *  This routine installs the hardware interrupt stack pointer.
    647  *
    648  *  NOTE:  It needs only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
    649  *         is TRUE.
    650  */
    651 
    652 void _CPU_Install_interrupt_stack( void );
    653 
    654 /*
    655612 *  _CPU_Thread_Idle_body
    656613 *

  • cpukit/score/cpu/sparc/include/rtems/score/cpu.h

    r715d616 r511dc4b  
    7070
    7171/**
    72  * Does the executive manage a dedicated interrupt stack in software?
    73  *
    74  * If TRUE, then a stack is allocated in _ISR_Handler_initialization.
    75  * If FALSE, nothing is done.
    76  *
    77  * The SPARC does not have a dedicated HW interrupt stack and one has
    78  * been implemented in SW.
    79  */
    80 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK   TRUE
    81 
    82 /**
    8372 * Does the CPU follow the simple vectored interrupt model?