Changeset 50440c0 in rtems


Ignore:
Timestamp:
Nov 19, 2014, 2:30:24 PM (5 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
3bb9c61c
Parents:
d1eb7b1
git-author:
Sebastian Huber <sebastian.huber@…> (11/19/14 14:30:24)
git-committer:
Sebastian Huber <sebastian.huber@…> (11/20/14 10:36:03)
Message:

bsps/arm: Enable L2C for Cortex-A9 MPCore BSPs

Location:
c/src/lib/libbsp/arm
Files:
2 added
9 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am

    rd1eb7b1 r50440c0  
    175175libbsp_a_SOURCES += startup/mmu-config.c
    176176if HAS_SMP
     177libbsp_a_SOURCES += ../shared/arm-a9mpcore-smp.c
    177178libbsp_a_SOURCES += startup/bspsmp.c
    178179endif
  • c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac

    rd1eb7b1 r50440c0  
    2424RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[])
    2525RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start])
     26
     27RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*],[1])
     28RTEMS_BSPOPTS_HELP([BSP_DATA_CACHE_ENABLED],[enable data cache])
     29
     30RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*],[1])
     31RTEMS_BSPOPTS_HELP([BSP_INSTRUCTION_CACHE_ENABLED],[enable instruction cache])
    2632
    2733RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[altcycv_devkit*],[200000000U])
  • c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspsmp.c

    rd1eb7b1 r50440c0  
    1313 */
    1414
    15 #include <assert.h>
    16 
    1715#include <rtems/score/smpimpl.h>
    1816
    19 #include <libcpu/arm-cp15.h>
    20 
    21 #include <bsp/irq.h>
    22 #include <bsp/linker-symbols.h>
    2317#include <bsp/start.h>
    2418
     
    2721#include <socal/hps.h>
    2822#include <socal/socal.h>
    29 
    30 static void bsp_inter_processor_interrupt(void *arg)
    31 {
    32   _SMP_Inter_processor_interrupt_handler();
    33 }
    34 
    35 uint32_t _CPU_SMP_Initialize(void)
    36 {
    37   uint32_t hardware_count = arm_gic_irq_processor_count();
    38   uint32_t linker_count = (uint32_t) bsp_processor_count;
    39 
    40   return hardware_count <= linker_count ? hardware_count : linker_count;
    41 }
    4223
    4324bool _CPU_SMP_Start_processor(uint32_t cpu_index)
     
    6748  return started;
    6849}
    69 
    70 void _CPU_SMP_Finalize_initialization(uint32_t cpu_count)
    71 {
    72   if (cpu_count > 0) {
    73     rtems_status_code sc;
    74 
    75     sc = rtems_interrupt_handler_install(
    76       ARM_GIC_IRQ_SGI_0,
    77       "IPI",
    78       RTEMS_INTERRUPT_UNIQUE,
    79       bsp_inter_processor_interrupt,
    80       NULL
    81     );
    82     assert(sc == RTEMS_SUCCESSFUL);
    83 
    84     /* Enable unified L2 cache */
    85     rtems_cache_enable_data();
    86   }
    87 }
    88 
    89 void _CPU_SMP_Send_interrupt(uint32_t target_processor_index)
    90 {
    91   arm_gic_irq_generate_software_irq(
    92     ARM_GIC_IRQ_SGI_0,
    93     ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,
    94     (uint8_t) (1U << target_processor_index)
    95   );
    96 }
  • c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am

    rd1eb7b1 r50440c0  
    9898libbsp_a_SOURCES += startup/bspreset.c
    9999libbsp_a_SOURCES += startup/bspstart.c
     100if HAS_SMP
     101libbsp_a_SOURCES += ../shared/arm-a9mpcore-smp.c
     102libbsp_a_SOURCES += startup/bspsmp.c
     103endif
    100104
    101105# IRQ
     
    132136libbsp_a_SOURCES += startup/fb-config.c
    133137
    134 if HAS_SMP
    135 libbsp_a_SOURCES += ../shared/arm-a9mpcore-smp.c
    136 endif
    137 
    138138###############################################################################
    139139#                  Special Rules                                              #
  • c/src/lib/libbsp/arm/realview-pbx-a9/configure.ac

    rd1eb7b1 r50440c0  
    2525RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start])
    2626
     27RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*qemu],[])
     28RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*],[1])
     29RTEMS_BSPOPTS_HELP([BSP_DATA_CACHE_ENABLED],[enable data cache])
     30
     31RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*qemu],[])
     32RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*],[1])
     33RTEMS_BSPOPTS_HELP([BSP_INSTRUCTION_CACHE_ENABLED],[enable instruction cache])
     34
    2735RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[*],[100000000U])
    2836RTEMS_BSPOPTS_HELP([BSP_ARM_A9MPCORE_PERIPHCLK],[ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz])
  • c/src/lib/libbsp/arm/shared/arm-a9mpcore-smp.c

    rd1eb7b1 r50440c0  
    2020
    2121#include <bsp/irq.h>
     22#include <bsp/linker-symbols.h>
    2223
    2324static void bsp_inter_processor_interrupt(void *arg)
     
    2829uint32_t _CPU_SMP_Initialize(void)
    2930{
    30   return arm_gic_irq_processor_count();
    31 }
     31  uint32_t hardware_count = arm_gic_irq_processor_count();
     32  uint32_t linker_count = (uint32_t) bsp_processor_count;
    3233
    33 bool _CPU_SMP_Start_processor(uint32_t cpu_index)
    34 {
    35   (void) cpu_index;
    36 
    37   /* Nothing to do */
    38 
    39   return true;
     34  return hardware_count <= linker_count ? hardware_count : linker_count;
    4035}
    4136
     
    5348    );
    5449    assert(sc == RTEMS_SUCCESSFUL);
     50
     51#if defined(BSP_DATA_CACHE_ENABLED) || defined(BSP_INSTRUCTION_CACHE_ENABLED)
     52    /* Enable unified L2 cache */
     53    rtems_cache_enable_data();
     54#endif
    5555  }
    5656}
  • c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am

    rd1eb7b1 r50440c0  
    9595libbsp_a_SOURCES += startup/bspreset.c
    9696libbsp_a_SOURCES += startup/bspstart.c
     97if HAS_SMP
     98libbsp_a_SOURCES += ../shared/arm-a9mpcore-smp.c
     99libbsp_a_SOURCES += startup/bspsmp.c
     100endif
    97101
    98102# IRQ
     
    123127# Cache
    124128libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
     129libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
    125130libbsp_a_SOURCES += ../shared/arm-l2c-310/cache_.h
    126131libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/arm-l2c-310
     
    128133# Start hooks
    129134libbsp_a_SOURCES += startup/bspstarthooks.c startup/bspstartmmu.c
    130 
    131 if HAS_SMP
    132 libbsp_a_SOURCES += ../shared/arm-a9mpcore-smp.c
    133 endif
    134135
    135136###############################################################################
  • c/src/lib/libbsp/arm/xilinx-zynq/configure.ac

    rd1eb7b1 r50440c0  
    2424RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[])
    2525RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start])
     26
     27RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*qemu],[])
     28RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*],[1])
     29RTEMS_BSPOPTS_HELP([BSP_DATA_CACHE_ENABLED],[enable data cache])
     30
     31RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*qemu],[])
     32RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*],[1])
     33RTEMS_BSPOPTS_HELP([BSP_INSTRUCTION_CACHE_ENABLED],[enable instruction cache])
    2634
    2735RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[xilinx_zynq_zc702*],[333333333U])
  • c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c

    rd1eb7b1 r50440c0  
    11/*
    2  * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
     2 * Copyright (c) 2013-2014 embedded brains GmbH.  All rights reserved.
    33 *
    44 *  embedded brains GmbH
     
    3030  bsp_start_copy_sections();
    3131  zynq_setup_mmu_and_cache();
     32
     33#if !defined(RTEMS_SMP) \
     34  && (defined(BSP_DATA_CACHE_ENABLED) \
     35    || defined(BSP_INSTRUCTION_CACHE_ENABLED))
     36  /* Enable unified L2 cache */
     37  rtems_cache_enable_data();
     38#endif
     39
    3240  bsp_start_clear_bss();
    3341}
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