Changeset 50440c0 in rtems
- Timestamp:
- 11/19/14 14:30:24 (9 years ago)
- Branches:
- 4.11, 5, master
- Children:
- 3bb9c61c
- Parents:
- d1eb7b1
- git-author:
- Sebastian Huber <sebastian.huber@…> (11/19/14 14:30:24)
- git-committer:
- Sebastian Huber <sebastian.huber@…> (11/20/14 10:36:03)
- Location:
- c/src/lib/libbsp/arm
- Files:
-
- 2 added
- 9 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am
rd1eb7b1 r50440c0 175 175 libbsp_a_SOURCES += startup/mmu-config.c 176 176 if HAS_SMP 177 libbsp_a_SOURCES += ../shared/arm-a9mpcore-smp.c 177 178 libbsp_a_SOURCES += startup/bspsmp.c 178 179 endif -
c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac
rd1eb7b1 r50440c0 24 24 RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[]) 25 25 RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start]) 26 27 RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*],[1]) 28 RTEMS_BSPOPTS_HELP([BSP_DATA_CACHE_ENABLED],[enable data cache]) 29 30 RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*],[1]) 31 RTEMS_BSPOPTS_HELP([BSP_INSTRUCTION_CACHE_ENABLED],[enable instruction cache]) 26 32 27 33 RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[altcycv_devkit*],[200000000U]) -
c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspsmp.c
rd1eb7b1 r50440c0 13 13 */ 14 14 15 #include <assert.h>16 17 15 #include <rtems/score/smpimpl.h> 18 16 19 #include <libcpu/arm-cp15.h>20 21 #include <bsp/irq.h>22 #include <bsp/linker-symbols.h>23 17 #include <bsp/start.h> 24 18 … … 27 21 #include <socal/hps.h> 28 22 #include <socal/socal.h> 29 30 static void bsp_inter_processor_interrupt(void *arg)31 {32 _SMP_Inter_processor_interrupt_handler();33 }34 35 uint32_t _CPU_SMP_Initialize(void)36 {37 uint32_t hardware_count = arm_gic_irq_processor_count();38 uint32_t linker_count = (uint32_t) bsp_processor_count;39 40 return hardware_count <= linker_count ? hardware_count : linker_count;41 }42 23 43 24 bool _CPU_SMP_Start_processor(uint32_t cpu_index) … … 67 48 return started; 68 49 } 69 70 void _CPU_SMP_Finalize_initialization(uint32_t cpu_count)71 {72 if (cpu_count > 0) {73 rtems_status_code sc;74 75 sc = rtems_interrupt_handler_install(76 ARM_GIC_IRQ_SGI_0,77 "IPI",78 RTEMS_INTERRUPT_UNIQUE,79 bsp_inter_processor_interrupt,80 NULL81 );82 assert(sc == RTEMS_SUCCESSFUL);83 84 /* Enable unified L2 cache */85 rtems_cache_enable_data();86 }87 }88 89 void _CPU_SMP_Send_interrupt(uint32_t target_processor_index)90 {91 arm_gic_irq_generate_software_irq(92 ARM_GIC_IRQ_SGI_0,93 ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,94 (uint8_t) (1U << target_processor_index)95 );96 } -
c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am
rd1eb7b1 r50440c0 98 98 libbsp_a_SOURCES += startup/bspreset.c 99 99 libbsp_a_SOURCES += startup/bspstart.c 100 if HAS_SMP 101 libbsp_a_SOURCES += ../shared/arm-a9mpcore-smp.c 102 libbsp_a_SOURCES += startup/bspsmp.c 103 endif 100 104 101 105 # IRQ … … 132 136 libbsp_a_SOURCES += startup/fb-config.c 133 137 134 if HAS_SMP135 libbsp_a_SOURCES += ../shared/arm-a9mpcore-smp.c136 endif137 138 138 ############################################################################### 139 139 # Special Rules # -
c/src/lib/libbsp/arm/realview-pbx-a9/configure.ac
rd1eb7b1 r50440c0 25 25 RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start]) 26 26 27 RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*qemu],[]) 28 RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*],[1]) 29 RTEMS_BSPOPTS_HELP([BSP_DATA_CACHE_ENABLED],[enable data cache]) 30 31 RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*qemu],[]) 32 RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*],[1]) 33 RTEMS_BSPOPTS_HELP([BSP_INSTRUCTION_CACHE_ENABLED],[enable instruction cache]) 34 27 35 RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[*],[100000000U]) 28 36 RTEMS_BSPOPTS_HELP([BSP_ARM_A9MPCORE_PERIPHCLK],[ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz]) -
c/src/lib/libbsp/arm/shared/arm-a9mpcore-smp.c
rd1eb7b1 r50440c0 20 20 21 21 #include <bsp/irq.h> 22 #include <bsp/linker-symbols.h> 22 23 23 24 static void bsp_inter_processor_interrupt(void *arg) … … 28 29 uint32_t _CPU_SMP_Initialize(void) 29 30 { 30 returnarm_gic_irq_processor_count();31 } 31 uint32_t hardware_count = arm_gic_irq_processor_count(); 32 uint32_t linker_count = (uint32_t) bsp_processor_count; 32 33 33 bool _CPU_SMP_Start_processor(uint32_t cpu_index) 34 { 35 (void) cpu_index; 36 37 /* Nothing to do */ 38 39 return true; 34 return hardware_count <= linker_count ? hardware_count : linker_count; 40 35 } 41 36 … … 53 48 ); 54 49 assert(sc == RTEMS_SUCCESSFUL); 50 51 #if defined(BSP_DATA_CACHE_ENABLED) || defined(BSP_INSTRUCTION_CACHE_ENABLED) 52 /* Enable unified L2 cache */ 53 rtems_cache_enable_data(); 54 #endif 55 55 } 56 56 } -
c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am
rd1eb7b1 r50440c0 95 95 libbsp_a_SOURCES += startup/bspreset.c 96 96 libbsp_a_SOURCES += startup/bspstart.c 97 if HAS_SMP 98 libbsp_a_SOURCES += ../shared/arm-a9mpcore-smp.c 99 libbsp_a_SOURCES += startup/bspsmp.c 100 endif 97 101 98 102 # IRQ … … 123 127 # Cache 124 128 libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c 129 libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h 125 130 libbsp_a_SOURCES += ../shared/arm-l2c-310/cache_.h 126 131 libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/arm-l2c-310 … … 128 133 # Start hooks 129 134 libbsp_a_SOURCES += startup/bspstarthooks.c startup/bspstartmmu.c 130 131 if HAS_SMP132 libbsp_a_SOURCES += ../shared/arm-a9mpcore-smp.c133 endif134 135 135 136 ############################################################################### -
c/src/lib/libbsp/arm/xilinx-zynq/configure.ac
rd1eb7b1 r50440c0 24 24 RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[]) 25 25 RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start]) 26 27 RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*qemu],[]) 28 RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*],[1]) 29 RTEMS_BSPOPTS_HELP([BSP_DATA_CACHE_ENABLED],[enable data cache]) 30 31 RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*qemu],[]) 32 RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*],[1]) 33 RTEMS_BSPOPTS_HELP([BSP_INSTRUCTION_CACHE_ENABLED],[enable instruction cache]) 26 34 27 35 RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[xilinx_zynq_zc702*],[333333333U]) -
c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c
rd1eb7b1 r50440c0 1 1 /* 2 * Copyright (c) 2013 embedded brains GmbH. All rights reserved.2 * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. 3 3 * 4 4 * embedded brains GmbH … … 30 30 bsp_start_copy_sections(); 31 31 zynq_setup_mmu_and_cache(); 32 33 #if !defined(RTEMS_SMP) \ 34 && (defined(BSP_DATA_CACHE_ENABLED) \ 35 || defined(BSP_INSTRUCTION_CACHE_ENABLED)) 36 /* Enable unified L2 cache */ 37 rtems_cache_enable_data(); 38 #endif 39 32 40 bsp_start_clear_bss(); 33 41 }
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