Index: bsps/mips/shared/irq/exception.S
===================================================================
--- bsps/mips/shared/irq/exception.S	(revision ff081aee72436131cf11e3a35f96a6405c3a4d78)
+++ bsps/mips/shared/irq/exception.S	(revision 4fea054ca575418a4190f0b7876c206382ccfd05)
@@ -373,5 +373,5 @@
   /*
    *  prepare to get out of interrupt
-   *  return from interrupt  (maybe to _ISR_Dispatch)
+   *  return from interrupt
    *
    *  LABEL "exit interrupt (simple case):"
Index: cpukit/Makefile.am
===================================================================
--- cpukit/Makefile.am	(revision ff081aee72436131cf11e3a35f96a6405c3a4d78)
+++ cpukit/Makefile.am	(revision 4fea054ca575418a4190f0b7876c206382ccfd05)
@@ -1600,5 +1600,4 @@
 librtemscpu_a_SOURCES += score/cpu/m32c/context_init.c
 librtemscpu_a_SOURCES += score/cpu/m32c/context_switch.S
-librtemscpu_a_SOURCES += score/cpu/m32c/cpu_asm.c
 librtemscpu_a_SOURCES += score/cpu/m32c/cpu.c
 librtemscpu_a_SOURCES += score/cpu/m32c/m32c-exception-frame-print.c
Index: cpukit/include/rtems/score/isr.h
===================================================================
--- cpukit/include/rtems/score/isr.h	(revision ff081aee72436131cf11e3a35f96a6405c3a4d78)
+++ cpukit/include/rtems/score/isr.h	(revision 4fea054ca575418a4190f0b7876c206382ccfd05)
@@ -147,19 +147,4 @@
 
 /**
- *  @brief ISR wrapper for thread dispatcher.
- *
- *  This routine provides a wrapper so that the routine
- *  @ref _Thread_Dispatch can be invoked when a reschedule is necessary
- *  at the end of the outermost interrupt service routine.  This
- *  wrapper is necessary to establish the processor context needed
- *  by _Thread_Dispatch and to save the processor context which is
- *  corrupted by _Thread_Dispatch.  This context typically consists
- *  of registers which are not preserved across routine invocations.
- *
- *  @note  Typically mplemented in assembly language.
- */
-void _ISR_Dispatch( void );
-
-/**
  *  @brief Checks if an ISR in progress.
  *
Index: ukit/score/cpu/m32c/cpu_asm.c
===================================================================
--- cpukit/score/cpu/m32c/cpu_asm.c	(revision ff081aee72436131cf11e3a35f96a6405c3a4d78)
+++ 	(revision )
@@ -1,106 +1,0 @@
-/**
- *  @file
- *
- *  @brief M32C CPU Assembly File
- */
-
-/*  cpu_asm.c  ===> cpu_asm.S or cpu_asm.s
- *
- *  This file contains the basic algorithms for all assembly code used
- *  in an specific CPU port of RTEMS.  These algorithms must be implemented
- *  in assembly language
- *
- *  NOTE:  This is supposed to be a .S or .s file NOT a C file.
- *
- *  M32C does not yet have interrupt support.  When this functionality
- *  is written, this file should become obsolete.
- *
- *  COPYRIGHT (c) 1989-2008.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-/*
- *  This is supposed to be an assembly file.  This means that system.h
- *  and cpu.h should not be included in a "real" cpu_asm file.  An
- *  implementation in assembly should include "cpu_asm.h>
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <rtems/system.h>
-#include <rtems/score/cpu.h>
-
-void _ISR_Handler(void);
-
-/*  void __ISR_Handler()
- *
- *  This routine provides the RTEMS interrupt management.
- *
- *  M32C Specific Information:
- *
- *  Interrupts are not currently supported.
- */
-void _ISR_Handler(void)
-{
-   /*
-    *  This discussion ignores a lot of the ugly details in a real
-    *  implementation such as saving enough registers/state to be
-    *  able to do something real.  Keep in mind that the goal is
-    *  to invoke a user's ISR handler which is written in C and
-    *  uses a certain set of registers.
-    *
-    *  Also note that the exact order is to a large extent flexible.
-    *  Hardware will dictate a sequence for a certain subset of
-    *  _ISR_Handler while requirements for setting
-    */
-
-  /*
-   *  At entry to "common" _ISR_Handler, the vector number must be
-   *  available.  On some CPUs the hardware puts either the vector
-   *  number or the offset into the vector table for this ISR in a
-   *  known place.  If the hardware does not give us this information,
-   *  then the assembly portion of RTEMS for this port will contain
-   *  a set of distinct interrupt entry points which somehow place
-   *  the vector number in a known place (which is safe if another
-   *  interrupt nests this one) and branches to _ISR_Handler.
-   *
-   *  save some or all context on stack
-   *  may need to save some special interrupt information for exit
-   *
-   *  if ( _ISR_Nest_level == 0 )
-   *    switch to software interrupt stack
-   *
-   *  _ISR_Nest_level++;
-   *
-   *  _Thread_Dispatch_disable_level++;
-   *
-   *  (*_ISR_Vector_table[ vector ])( vector );
-   *
-   *  _Thread_Dispatch_disable_level--;
-   *
-   *  --_ISR_Nest_level;
-   *
-   *  if ( _ISR_Nest_level )
-   *    goto the label "exit interrupt (simple case)"
-   *
-   *  if ( _Thread_Dispatch_disable_level )
-   *    goto the label "exit interrupt (simple case)"
-   *
-   *  if ( _Thread_Dispatch_necessary ) {
-   *    call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
-   *    prepare to get out of interrupt
-   *    return from interrupt  (maybe to _ISR_Dispatch)
-   *
-   *  LABEL "exit interrupt (simple case):
-   *  if outermost interrupt
-   *    restore stack
-   *  prepare to get out of interrupt
-   *  return from interrupt
-   */
-}
Index: cpukit/score/cpu/m68k/cpu_asm.S
===================================================================
--- cpukit/score/cpu/m68k/cpu_asm.S	(revision ff081aee72436131cf11e3a35f96a6405c3a4d78)
+++ cpukit/score/cpu/m68k/cpu_asm.S	(revision 4fea054ca575418a4190f0b7876c206382ccfd05)
@@ -325,5 +325,5 @@
         movec   msp,a0                   | a0 = master stack pointer
         movew   #0,a0@-                  | push format word
-        movel   #SYM(_ISR_Dispatch),a0@- | push return addr
+        movel   #thread_dispatch,a0@-    | push return addr
         movew   a0@(6),a0@-              | push saved sr
         movec   a0,msp                   | set master stack pointer
@@ -345,6 +345,6 @@
                                          |   OR _Isr_dispatch
 
-/*void _ISR_Dispatch()
- *
+#if ( M68K_HAS_SEPARATE_STACKS == 1 )
+/*
  *  Entry point from the outermost interrupt service routine exit.
  *  The current stack is the supervisor mode stack if this processor
@@ -358,6 +358,5 @@
  */
 
-        .global SYM (_ISR_Dispatch)
-SYM (_ISR_Dispatch):
+thread_dispatch:
 #if ( !defined(__mcoldfire__) )
         movml   d0-d1/a0-a1,a7@-
@@ -376,2 +375,3 @@
 #endif /* M68K_HAS_VBR */
         rte
+#endif /* M68K_HAS_SEPARATE_STACKS */
Index: cpukit/score/cpu/mips/cpu_asm.S
===================================================================
--- cpukit/score/cpu/mips/cpu_asm.S	(revision ff081aee72436131cf11e3a35f96a6405c3a4d78)
+++ cpukit/score/cpu/mips/cpu_asm.S	(revision 4fea054ca575418a4190f0b7876c206382ccfd05)
@@ -1050,5 +1050,5 @@
   /*
    *  prepare to get out of interrupt
-   *  return from interrupt  (maybe to _ISR_Dispatch)
+   *  return from interrupt
    *
    *  LABEL "exit interrupt (simple case):"
Index: cpukit/score/cpu/moxie/cpu_asm.S
===================================================================
--- cpukit/score/cpu/moxie/cpu_asm.S	(revision ff081aee72436131cf11e3a35f96a6405c3a4d78)
+++ cpukit/score/cpu/moxie/cpu_asm.S	(revision 4fea054ca575418a4190f0b7876c206382ccfd05)
@@ -88,19 +88,4 @@
 
 
-/*
-        Called from ISR_Handler as a way of ending IRQ
-        but allowing dispatch to another task.
-        Must use RTE as CCR is still on stack but IRQ has been serviced.
-        CCR and PC occupy same word so rte can be used.
-        now using task stack
-*/
-
-        .align 2
-        .global SYM(_ISR_Dispatch)
-
-SYM(_ISR_Dispatch):
-        brk
-
-
         .align 2
         .global SYM(_CPU_Context_save_fp)
Index: cpukit/score/cpu/no_cpu/cpu_asm.c
===================================================================
--- cpukit/score/cpu/no_cpu/cpu_asm.c	(revision ff081aee72436131cf11e3a35f96a6405c3a4d78)
+++ cpukit/score/cpu/no_cpu/cpu_asm.c	(revision 4fea054ca575418a4190f0b7876c206382ccfd05)
@@ -172,7 +172,7 @@
    *
    *  if ( _Thread_Dispatch_necessary ) {
-   *    call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
+   *    call _Thread_Dispatch() or prepare to return from interrupt
    *    prepare to get out of interrupt
-   *    return from interrupt  (maybe to _ISR_Dispatch)
+   *    return from interrupt
    *
    *  LABEL "exit interrupt (simple case):
Index: cpukit/score/cpu/sparc/cpu.c
===================================================================
--- cpukit/score/cpu/sparc/cpu.c	(revision ff081aee72436131cf11e3a35f96a6405c3a4d78)
+++ cpukit/score/cpu/sparc/cpu.c	(revision 4fea054ca575418a4190f0b7876c206382ccfd05)
@@ -413,7 +413,7 @@
   /*
    *  Since THIS thread is being created, there is no way that THIS
-   *  thread can have an _ISR_Dispatch stack frame on its stack.
-   */
-    the_context->isr_dispatch_disable = 0;
+   *  thread can have an interrupt stack frame on its stack.
+   */
+  the_context->isr_dispatch_disable = 0;
 
   if ( tls_area != NULL ) {
Index: cpukit/score/cpu/sparc64/cpu.c
===================================================================
--- cpukit/score/cpu/sparc64/cpu.c	(revision ff081aee72436131cf11e3a35f96a6405c3a4d78)
+++ cpukit/score/cpu/sparc64/cpu.c	(revision 4fea054ca575418a4190f0b7876c206382ccfd05)
@@ -61,5 +61,5 @@
    *  Since no tasks have been created yet and no interrupts have occurred,
    *  there is no way that the currently executing thread can have an
-   *  _ISR_Dispatch stack frame on its stack.
+   *  interrupt stack frame on its stack.
    */
   _CPU_ISR_Dispatch_disable = 0;
@@ -101,5 +101,5 @@
   /*
    *  Since THIS thread is being created, there is no way that THIS
-   *  thread can have an _ISR_Dispatch stack frame on its stack.
+   *  thread can have an interrupt stack frame on its stack.
    */
     the_context->isr_dispatch_disable = 0;
Index: cpukit/score/cpu/sparc64/include/rtems/score/cpu.h
===================================================================
--- cpukit/score/cpu/sparc64/include/rtems/score/cpu.h	(revision ff081aee72436131cf11e3a35f96a6405c3a4d78)
+++ cpukit/score/cpu/sparc64/include/rtems/score/cpu.h	(revision 4fea054ca575418a4190f0b7876c206382ccfd05)
@@ -488,5 +488,5 @@
 /*
  *  This flag is context switched with each thread.  It indicates
- *  that THIS thread has an _ISR_Dispatch stack frame on its stack.
+ *  that THIS thread has an interrupt stack frame on its stack.
  *  By using this flag, we can avoid nesting more interrupt dispatching
  *  attempts on a previously interrupted thread's stack.
Index: cpukit/score/cpu/sparc64/interrupt.S
===================================================================
--- cpukit/score/cpu/sparc64/interrupt.S	(revision ff081aee72436131cf11e3a35f96a6405c3a4d78)
+++ cpukit/score/cpu/sparc64/interrupt.S	(revision 4fea054ca575418a4190f0b7876c206382ccfd05)
@@ -351,6 +351,5 @@
      *  Invoke interrupt dispatcher.
      */
-PUBLIC(_ISR_Dispatch)
-  SYM(_ISR_Dispatch):
+
     ! Set ISR dispatch nesting prevention flag
       mov      1, %o1
