Changeset 4f0b287 in rtems for cpukit/score


Ignore:
Timestamp:
Jul 17, 2002, 5:14:31 PM (18 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
18e45af
Parents:
74c402a2
Message:

2002-07-17 Jay Monkman <jtm@…>

  • rtems/score/cpu_asm.h: Enhanced to include register offsets.
  • Makefile.am: Install rtems/score/cpu_asm.h.
  • cpu.c: Significantly enhanced including the implementation of _CPU_ISR_Get_level.
  • cpu_asm.S: Improved behavior of context switch and interrupt dispatching.
  • rtems/score/arm.h: Improved the CPU model name determination.
  • rtems/score/cpu.h: Improved interrupt disable/enable functions.
Location:
cpukit/score/cpu/arm
Files:
7 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/arm/ChangeLog

    r74c402a2 r4f0b287  
     12002-07-17      Jay Monkman <jtm@smoothsmoothie.com>
     2
     3        * rtems/score/cpu_asm.h: Enhanced to include register offsets.
     4        * Makefile.am: Install rtems/score/cpu_asm.h.
     5        * cpu.c: Significantly enhanced including the implementation of
     6        _CPU_ISR_Get_level.
     7        * cpu_asm.S: Improved behavior of context switch and interrupt
     8        dispatching.
     9        * rtems/score/arm.h: Improved the CPU model name determination.
     10        * rtems/score/cpu.h: Improved interrupt disable/enable functions.
     11
    1122002-07-05      Joel Sherrill <joel@OARcorp.com>
    213
  • cpukit/score/cpu/arm/Makefile.am

    r74c402a2 r4f0b287  
    2727include_rtems_score_HEADERS = \
    2828    rtems/score/cpu.h \
     29    rtems/score/cpu_asm.h \
    2930    rtems/score/arm.h  \
    3031    rtems/score/types.h
  • cpukit/score/cpu/arm/cpu.c

    r74c402a2 r4f0b287  
    55 *  COPYRIGHT (c) 2000 Canon Research Centre France SA.
    66 *  Emmanuel Raguet, mailto:raguet@crf.canon.fr
     7 *
     8 *  Copyright (c) 2002 Advent Networks, Inc
     9 *      Jay Monkman <jmonkman@adventnetworks.com>
    710 *
    811 *  The license and distribution terms for this file may be
     
    2629 *  INPUT PARAMETERS:
    2730 *    cpu_table       - CPU table to initialize
    28  *    thread_dispatch - address of disptaching routine
    29  */
    30 
     31 *    thread_dispatch - address of ISR disptaching routine (unused)
     32 *   
     33 */
    3134
    3235void _CPU_Initialize(
     
    3538)
    3639{
    37   _CPU_Table = *cpu_table;
    38 }
    39 
    40 /*PAGE
    41  *
    42  *  _CPU_ISR_Get_level
     40    _CPU_Table = *cpu_table;
     41}
     42
     43/*
     44 *
     45 *  _CPU_ISR_Get_level - returns the current interrupt level
    4346 */
    4447 
    4548unsigned32 _CPU_ISR_Get_level( void )
    4649{
    47   /*
    48    *  This routine returns the current interrupt level.
    49    */
    50 
    51   return 0;
     50    unsigned32 reg;
     51   
     52    asm volatile ("mrs  %0, cpsr \n"           \
     53                  "and  %0,  %0, #0xc0 \n"     \
     54                  : "=r" (reg));
     55   
     56    return reg;
    5257}
    5358
     
    6065 *  Input parameters:
    6166 *    vector      - interrupt vector number
    62  *    old_handler - former ISR for this vector number
    6367 *    new_handler - replacement ISR for this vector number
     68 *    old_handler - pointer to store former ISR for this vector number
     69 *
     70 *  FIXME: This vector scheme should be changed to allow FIQ to be
     71 *         handled better. I'd like to be able to put VectorTable
     72 *         elsewhere - JTM
     73 *
    6474 *
    6575 *  Output parameters:  NONE
    6676 *
    6777 */
    68 
    6978void _CPU_ISR_install_vector(
    7079  unsigned32  vector,
     
    7382)
    7483{
    75   /* pointer on the redirection table in RAM */
    76   long *VectorTable = (long *)(MAX_EXCEPTIONS * 4);
    77 
    78   if (old_handler != NULL)
    79     old_handler = *(proc_ptr *)(VectorTable + vector);
    80   *(VectorTable + vector) = (long)new_handler ;
     84    /* pointer on the redirection table in RAM */
     85    long *VectorTable = (long *)(MAX_EXCEPTIONS * 4);
     86   
     87    if (old_handler != NULL) {
     88        old_handler = *(proc_ptr *)(VectorTable + vector);
     89    }
     90
     91    *(VectorTable + vector) = (long)new_handler ;
    8192 
    8293}
    8394
     95void _CPU_Context_Initialize(
     96  Context_Control  *the_context,
     97  unsigned32       *stack_base,
     98  unsigned32        size,
     99  unsigned32        new_level,
     100  void             *entry_point,
     101  boolean           is_fp
     102)
     103{
     104    the_context->register_sp = ((unsigned32)(stack_base)) + (size) ;
     105    the_context->register_pc = (entry_point);
     106    the_context->register_cpsr = (new_level | 0x13);
     107}
     108
    84109/*PAGE
    85110 *
     
    89114void _CPU_Install_interrupt_stack( void )
    90115{
     116/* FIXME: do something here */
     117#if 0
     118    extern unsigned long _fiq_stack;
     119    extern unsigned long _fiq_stack_size;
     120    extern unsigned long _irq_stack;
     121    extern unsigned long _irq_stack_size;
     122    extern unsigned long _abt_stack;
     123    extern unsigned long _abt_stack_size;
     124    unsigned long *ptr;
     125    int i;
     126
     127    ptr = &_fiq_stack;
     128    for (i = 0; i < ((int)&_fiq_stack_size/4); i++) {
     129        ptr[i] = 0x13131313;
     130    }
     131
     132    ptr = &_irq_stack;
     133    for (i = 0; i < ((int)&_irq_stack_size/4); i++) {
     134        ptr[i] = 0xf0f0f0f0;
     135    }
     136
     137    ptr = &_abt_stack;
     138    for (i = 0; i < ((int)&_abt_stack_size/4); i++) {
     139        ptr[i] = 0x55555555;
     140    }
     141#endif
    91142}
    92143
     
    111162{
    112163
    113   while(1);
     164    while(1); /* FIXME: finish this */
    114165    /* insert your "halt" instruction here */ ;
    115166}
     
    117168void _defaultExcHandler (CPU_Exception_frame *ctx)
    118169{
    119   printk("----------------------------------------------------------\n");
    120   printk("Exception %d caught at PC %x by thread %d\n",
    121          ctx->register_pc, ctx->register_lr - 4,
    122          _Thread_Executing->Object.id);
    123   printk("----------------------------------------------------------\n");
    124   printk("Processor execution context at time of the fault was  :\n");
    125   printk("----------------------------------------------------------\n");
    126   printk(" r0 = %x     r1 = %x     r2 = %x     r3 = %x\n",
    127          ctx->register_r0, ctx->register_r1, ctx->register_r2, ctx->register_r3);
    128   printk(" r4 = %x     r5 = %x     r6 = %x     r7 = %x\n",
    129          ctx->register_r4, ctx->register_r5, ctx->register_r6, ctx->register_r7);
    130   printk(" r8 = %x     r9 = %x     r10 = %x\n",
    131          ctx->register_r8, ctx->register_r9, ctx->register_r10);
    132   printk(" fp = %x     ip = %x     sp = %x     pc = %x\n",
    133          ctx->register_fp, ctx->register_ip, ctx->register_sp, ctx->register_lr - 4);
    134   printk("----------------------------------------------------------\n");
    135 
    136  if (_ISR_Nest_level > 0) {
    137     /*
    138      * In this case we shall not delete the task interrupted as
    139      * it has nothing to do with the fault. We cannot return either
    140      * because the eip points to the faulty instruction so...
    141      */
    142     printk("Exception while executing ISR!!!. System locked\n");
    143     while(1);
    144   }
    145  else {
    146    printk(" ************ FAULTY THREAD WILL BE DELETED **************\n");
    147    rtems_task_delete(_Thread_Executing->Object.id);
    148  }
     170    printk("\n\r");
     171    printk("----------------------------------------------------------\n\r");
     172    printk("Exception 0x%x caught at PC 0x%x by thread %d\n",
     173           ctx->register_pc, ctx->register_lr - 4,
     174           _Thread_Executing->Object.id);
     175    printk("----------------------------------------------------------\n\r");
     176    printk("Processor execution context at time of the fault was  :\n\r");
     177    printk("----------------------------------------------------------\n\r");
     178    printk(" r0  = %8x  r1  = %8x  r2  = %8x  r3  = %8x\n\r",
     179           ctx->register_r0, ctx->register_r1,
     180           ctx->register_r2, ctx->register_r3);
     181    printk(" r4  = %8x  r5  = %8x  r6  = %8x  r7  = %8x\n\r",
     182           ctx->register_r4, ctx->register_r5,
     183           ctx->register_r6, ctx->register_r7);
     184    printk(" r8  = %8x  r9  = %8x  r10 = %8x\n\r",
     185           ctx->register_r8, ctx->register_r9, ctx->register_r10);
     186    printk(" fp  = %8x  ip  = %8x  sp  = %8x  pc  = %8x\n\r",
     187           ctx->register_fp, ctx->register_ip,
     188           ctx->register_sp, ctx->register_lr - 4);
     189    printk("----------------------------------------------------------\n\r");
     190   
     191    if (_ISR_Nest_level > 0) {
     192        /*
     193         * In this case we shall not delete the task interrupted as
     194         * it has nothing to do with the fault. We cannot return either
     195         * because the eip points to the faulty instruction so...
     196         */
     197        printk("Exception while executing ISR!!!. System locked\n\r");
     198        while(1);
     199    }
     200    else {
     201        printk("*********** FAULTY THREAD WILL BE DELETED **************\n\r");
     202        rtems_task_delete(_Thread_Executing->Object.id);
     203    }
    149204}
    150205
     
    153208extern void _Exception_Handler_Undef_Swi();
    154209extern void _Exception_Handler_Abort();
    155 
     210/* FIXME: put comments here */
    156211void rtems_exception_init_mngt()
    157212{
    158         ISR_Level level;
     213        ISR_Level level;
    159214     
    160215      _CPU_ISR_Disable(level);
    161       _CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF,      _Exception_Handler_Undef_Swi, NULL);
    162       _CPU_ISR_install_vector(ARM_EXCEPTION_SWI,        _Exception_Handler_Undef_Swi, NULL);
    163       _CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT, _Exception_Handler_Abort    , NULL);
    164       _CPU_ISR_install_vector(ARM_EXCEPTION_DATA_ABORT, _Exception_Handler_Abort    , NULL);
    165       _CPU_ISR_install_vector(ARM_EXCEPTION_FIQ,        _Exception_Handler_Abort    , NULL);
    166       _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ,        _Exception_Handler_Abort    , NULL);
     216      _CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF,
     217                              _Exception_Handler_Undef_Swi,
     218                              NULL);
     219 
     220      _CPU_ISR_install_vector(ARM_EXCEPTION_SWI,
     221                              _Exception_Handler_Undef_Swi,
     222                              NULL);
     223     
     224      _CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT,
     225                              _Exception_Handler_Abort,
     226                              NULL);
     227     
     228      _CPU_ISR_install_vector(ARM_EXCEPTION_DATA_ABORT,
     229                              _Exception_Handler_Abort,
     230                              NULL);
     231     
     232      _CPU_ISR_install_vector(ARM_EXCEPTION_FIQ,       
     233                              _Exception_Handler_Abort,
     234                              NULL);
     235     
     236      _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ,
     237                              _Exception_Handler_Abort,
     238                              NULL);
     239     
    167240      _CPU_ISR_Enable(level);
    168241}
  • cpukit/score/cpu/arm/cpu_asm.S

    r74c402a2 r4f0b287  
    1 /*  cpu_asm.s
     1/*
     2 *  $Id$
    23 *
    34 *  This file contains all assembly code for the ARM implementation
    45 *  of RTEMS.
     6 *
     7 *  Copyright (c) 2002 by Advent Networks, Inc.
     8 *          Jay Monkman <jmonkman@adventnetworks.com>
    59 *
    610 *  COPYRIGHT (c) 2000 Canon Research Centre France SA.
     
    1418
    1519#include <asm.h>
    16 
    17 /*
    18  * Format of ARM Register structure
    19  */
    20 
    21 .set REG_R0,  0
    22 .set REG_R1,  4
    23 .set REG_R2,  8
    24 .set REG_R3,  12
    25 .set REG_R4,  16
    26 .set REG_R5,  20
    27 .set REG_R6,  24
    28 .set REG_R7,  28
    29 .set REG_R8,  32
    30 .set REG_R9,  36
    31 .set REG_R10, 40
    32 .set REG_FP,  44
    33 .set REG_IP,  48
    34 .set REG_SP,  52
    35 .set REG_LR,  56
    36 .set REG_PC,  60
    37 .set SIZE_REGS,   REG_PC + 4
     20#include <rtems/score/cpu_asm.h>
     21
    3822
    3923/*
    4024 *  void _CPU_Context_switch( run_context, heir_context )
     25 *  void _CPU_Context_restore( run_context, heir_context )
    4126 *
    4227 *  This routine performs a normal non-FP context.
    4328 *
    44  * R0 = run_context    R1 = heir_context
    45  *     
     29 *  R0 = run_context    R1 = heir_context
     30 *
     31 *  This function copies the current registers to where r0 points, then
     32 *  restores the ones from where r1 points.
     33 *
     34 *
     35 *  NOTE:  The function should be able to only save/restore the registers
     36 *         that would be saved by a C function since the others have already
     37 *         been saved.
     38 *       
     39 *         It should also be able to use the stm/ldm instructions.
     40 *       
    4641 */
    4742
    4843        .globl _CPU_Context_switch
    49 
    5044_CPU_Context_switch:
     45/* FIXME: This should use load and store multiple instructions */
     46/* Start saving context */
    5147        str     r2,  [r0, #REG_R2]
    5248        str     r3,  [r0, #REG_R3]
     
    5854        str     r9,  [r0, #REG_R9]
    5955        str     r10, [r0, #REG_R10]
     56       
     57        str     r11, [r0, #REG_R11]
     58        str     r12, [r0, #REG_R12]     
     59       
    6060        str     sp,  [r0, #REG_SP]
    61         str     lr,  [r0, #REG_PC]
    62        
     61        str     lr,  [r0, #REG_PC]     /* save LR at PC's location */
     62       
     63        mrs     r2, cpsr
     64        str     r2,  [r0, #REG_CPSR]
     65
     66/* Start restoring context */
     67       
     68        ldr     r2,  [r1, #REG_CPSR]
     69        msr     cpsr, r2
     70
    6371        ldr     r2,  [r1, #REG_R2]
    6472        ldr     r3,  [r1, #REG_R3]
     
    6977        ldr     r8,  [r1, #REG_R8]
    7078        ldr     r9,  [r1, #REG_R9]
    71         ldr     r10, [r1, #REG_R10]
     79        ldr     r10, [r1, #REG_R10]     
     80        ldr     r11, [r1, #REG_R11]
     81        ldr     r12, [r1, #REG_R12]     
     82       
    7283        ldr     sp,  [r1, #REG_SP]
    73         ldr     lr,  [r1, #REG_PC]
     84        ldr     lr,  [r1, #REG_PC]     
    7485        mov     pc, lr
    75 
    76 /*
    77  *  NOTE: May be unnecessary to reload some registers.
    78  */
    7986
    8087/*
    8188 *  void _CPU_Context_restore( new_context )
    8289 *
    83  *  This routine performs a normal non-FP context.
     90 *  This function copies the restores the registers from where r0 points.
     91 *  It must match _CPU_Context_switch()
     92 *
     93 *  NOTE:  The function should be able to only save/restore the registers
     94 *         that would be saved by a C function since the others have already
     95 *         been saved.
     96 *       
     97 *         It should also be able to use the stm/ldm instructions.
     98 *       
    8499 */
    85100        .globl _CPU_Context_restore
    86 
    87101_CPU_Context_restore:
    88 
    89         ldr     r2,  [r0, #REG_R2]
     102/* FIXME: This should use load and store multiple instructions */
     103        ldr     r2,  [r0, #REG_CPSR]
     104        msr     cpsr, r2
     105
     106        ldr     r2,  [r0, #REG_R2]     
    90107        ldr     r3,  [r0, #REG_R3]
    91108        ldr     r4,  [r0, #REG_R4]
     
    95112        ldr     r8,  [r0, #REG_R8]
    96113        ldr     r9,  [r0, #REG_R9]
    97         ldr     r10, [r0, #REG_R10]
     114        ldr     r10, [r0, #REG_R10]     
     115        ldr     r11, [r1, #REG_R11]
     116        ldr     r12, [r1, #REG_R12]     
     117                       
    98118        ldr     sp,  [r0, #REG_SP]
    99119        ldr     lr,  [r0, #REG_PC]
     
    101121
    102122
     123/* FIXME:       _Exception_Handler_Undef_Swi is untested */
    103124        .globl _Exception_Handler_Undef_Swi
    104125_Exception_Handler_Undef_Swi:
     126/* FIXME: This should use load and store multiple instructions */
    105127        sub     r13,r13,#SIZE_REGS
    106128        str     r0,  [r13, #REG_R0]
     
    115137        str     r9,  [r13, #REG_R9]
    116138        str     r10, [r13, #REG_R10]
    117         str     fp,  [r13, #REG_FP]
    118         str     ip,  [r13, #REG_IP]
     139        str     r11, [r13, #REG_R11]
     140        str     r12, [r13, #REG_R12]
    119141        str     sp,  [r13, #REG_SP]
    120142        str     lr,  [r13, #REG_LR]
     
    124146        mov     r0,  r13                /* put frame address in r0 (C arg 1) */
    125147
    126         ldr     r1, =_currentExcHandler
     148        ldr     r1, =SWI_Handler
    127149        ldr     lr, =_go_back_1
    128150        ldr     pc,[r1]                         /* call handler  */
     
    139161        ldr     r9,  [r13, #REG_R9]
    140162        ldr     r10, [r13, #REG_R10]
    141         ldr     fp,  [r13, #REG_FP]
    142         ldr     ip,  [r13, #REG_IP]
     163        ldr     r11, [r13, #REG_R11]
     164        ldr     r12, [r13, #REG_R12]
    143165        ldr     sp,  [r13, #REG_SP]
    144166        ldr     lr,  [r13, #REG_LR]
    145167        add     r13,r13,#SIZE_REGS
    146         movs    pc,r14                          /* return  */
    147 
     168        movs    pc,r14                  /* return  */
     169       
     170/* FIXME:       _Exception_Handler_Abort is untested */
    148171        .globl _Exception_Handler_Abort
    149172_Exception_Handler_Abort:
     173/* FIXME: This should use load and store multiple instructions */
    150174        sub     r13,r13,#SIZE_REGS
    151175        str     r0,  [r13, #REG_R0]
     
    160184        str     r9,  [r13, #REG_R9]
    161185        str     r10, [r13, #REG_R10]
    162         str     sp,  [r13, #REG_FP]
    163         str     lr,  [r13, #REG_IP]
     186        str     sp,  [r13, #REG_R11]
     187        str     lr,  [r13, #REG_R12]
    164188        str     lr,  [r13, #REG_SP]
    165189        str     lr,  [r13, #REG_LR]
     
    184208        ldr     r9,  [r13, #REG_R9]
    185209        ldr     r10, [r13, #REG_R10]
    186         ldr     sp,  [r13, #REG_FP]
    187         ldr     lr,  [r13, #REG_IP]
     210        ldr     sp,  [r13, #REG_R11]
     211        ldr     lr,  [r13, #REG_R12]
    188212        ldr     lr,  [r13, #REG_SP]
    189213        ldr     lr,  [r13, #REG_LR]
     
    191215        subs    pc,r14,#4                       /* return */
    192216       
    193 
  • cpukit/score/cpu/arm/rtems/score/arm.h

    r74c402a2 r4f0b287  
    1 /*  no_cpu.h
    2  *
    3  *  This file is an example (i.e. "no CPU") of the file which is
    4  *  created for each CPU family port of RTEMS.
     1/* 
     2 *  $Id$
    53 *
    64 *
    75 *  COPYRIGHT (c) 2000 Canon Research Centre France SA.
    86 *  Emmanuel Raguet, mailto:raguet@crf.canon.fr
     7 *
     8 *  Copyright (c) 2002 Advent Networks, Inc.
     9 *       Jay Monkman <jmonkman@adventnetworks.com>
    910 *
    1011 *  The license and distribution terms for this file may be
     
    2930 *  of the family.
    3031 */
    31  
    32 #if defined(__arm__)
    33  
    34 #define CPU_MODEL_NAME  "arm"
    35 #define ARM_HAS_FPU     0
    36  
     32#if defined(__arm9__)
     33#  define CPU_MODEL_NAME  "arm9"
     34#  define ARM_HAS_FPU     0
     35#elif defined(__arm9tdmi__)
     36#  define CPU_MODEL_NAME  "arm9tdmi"
     37#  define ARM_HAS_FPU     0
     38#elif defined(__arm7__)
     39#  define CPU_MODEL_NAME  "arm7"
     40#  define ARM_HAS_FPU     0
     41#elif defined(__arm7tdmi__)
     42#  define CPU_MODEL_NAME  "arm7tdmi"
     43#  define ARM_HAS_FPU     0
     44#elif defined(__arm__)
     45#  define CPU_MODEL_NAME  "unknown ARM"
     46#  define ARM_HAS_FPU     0
    3747#else
    38  
    39 #error "Unsupported CPU Model"
    40  
     48#  error "Unsupported CPU Model"
    4149#endif
    4250
  • cpukit/score/cpu/arm/rtems/score/cpu.h

    r74c402a2 r4f0b287  
    1 /*  cpu.h
    2  *
    3  *  This include file contains information pertaining to the arm
     1/*
     2 *  This include file contains information pertaining to the ARM
    43 *  processor.
     4 *
     5 *  COPYRIGHT (c) 2002 Advent Networks, Inc.
     6 *        Jay Monkman <jmonkman@adventnetworks.com>
    57 *
    68 *  COPYRIGHT (c) 2000 Canon Research Centre France SA.
     
    1113 *  http://www.OARcorp.com/rtems/license.html.
    1214 *
    13  */
    14 
     15 *  $Id$
     16 */
     17
     18/* FIXME: finish commenting/cleaning up this file */
    1519#ifndef __CPU_h
    1620#define __CPU_h
     
    4448 */
    4549
    46 #define CPU_INLINE_ENABLE_DISPATCH       FALSE
     50#define CPU_INLINE_ENABLE_DISPATCH       TRUE
    4751
    4852/*
     
    6468 */
    6569
    66 #define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
     70#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
    6771
    6872/*
     
    100104 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
    101105 *
    102  *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
     106 *  Only one of CPU_HAS_SOFTWARE_INTERRU
    103107 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
    104108 *  possible that both are FALSE for a particular CPU.  Although it
     
    107111 */
    108112
    109 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
     113#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
    110114
    111115/*
     
    119123 */
    120124
    121 #define CPU_ALLOCATE_INTERRUPT_STACK FALSE
     125#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
    122126
    123127/*
     
    274278
    275279#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
    276 #define CPU_BIG_ENDIAN                           TRUE
    277 #define CPU_LITTLE_ENDIAN                        FALSE
     280#define CPU_BIG_ENDIAN                           FALSE
     281#define CPU_LITTLE_ENDIAN                        TRUE
    278282
    279283/*
     
    283287 */
    284288
    285 #define CPU_MODES_INTERRUPT_MASK   0x00000001
     289#define CPU_MODES_INTERRUPT_MASK   0x000000c0
    286290
    287291/*
     
    346350    unsigned32 register_lr;
    347351    unsigned32 register_pc;
     352    unsigned32 register_cpsr;
    348353} Context_Control;
    349354
     
    477482 */
    478483
    479 #define CPU_STACK_MINIMUM_SIZE          (1024*4)
     484#define CPU_STACK_MINIMUM_SIZE          (1024*16)
    480485
    481486/*
     
    484489 */
    485490
    486 #define CPU_ALIGNMENT              8
     491#define CPU_ALIGNMENT              4
    487492
    488493/*
     
    523528 */
    524529
    525 #define CPU_STACK_ALIGNMENT        32
     530#define CPU_STACK_ALIGNMENT        4
    526531
    527532/* ISR handler macros */
     
    538543 */
    539544
    540 #define _CPU_ISR_Disable( _level ) \
    541   { \
    542     (_level) = 0; \
    543    asm volatile ("MRS r0, cpsr          \n"  \
    544                  "ORR  r0, r0, #0xc0    \n" \
    545                  "MSR  cpsr, r0         \n" \
    546                    : : : "r0"); \
    547   }
     545#define _CPU_ISR_Disable( _level )                \
     546  do {                                            \
     547    int reg;                                      \
     548    asm volatile ("MRS        %0, cpsr \n"        \
     549                  "ORR  %1, %0, #0xc0 \n"         \
     550                  "MSR  cpsr, %1 \n"              \
     551                  "AND  %0, %0, #0xc0 \n"         \
     552                   : "=r" (_level), "=r" (reg)    \
     553                   : "0" (_level), "1" (reg));    \
     554  } while (0)
    548555
    549556/*
     
    553560 */
    554561
    555 #define _CPU_ISR_Enable( _level )  \
    556   { \
    557    asm volatile ("MRS r0, cpsr                  \n"  \
    558                  "AND  r0, r0, #0xFFFFFF3F      \n" \
    559                  "MSR  cpsr, r0                 \n" \
    560                  : : : "r0" ); \
    561   }
    562  
     562#define _CPU_ISR_Enable( _level )               \
     563  do {                                          \
     564    int reg;                                    \
     565    asm volatile ("MRS        %0, cpsr \n"      \
     566                  "BIC  %0, %0, #0xc0 \n"       \
     567                  "ORR  %0, %0, %2 \n"          \
     568                  "MSR  cpsr, %0 \n"            \
     569                  : "=r" (reg)                  \
     570                  : "0" (reg), "r" (_level));   \
     571  } while (0)
     572
    563573/*
    564574 *  This temporarily restores the interrupt to _level before immediately
     
    568578 */
    569579
    570 #define _CPU_ISR_Flash( _isr_cookie ) \
     580#define _CPU_ISR_Flash( _level ) \
    571581  { \
     582    int reg1;                                   \
     583    int reg2;                                   \
     584    asm volatile ("MRS  %0, cpsr \n"            \
     585                  "BIC  %1, %0, #0xc0 \n"       \
     586                  "ORR  %1, %1, %4 \n"          \
     587                  "MSR  cpsr, %1 \n"            \
     588                  "MSR  cpsr, %0 \n"            \
     589                  : "=r" (reg1), "=r" (reg2)    \
     590                  : "0" (reg1), "1" (reg2),  "r" (_level));       \
    572591  }
    573592
     
    587606#define _CPU_ISR_Set_level( new_level ) \
    588607  { \
     608    int reg;                                    \
     609    asm volatile ("MRS  %0, cpsr \n"            \
     610                  "BIC  %0, %0, #0xc0 \n"            \
     611                  "ORR  %0, %0, %2 \n"          \
     612                  "MSR  cpsr_c, %0 \n"            \
     613                  : "=r" (reg)                 \
     614                  : "0" (reg), "r" (new_level)); \
    589615  }
     616
    590617
    591618unsigned32 _CPU_ISR_Get_level( void );
     
    616643 */
    617644
    618 #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
    619                                  _isr, _entry_point, _is_fp ) \
    620   { \
    621    (_the_context)->register_sp = ((unsigned32)(_stack_base)) + (_size) ; \
    622    (_the_context)->register_pc = (_entry_point); \
    623   }
     645void _CPU_Context_Initialize(
     646  Context_Control  *the_context,
     647  unsigned32       *stack_base,
     648  unsigned32        size,
     649  unsigned32        new_level,
     650  void             *entry_point,
     651  boolean           is_fp
     652);
    624653
    625654/*
  • cpukit/score/cpu/arm/rtems/score/cpu_asm.h

    r74c402a2 r4f0b287  
    11/*
    2  *  cpu_asm.h
     2 *  $Id$
    33 *
    4  *  Very loose template for an include file for the cpu_asm.? file
    5  *  if it is implemented as a ".S" file (preprocessed by cpp) instead
    6  *  of a ".s" file (preprocessed by gm4 or gasp).
    7  *
    8  *  COPYRIGHT (c) 2000 Canon Research Centre France SA.
    9  *  Emmanuel Raguet, mailto:raguet@crf.canon.fr
     4 *  Copyright (c) 2002 by Advent Networks, Inc.
     5 *          Jay Monkman <jmonkman@adventnetworks.com>
    106 *
    117 *  The license and distribution terms for this file may be
    128 *  found in the file LICENSE in this distribution or at
    139 *  http://www.OARcorp.com/rtems/license.html.
     10 *
     11 *  This file is the include file for cpu_asm.S
    1412 *
    1513 *
     
    1917#define __CPU_ASM_h
    2018
    21 /* pull in the generated offsets */
    2219
    23 #include <rtems/score/offsets.h>
     20/* Registers saved in context switch: */
     21.set REG_R0,      0
     22.set REG_R1,      4
     23.set REG_R2,      8
     24.set REG_R3,     12
     25.set REG_R4,     16
     26.set REG_R5,     20
     27.set REG_R6,     24
     28.set REG_R7,     28
     29.set REG_R8,     32
     30.set REG_R9,     36
     31.set REG_R10,    40
     32.set REG_R11,    44
     33.set REG_R12,    48
     34.set REG_SP,     52
     35.set REG_LR,     56
     36.set REG_PC,     60
     37.set REG_CPSR,   64
     38.set SIZE_REGS,  REG_CPSR + 4
    2439
    25 /*
    26  * Hardware General Registers
    27  */
    28 
    29 /* put something here */
    30 
    31 /*
    32  * Hardware Floating Point Registers
    33  */
    34 
    35 /* put something here */
    36 
    37 /*
    38  * Hardware Control Registers
    39  */
    40 
    41 /* put something here */
    42 
    43 /*
    44  * Calling Convention
    45  */
    46 
    47 /* put something here */
    48 
    49 /*
    50  * Temporary registers
    51  */
    52 
    53 /* put something here */
    54 
    55 /*
    56  * Floating Point Registers - SW Conventions
    57  */
    58 
    59 /* put something here */
    60 
    61 /*
    62  * Temporary floating point registers
    63  */
    64 
    65 /* put something here */
    6640
    6741#endif
    68 
    69 /* end of file */
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