Changeset 4ef40152 in rtems
- Timestamp:
- 02/18/99 15:09:27 (24 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 9e5c391
- Parents:
- ee733965
- Location:
- c/src/exec/score/cpu/powerpc
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/exec/score/cpu/powerpc/Makefile.in
ree733965 r4ef40152 20 20 21 21 # H_FILES that get installed externally 22 EXTERNAL_H_FILES = $(srcdir)/asm.h 22 EXTERNAL_H_FILES = $(srcdir)/asm.h $(srcdir)/mpc860.h 23 23 24 24 # Assembly source names, if any, go here -- minus the .S -
c/src/exec/score/cpu/powerpc/cpu.c
ree733965 r4ef40152 406 406 }; 407 407 408 #ifdef mpc860 409 const CPU_Trap_table_entry _CPU_Trap_slot_template_m860 = { 410 0x7c0803ac, /* mtlr %r0 */ 411 0x81210028, /* lwz %r9, IP_9(%r1) */ 412 0x38000000, /* li %r0, PPC_IRQ */ 413 0x48000002 /* b PROC (_ISR_Handler) */ 414 }; 415 #endif /* mpc860 */ 416 408 417 unsigned32 ppc_exception_vector_addr( 409 418 unsigned32 vector … … 484 493 *old_handler = (proc_ptr) u32_handler; 485 494 } else 495 /* There are two kinds of handlers for the MPC860. One is the 'standard' 496 * one like above. The other is for the cascaded interrupts from the SIU 497 * and CPM. Therefore we must check for the alternate one if the standard 498 * one is not present 499 */ 500 #ifdef mpc860 501 if (slot->stwu_r1 == _CPU_Trap_slot_template_m860.stwu_r1) { 502 /* 503 * Set u32_handler = to target address 504 */ 505 u32_handler = slot->b_Handler & 0x03fffffc; 506 *old_handler = (proc_ptr) u32_handler; 507 } else 508 #endif /* mpc860 */ 509 486 510 *old_handler = 0; 487 511 … … 489 513 * Copy the template to the slot and then fix it. 490 514 */ 515 #ifdef mpc860 516 if (vector > PPC_STD_IRQ_LAST) 517 *slot = _CPU_Trap_slot_template_m860; 518 else 519 #endif /* mpc860 */ 491 520 *slot = _CPU_Trap_slot_template; 492 521 … … 643 672 Offset = 0x1400; 644 673 break; 674 675 #elif defined(mpc860) 676 case PPC_IRQ_IRQ0: 677 Offset = 0x1000; 678 break; 679 case PPC_IRQ_LVL0: 680 Offset = 0x1040; 681 break; 682 case PPC_IRQ_IRQ1: 683 Offset = 0x1080; 684 break; 685 case PPC_IRQ_LVL1: 686 Offset = 0x10c0; 687 break; 688 case PPC_IRQ_IRQ2: 689 Offset = 0x1100; 690 break; 691 case PPC_IRQ_LVL2: 692 Offset = 0x1140; 693 break; 694 case PPC_IRQ_IRQ3: 695 Offset = 0x1180; 696 break; 697 case PPC_IRQ_LVL3: 698 Offset = 0x11c0; 699 break; 700 case PPC_IRQ_IRQ4: 701 Offset = 0x1200; 702 break; 703 case PPC_IRQ_LVL4: 704 Offset = 0x1240; 705 break; 706 case PPC_IRQ_IRQ5: 707 Offset = 0x1280; 708 break; 709 case PPC_IRQ_LVL5: 710 Offset = 0x12c0; 711 break; 712 case PPC_IRQ_IRQ6: 713 Offset = 0x1300; 714 break; 715 case PPC_IRQ_LVL6: 716 Offset = 0x1340; 717 break; 718 case PPC_IRQ_IRQ7: 719 Offset = 0x1380; 720 break; 721 case PPC_IRQ_LVL7: 722 Offset = 0x13c0; 723 break; 724 case PPC_IRQ_CPM_RESERVED_0: 725 Offset = 0x1400; 726 break; 727 case PPC_IRQ_CPM_PC4: 728 Offset = 0x1410; 729 break; 730 case PPC_IRQ_CPM_PC5: 731 Offset = 0x1420; 732 break; 733 case PPC_IRQ_CPM_SMC2: 734 Offset = 0x1430; 735 break; 736 case PPC_IRQ_CPM_SMC1: 737 Offset = 0x1440; 738 break; 739 case PPC_IRQ_CPM_SPI: 740 Offset = 0x1450; 741 break; 742 case PPC_IRQ_CPM_PC6: 743 Offset = 0x1460; 744 break; 745 case PPC_IRQ_CPM_TIMER4: 746 Offset = 0x1470; 747 break; 748 case PPC_IRQ_CPM_RESERVED_8: 749 Offset = 0x1480; 750 break; 751 case PPC_IRQ_CPM_PC7: 752 Offset = 0x1490; 753 break; 754 case PPC_IRQ_CPM_PC8: 755 Offset = 0x14a0; 756 break; 757 case PPC_IRQ_CPM_PC9: 758 Offset = 0x14b0; 759 break; 760 case PPC_IRQ_CPM_TIMER3: 761 Offset = 0x14c0; 762 break; 763 case PPC_IRQ_CPM_RESERVED_D: 764 Offset = 0x14d0; 765 break; 766 case PPC_IRQ_CPM_PC10: 767 Offset = 0x14e0; 768 break; 769 case PPC_IRQ_CPM_PC11: 770 Offset = 0x14f0; 771 break; 772 case PPC_IRQ_CPM_I2C: 773 Offset = 0x1500; 774 break; 775 case PPC_IRQ_CPM_RISC_TIMER: 776 Offset = 0x1510; 777 break; 778 case PPC_IRQ_CPM_TIMER2: 779 Offset = 0x1520; 780 break; 781 case PPC_IRQ_CPM_RESERVED_13: 782 Offset = 0x1530; 783 break; 784 case PPC_IRQ_CPM_IDMA2: 785 Offset = 0x1540; 786 break; 787 case PPC_IRQ_CPM_IDMA1: 788 Offset = 0x1550; 789 break; 790 case PPC_IRQ_CPM_SDMA_ERROR: 791 Offset = 0x1560; 792 break; 793 case PPC_IRQ_CPM_PC12: 794 Offset = 0x1570; 795 break; 796 case PPC_IRQ_CPM_PC13: 797 Offset = 0x1580; 798 break; 799 case PPC_IRQ_CPM_TIMER1: 800 Offset = 0x1590; 801 break; 802 case PPC_IRQ_CPM_PC14: 803 Offset = 0x15a0; 804 break; 805 case PPC_IRQ_CPM_SCC4: 806 Offset = 0x15b0; 807 break; 808 case PPC_IRQ_CPM_SCC3: 809 Offset = 0x15c0; 810 break; 811 case PPC_IRQ_CPM_SCC2: 812 Offset = 0x15d0; 813 break; 814 case PPC_IRQ_CPM_SCC1: 815 Offset = 0x15e0; 816 break; 817 case PPC_IRQ_CPM_PC15: 818 Offset = 0x15f0; 819 break; 645 820 #endif 646 821 -
c/src/exec/score/cpu/powerpc/cpu.h
ree733965 r4ef40152 475 475 boolean exceptions_in_RAM; /* TRUE if in RAM */ 476 476 477 #if defined(ppc403)477 #if (defined(ppc403) || defined(mpc860)) 478 478 unsigned32 serial_per_sec; /* Serial clocks per second */ 479 479 boolean serial_external_clock; … … 484 484 unsigned32 timer_least_valid; /* Least valid number from timer */ 485 485 boolean timer_internal_clock; /* TRUE, when timer runs with CPU clk */ 486 #endif 487 488 #if (defined(mpc860)) 489 unsigned32 clock_speed; /* Speed of CPU in Hz */ 486 490 #endif 487 491 } rtems_cpu_table; -
c/src/exec/score/cpu/powerpc/ppc.h
ree733965 r4ef40152 7 7 * 8 8 * COPYRIGHT (c) 1995 by i-cubed ltd. 9 * 10 * MPC860 support code was added by Jay Monkman <jmonkman@frasca.com> 9 11 * 10 12 * To anyone who acknowledges that this file is provided "AS IS" … … 178 180 #define PPC_D_CACHE 16384 179 181 182 #elif defined(mpc860) 183 /* 184 * Added by Jay Monkman (jmonkman@frasca.com) 6/28/98 185 */ 186 #define CPU_MODEL_NAME "PowerPC MPC860" 187 188 #define PPC_ALIGNMENT 4 189 #define PPC_I_CACHE 4096 190 #define PPC_D_CACHE 4096 191 #define PPC_CACHE_ALIGNMENT 16 192 #define PPC_INTERRUPT_MAX 64 193 #define PPC_HAS_FPU 0 194 #define PPC_HAS_DOUBLE 0 195 #define PPC_USE_MULTIPLE 1 196 #define PPC_USE_SPRG 1 197 198 #define PPC_MSR_0 0x00009000 199 #define PPC_MSR_1 0x00001000 200 #define PPC_MSR_2 0x00001000 201 #define PPC_MSR_3 0x00000000 202 180 203 #else 181 204 … … 414 437 #define PPC_IRQ_LAST PPC604_IRQ_SYS_MGT 415 438 439 #elif defined(mpc860) 440 #define PPC_IRQ_IRQ0 (PPC_STD_IRQ_LAST + 1) 441 #define PPC_IRQ_LVL0 (PPC_STD_IRQ_LAST + 2) 442 #define PPC_IRQ_IRQ1 (PPC_STD_IRQ_LAST + 3) 443 #define PPC_IRQ_LVL1 (PPC_STD_IRQ_LAST + 4) 444 #define PPC_IRQ_IRQ2 (PPC_STD_IRQ_LAST + 5) 445 #define PPC_IRQ_LVL2 (PPC_STD_IRQ_LAST + 6) 446 #define PPC_IRQ_IRQ3 (PPC_STD_IRQ_LAST + 7) 447 #define PPC_IRQ_LVL3 (PPC_STD_IRQ_LAST + 8) 448 #define PPC_IRQ_IRQ4 (PPC_STD_IRQ_LAST + 9) 449 #define PPC_IRQ_LVL4 (PPC_STD_IRQ_LAST + 10) 450 #define PPC_IRQ_IRQ5 (PPC_STD_IRQ_LAST + 11) 451 #define PPC_IRQ_LVL5 (PPC_STD_IRQ_LAST + 12) 452 #define PPC_IRQ_IRQ6 (PPC_STD_IRQ_LAST + 13) 453 #define PPC_IRQ_LVL6 (PPC_STD_IRQ_LAST + 14) 454 #define PPC_IRQ_IRQ7 (PPC_STD_IRQ_LAST + 15) 455 #define PPC_IRQ_LVL7 (PPC_STD_IRQ_LAST + 16) 456 #define PPC_IRQ_CPM_RESERVED_0 (PPC_STD_IRQ_LAST + 17) 457 #define PPC_IRQ_CPM_PC4 (PPC_STD_IRQ_LAST + 18) 458 #define PPC_IRQ_CPM_PC5 (PPC_STD_IRQ_LAST + 19) 459 #define PPC_IRQ_CPM_SMC2 (PPC_STD_IRQ_LAST + 20) 460 #define PPC_IRQ_CPM_SMC1 (PPC_STD_IRQ_LAST + 21) 461 #define PPC_IRQ_CPM_SPI (PPC_STD_IRQ_LAST + 22) 462 #define PPC_IRQ_CPM_PC6 (PPC_STD_IRQ_LAST + 23) 463 #define PPC_IRQ_CPM_TIMER4 (PPC_STD_IRQ_LAST + 24) 464 #define PPC_IRQ_CPM_RESERVED_8 (PPC_STD_IRQ_LAST + 25) 465 #define PPC_IRQ_CPM_PC7 (PPC_STD_IRQ_LAST + 26) 466 #define PPC_IRQ_CPM_PC8 (PPC_STD_IRQ_LAST + 27) 467 #define PPC_IRQ_CPM_PC9 (PPC_STD_IRQ_LAST + 28) 468 #define PPC_IRQ_CPM_TIMER3 (PPC_STD_IRQ_LAST + 29) 469 #define PPC_IRQ_CPM_RESERVED_D (PPC_STD_IRQ_LAST + 30) 470 #define PPC_IRQ_CPM_PC10 (PPC_STD_IRQ_LAST + 31) 471 #define PPC_IRQ_CPM_PC11 (PPC_STD_IRQ_LAST + 32) 472 #define PPC_IRQ_CPM_I2C (PPC_STD_IRQ_LAST + 33) 473 #define PPC_IRQ_CPM_RISC_TIMER (PPC_STD_IRQ_LAST + 34) 474 #define PPC_IRQ_CPM_TIMER2 (PPC_STD_IRQ_LAST + 35) 475 #define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 36) 476 #define PPC_IRQ_CPM_IDMA2 (PPC_STD_IRQ_LAST + 37) 477 #define PPC_IRQ_CPM_IDMA1 (PPC_STD_IRQ_LAST + 38) 478 #define PPC_IRQ_CPM_SDMA_ERROR (PPC_STD_IRQ_LAST + 39) 479 #define PPC_IRQ_CPM_PC12 (PPC_STD_IRQ_LAST + 40) 480 #define PPC_IRQ_CPM_PC13 (PPC_STD_IRQ_LAST + 41) 481 #define PPC_IRQ_CPM_TIMER1 (PPC_STD_IRQ_LAST + 42) 482 #define PPC_IRQ_CPM_PC14 (PPC_STD_IRQ_LAST + 43) 483 #define PPC_IRQ_CPM_SCC4 (PPC_STD_IRQ_LAST + 44) 484 #define PPC_IRQ_CPM_SCC3 (PPC_STD_IRQ_LAST + 45) 485 #define PPC_IRQ_CPM_SCC2 (PPC_STD_IRQ_LAST + 46) 486 #define PPC_IRQ_CPM_SCC1 (PPC_STD_IRQ_LAST + 47) 487 #define PPC_IRQ_CPM_PC15 (PPC_STD_IRQ_LAST + 48) 488 489 #define PPC_IRQ_LAST PPC_IRQ_CPM_PC15 490 416 491 #endif 417 492
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