Changeset 4dd1aa5 in rtems


Ignore:
Timestamp:
Jan 22, 2001, 2:11:09 PM (19 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
9f87484
Parents:
d6b1d73
Message:

2001-01-22 Radzislaw Galler <rgaller@…>

  • clock/ckinit.c (Install_clock): Modified MTU timer 0 initialization to generate an interrupt exactly every 1us
Location:
c/src/lib/libcpu/sh/sh7045
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/sh/sh7045/ChangeLog

    rd6b1d73 r4dd1aa5  
     12001-01-22  Radzislaw Galler  <rgaller@et.put.poznan.pl>
     2
     3        * clock/ckinit.c (Install_clock): Modified MTU timer 0 initialization
     4        to generate an interrupt exactly every 1us
     5
    162001-01-05      Joel Sherrill <joel@OARcorp.com>
    27
  • c/src/lib/libcpu/sh/sh7045/clock/ckinit.c

    rd6b1d73 r4dd1aa5  
    4545#include <rtems/score/iosh7045.h>
    4646
    47 #define _MTU_COUNTER0_MICROSECOND (Clock_MHZ/4)
     47#define _MTU_COUNTER0_MICROSECOND (Clock_MHZ/16)
    4848
    4949#ifndef CLOCKPRIO
     
    5454#define MTU0_SYNCMASK   0xfe
    5555#define MTU0_MODEMASK   0xc0
    56 #define MTU0_TCRMASK    0x01 /* bit 7 also used, vs 703x */
     56#define MTU0_TCRMASK    0x22 /* bit 7 also used, vs 703x */
    5757#define MTU0_STAT_MASK  0xc0
    5858#define MTU0_IRQMASK    0xfe
     
    151151{
    152152  unsigned8 temp8 = 0;
     153  unsigned32 factor = 1000000;
     154 
    153155 
    154156  /*
     
    159161  Clock_isrs_const = rtems_configuration_get_microseconds_per_tick() / 10000;
    160162  Clock_isrs = Clock_isrs_const;
    161 
    162   Clock_MHZ = rtems_cpu_configuration_get_clicks_per_second() / 1000000 ;
     163 
     164  factor /= rtems_configuration_get_microseconds_per_tick(); /* minimalization of integer division error */
     165  Clock_MHZ = rtems_cpu_configuration_get_clicks_per_second() / factor ;
    163166
    164167  rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker );
     
    183186  write8( temp8, MTU_TMDR0);
    184187
    185   /* TCNT is cleared by GRA ; internal clock /4 */
     188  /* TCNT is cleared by GRA ; internal clock /16 */
    186189  write8( MTU0_TCRMASK , MTU_TCR0);
    187190
     
    202205
    203206  /* set counter limits */
    204   write16( _MTU_COUNTER0_MICROSECOND *
    205     rtems_configuration_get_microseconds_per_tick(), MTU_GR0A);
     207  write16( _MTU_COUNTER0_MICROSECOND, MTU_GR0A);
    206208   
    207209  /* start counter */
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