Changeset 4daebbd in rtems


Ignore:
Timestamp:
Aug 14, 2008, 3:25:14 PM (11 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.9, master
Children:
e73f9f6b
Parents:
b281e42
Message:

2008-08-14 Sebastian Huber <sebastian.huber@…>

  • rtems/include/rtems/rtems/ratemon.h, rtems/include/rtems/rtems/status.h, score/include/rtems/score/coremutex.h, score/include/rtems/score/object.h: Removed extraneous commas.
Location:
cpukit
Files:
10 edited

Legend:

Unmodified
Added
Removed
  • cpukit/ChangeLog

    rb281e42 r4daebbd  
     12008-08-14     Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * rtems/include/rtems/rtems/ratemon.h,
     4        rtems/include/rtems/rtems/status.h,
     5        score/include/rtems/score/coremutex.h,
     6        score/include/rtems/score/object.h: Removed extraneous commas.
     7
    182008-08-08      Joel Sherrill <joel.sherrill@OARcorp.com>
    29
  • cpukit/rtems/include/rtems/rtems/ratemon.h

    rb281e42 r4daebbd  
    120120   * all time to complete this iteration of the period.
    121121   */
    122   RATE_MONOTONIC_EXPIRED,
     122  RATE_MONOTONIC_EXPIRED
    123123}   rtems_rate_monotonic_period_states;
    124124
  • cpukit/rtems/include/rtems/rtems/status.h

    rb281e42 r4daebbd  
    170170   *  @note This status will @b NOT be returned to the user.
    171171   */
    172   RTEMS_PROXY_BLOCKING           = 28,
     172  RTEMS_PROXY_BLOCKING           = 28
    173173} rtems_status_code;
    174174
  • cpukit/score/cpu/bfin/cpu.c

    rb281e42 r4daebbd  
    3030 */
    3131
     32
     33extern void _ISR15_Handler(void);
     34extern void _CPU_Emulation_handler(void);
     35extern void _CPU_Reset_handler(void);
     36extern void _CPU_NMI_handler(void);
     37extern void _CPU_Exception_handler(void);
     38extern void _CPU_Unhandled_Interrupt_handler(void);
    3239
    3340void _CPU_Initialize(
     
    4653   */
    4754
    48   _CPU_Thread_dispatch_pointer = thread_dispatch;
     55  /*_CPU_Thread_dispatch_pointer = thread_dispatch;*/
    4956
    5057  /*
     
    5663
    5764  /* FP context initialization support goes here */
    58 }
     65
     66
     67
     68  proc_ptr ignored;
     69
     70#if 0
     71  /* occassionally useful debug stuff */
     72  int i;
     73  _CPU_ISR_install_raw_handler(0, _CPU_Emulation_handler, &ignored);
     74  _CPU_ISR_install_raw_handler(1, _CPU_Reset_handler, &ignored);
     75  _CPU_ISR_install_raw_handler(2, _CPU_NMI_handler, &ignored);
     76  _CPU_ISR_install_raw_handler(3, _CPU_Exception_handler, &ignored);
     77  for (i = 5; i < 15; i++)
     78    _CPU_ISR_install_raw_handler(i, _CPU_Unhandled_Interrupt_handler, &ignored);
     79#endif
     80
     81  /* install handler that will be used to call _Thread_Dispatch */
     82  _CPU_ISR_install_raw_handler( 15, _ISR15_Handler, &ignored );
     83  /* enable self nesting */
     84  __asm__ __volatile__ ("syscfg = %0" : : "d" (0x00000004));
     85}
     86
     87
     88
    5989
    6090/*PAGE
     
    79109    _tmpimask = *((uint32_t*)IMASK);
    80110
    81     return _tmpimask;
     111    return (_tmpimask & 0xffe0) ? 0 : 1;
    82112}
    83113
     
    137167)
    138168{
     169   proc_ptr ignored;
     170
    139171   *old_handler = _ISR_Vector_table[ vector ];
    140 
    141    /*
    142     *  If the interrupt vector table is a table of pointer to isr entry
    143     *  points, then we need to install the appropriate RTEMS interrupt
    144     *  handler for this vector number.
    145     */
    146 
    147    _CPU_ISR_install_raw_handler( vector, _ISR_Handler, old_handler );
    148172
    149173   /*
     
    153177
    154178    _ISR_Vector_table[ vector ] = new_handler;
    155 }
     179
     180    _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
     181}
     182
     183#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
     184void *_CPU_Thread_Idle_body(uint32_t ignored) {
     185
     186    while (1) {
     187        __asm__ __volatile__("ssync; idle; ssync");
     188    }
     189}
     190#endif
    156191
    157192/*
     
    171206
    172207    the_context->register_sp = stack_high;
    173     // gcc/config/bfin/bfin.h defines CPU_MINIMUM_STACK_FRAME_SIZE = 0 thus we do sp=fp
    174     // is this correct ?????
    175     the_context->register_fp = stack_high;
    176208    the_context->register_rets = (uint32_t) entry_point;
    177 
    178     //mask the interrupt level
     209    the_context->imask = new_level ? 0 : 0xffff;
    179210}
    180211
  • cpukit/score/cpu/bfin/cpu_asm.S

    rb281e42 r4daebbd  
    55 *  in assembly language
    66 *
     7 *  Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
     8 *             written by Allan Hessenflow <allanh@kallisti.com>
     9 *
     10 *  Based on earlier version:
     11 *
    712 *  Copyright (c) 2006 by Atos Automacao Industrial Ltda.
    8  *            written by Alain Schaefer <alain.schaefer@easc.ch>
    9  *                    and Antonio Giovanini <antonio@atos.com.br>
     13 *                      written by Alain Schaefer <alain.schaefer@easc.ch>
     14 *                                      and Antonio Giovanini <antonio@atos.com.br>
    1015 *
    1116 *  The license and distribution terms for this file may be
     
    1520 *  $Id$
    1621 */
    17  
    18  
     22
     23
    1924#include <rtems/asm.h>
    2025#include <rtems/score/cpu_asm.h>
     
    2530#define HI(con32) (((con32) >> 16) & 0xFFFF)
    2631
     32
     33#if 0
     34/* some debug routines */
     35        .globl __CPU_write_char;
     36__CPU_write_char:
     37        p0.h = 0xffc0;
     38        p0.l = 0x0400;
     39txWaitLoop:
     40        r1 = w[p0 + 0x14];
     41        cc = bittst(r1, 5);
     42        if !cc jump txWaitLoop;
     43        w[p0 + 0x00] = r0;
     44        rts;
     45
     46        .globl __CPU_write_crlf;
     47__CPU_write_crlf:
     48        r0 = '\r';
     49        [--sp] = rets;
     50        call __CPU_write_char;
     51        rets = [sp++];
     52        r0 = '\n';
     53        jump __CPU_write_char;
     54
     55__CPU_write_space:
     56        r0 = ' ';
     57        jump __CPU_write_char;
     58
     59        .globl __CPU_write_nybble;
     60__CPU_write_nybble:
     61        r1 = 0x0f;
     62        r0 = r0 & r1;
     63        r0 += '0';
     64        r1 = '9';
     65        cc = r0 <= r1;
     66        if cc jump __CPU_write_char;
     67        r0 += 'a' - '0' - 10;
     68        jump __CPU_write_char;
     69
     70        .globl __CPU_write_byte;
     71__CPU_write_byte:
     72        [--sp] = r0;
     73        [--sp] = rets;
     74        r0 >>= 4;
     75        call __CPU_write_nybble;
     76        rets = [sp++];
     77        r0 = [sp++];
     78        jump __CPU_write_nybble;
     79
     80__CPU_write_chawmp:
     81        [--sp] = r0;
     82        [--sp] = rets;
     83        r0 >>= 8;
     84        call __CPU_write_byte;
     85        rets = [sp++];
     86        r0 = [sp++];
     87        jump __CPU_write_byte;
     88
     89__CPU_write_gawble:
     90        [--sp] = r0;
     91        [--sp] = rets;
     92        r0 >>= 16;
     93        call __CPU_write_chawmp;
     94        rets = [sp++];
     95        r0 = [sp++];
     96        jump __CPU_write_chawmp;
     97
     98__CPU_dump_registers:
     99        [--sp] = rets;
     100        [--sp] = r0;
     101        [--sp] = r1;
     102        [--sp] = p0;
     103        r0 = [sp + 8];
     104        call __CPU_write_gawble;
     105        call __CPU_write_space;
     106        r0 = [sp + 4];
     107        call __CPU_write_gawble;
     108        call __CPU_write_space;
     109        r0 = r2;
     110        call __CPU_write_gawble;
     111        call __CPU_write_space;
     112        r0 = r3;
     113        call __CPU_write_gawble;
     114        call __CPU_write_space;
     115        r0 = r4;
     116        call __CPU_write_gawble;
     117        call __CPU_write_space;
     118        r0 = r5;
     119        call __CPU_write_gawble;
     120        call __CPU_write_space;
     121        r0 = r6;
     122        call __CPU_write_gawble;
     123        call __CPU_write_space;
     124        r0 = r7;
     125        call __CPU_write_gawble;
     126        call __CPU_write_crlf;
     127        r0 = [sp];
     128        call __CPU_write_gawble;
     129        call __CPU_write_space;
     130        r0 = p1;
     131        call __CPU_write_gawble;
     132        call __CPU_write_space;
     133        r0 = p2;
     134        call __CPU_write_gawble;
     135        call __CPU_write_space;
     136        r0 = p3;
     137        call __CPU_write_gawble;
     138        call __CPU_write_space;
     139        r0 = p4;
     140        call __CPU_write_gawble;
     141        call __CPU_write_space;
     142        r0 = p5;
     143        call __CPU_write_gawble;
     144        call __CPU_write_space;
     145        r0 = fp;
     146        call __CPU_write_gawble;
     147        call __CPU_write_space;
     148        r0 = sp;
     149        r0 += 16;
     150        call __CPU_write_gawble;
     151        call __CPU_write_crlf;
     152
     153        p0 = [sp++];
     154        r1 = [sp++];
     155        r0 = [sp++];
     156        rets = [sp++];
     157        rts;
     158
     159        .globl __CPU_Exception_handler;
     160__CPU_Exception_handler:
     161        usp = sp;
     162        sp.h = 0xffb0;
     163        sp.l = 0x1000;
     164        [--sp] = (r7:0,p5:0);
     165
     166        r0 = 'x';
     167        call __CPU_write_char;
     168        jump hcf;
     169
     170
     171        .globl __CPU_Emulation_handler;
     172__CPU_Emulation_handler:
     173        usp = sp;
     174        sp.h = 0xffb0;
     175        sp.l = 0x1000;
     176        [--sp] = (r7:0,p5:0);
     177
     178        r0 = 'e';
     179        call __CPU_write_char;
     180        jump hcf;
     181
     182        .globl __CPU_Reset_handler;
     183__CPU_Reset_handler:
     184        usp = sp;
     185        sp.h = 0xffb0;
     186        sp.l = 0x1000;
     187        [--sp] = (r7:0,p5:0);
     188
     189        r0 = 'r';
     190        call __CPU_write_char;
     191        jump hcf;
     192
     193        .globl __CPU_NMI_handler;
     194__CPU_NMI_handler:
     195        usp = sp;
     196        sp.h = 0xffb0;
     197        sp.l = 0x1000;
     198        [--sp] = (r7:0,p5:0);
     199
     200        r0 = 'n';
     201        call __CPU_write_char;
     202        jump hcf;
     203
     204        .globl __CPU_Unhandled_Interrupt_handler;
     205__CPU_Unhandled_Interrupt_handler:
     206        usp = sp;
     207        sp.h = 0xffb0;
     208        sp.l = 0x1000;
     209        [--sp] = (r7:0,p5:0);
     210
     211        call __CPU_write_crlf;
     212        r0 = 'i';
     213        call __CPU_write_char;
     214        p0.h = HI(IPEND);
     215        p0.l = LO(IPEND);
     216        r0 = [p0];
     217        call __CPU_write_chawmp;
     218        jump hcf;
     219
     220hcf:
     221        idle;
     222        jump hcf;
     223
     224#endif
     225
     226
    27227/*  _CPU_Context_switch
    28228 *
     
    32232 *
    33233 *  For now we simply save all registers.
    34  * 
     234 *
    35235 */
    36236
    37 .globl __CPU_Context_switch
     237/* make sure this sequence stays in sync with the definition for
     238   Context_Control in rtems/score/cpu.h */
     239        .globl __CPU_Context_switch
    38240__CPU_Context_switch:
    39     /* Start saving context R0 = current, R1=heir */
    40     /*save P0 first*/
    41     [FP+0x8] = P0;
    42     P0 = R0;
    43     [ P0 + R0_OFFSET ] = R0;
    44     [ P0 + R1_OFFSET] = R1;
    45     [ P0 + R2_OFFSET] = R2;
    46     [ P0 + R4_OFFSET] = R4;
    47     [ P0 + R3_OFFSET] = R3;
    48     [ P0 + R5_OFFSET] = R5;
    49     [ P0 + R6_OFFSET] = R6;
    50     [ P0 + R7_OFFSET] = R7;
    51     [ P0 + P1_OFFSET] = P1;
    52     /* save the original value of P0 */
    53     P1 = [FP+0x8];
    54     [ P0 + P0_OFFSET] = P1;
    55     [ P0 + P2_OFFSET] = P2;
    56     [ P0 + P3_OFFSET] = P3;
    57     [ P0 + P4_OFFSET] = P4;
    58     [ P0 + P5_OFFSET] = P5;
    59     [ P0 + FP_OFFSET] = FP;
    60     [ P0 + SP_OFFSET] = SP;
    61    
    62     /* save ASTAT */
    63     R0 = ASTAT;
    64     [P0 + ASTAT_OFFSET] = R0;
    65 
    66     /* save Loop Counters */
    67     R0 = LC0;
    68     [P0 + LC0_OFFSET] = R0;
    69     R0 = LC1;
    70     [P0 + LC1_OFFSET] = R0;
    71 
    72     /* save Accumulators */
    73     R0 = A0.W;
    74     [P0 + A0W_OFFSET] = R0;
    75     R0 = A0.X;
    76     [P0 + A0X_OFFSET] = R0;
    77     R0 = A1.W;
    78     [P0 + A1W_OFFSET] = R0;
    79     R0 = A1.X;
    80     [P0 + A1X_OFFSET] = R0;
    81    
    82     /* save Index Registers */
    83     R0 = I0;
    84     [P0 + I0_OFFSET] = R0;
    85     R0 = I1;
    86     [P0 + I1_OFFSET] = R0;
    87     R0 = I2;
    88     [P0 + I2_OFFSET] = R0;
    89     R0 = I3;
    90     [P0 + I3_OFFSET] = R0;
    91 
    92     /* save Modifier Registers */
    93     R0 = M0;
    94     [P0 + M0_OFFSET] = R0;
    95     R0 = M1;
    96     [P0 + M1_OFFSET] = R0;
    97     R0 = M2;
    98     [P0 + M2_OFFSET] = R0;
    99     R0 = M3;
    100     [P0 + M3_OFFSET] = R0;
    101 
    102     /* save Length Registers */
    103     R0 = L0;
    104     [P0 + L0_OFFSET] = R0;
    105     R0 = L1;
    106     [P0 + L1_OFFSET] = R0;
    107     R0 = L2;
    108     [P0 + L2_OFFSET] = R0;
    109     R0 = L3;
    110     [P0 + L3_OFFSET] = R0;
    111 
    112     /* Base Registers */
    113     R0 = B0;
    114     [P0 + B0_OFFSET] = R0;
    115     R0 = B1;
    116     [P0 + B1_OFFSET] = R0;
    117     R0 = B2;
    118     [P0 + B2_OFFSET] = R0;
    119     R0 = B3;
    120     [P0 + B3_OFFSET] = R0;
    121    
    122     /* save RETS */
    123     R0 = RETS;
    124     [ P0 + RETS_OFFSET] = R0;
    125 
     241        /* Start saving context R0 = current, R1=heir */
     242        p0 = r0;
     243        [p0++] = r4;
     244        [p0++] = r5;
     245        [p0++] = r6;
     246        [p0++] = r7;
     247
     248        /* save pointer registers */
     249        [p0++] = p3;
     250        [p0++] = p4;
     251        [p0++] = p5;
     252        [p0++] = fp;
     253        [p0++] = sp;
     254
     255        /* save length registers */
     256        r0 = l0;
     257        [p0++] = r0;
     258        r0 = l1;
     259        [p0++] = r0;
     260        r0 = l2;
     261        [p0++] = r0;
     262        r0 = l3;
     263        [p0++] = r0;
     264
     265        /* save rets */
     266        r0 = rets;
     267        [p0++] = r0;
     268
     269        /* save IMASK */
     270        p1.h = HI(IMASK);
     271        p1.l = LO(IMASK);
     272        r0 = [p1];
     273        [p0++] = r0;
     274
     275        p0 = r1;
    126276restore:
    127     P0 = R1;
    128     R1 = [P0 + R1_OFFSET]; 
    129     R2 = [P0 + R2_OFFSET];
    130     R3 = [P0 + R3_OFFSET];
    131     R4 = [P0 + R4_OFFSET];
    132     R5 = [P0 + R5_OFFSET];
    133     R6 = [P0 + R6_OFFSET];
    134     R7 = [P0 + R7_OFFSET];
    135        
    136     P2 = [P0 + P2_OFFSET];
    137     P3 = [P0 + P3_OFFSET];
    138     P4 = [P0 + P4_OFFSET];
    139     P5 = [P0 + P5_OFFSET];
    140 
    141     /* might have to be placed more to the end */
    142     FP = [P0 + FP_OFFSET];
    143     SP = [P0 + SP_OFFSET];
    144 
    145     /* save ASTAT */
    146     R0 = [P0 + ASTAT_OFFSET];
    147     ASTAT = R0;
    148 
    149     /* save Loop Counters */
    150     R0 = [P0 + LC0_OFFSET];
    151     LC0 = R0;
    152     R0 = [P0 + LC1_OFFSET];
    153     LC1 = R0;
    154 
    155     /* save Accumulators */
    156     R0 = [P0 + A0W_OFFSET];
    157     A0.W = R0;
    158     R0 = [P0 + A0X_OFFSET];
    159     A0.X = R0;
    160     R0 = [P0 + A1W_OFFSET];
    161     A1.W = R0;
    162     R0 = [P0 + A1X_OFFSET];
    163     A1.X = R0;
    164 
    165     /* save Index Registers */
    166     R0 = [P0 + I0_OFFSET];
    167     I0 = R0;
    168     R0 = [P0 + I1_OFFSET];
    169     I1 = R0;
    170     R0 = [P0 + I2_OFFSET];
    171     I2 = R0;
    172     R0 = [P0 + I3_OFFSET];
    173     I3 = R0;
    174 
    175     /* save Modifier Registers */
    176     R0 = [P0 + M0_OFFSET];
    177     M0 = R0;
    178     R0 = [P0 + M1_OFFSET];
    179     M1 = R0;
    180     R0 = [P0 + M2_OFFSET];
    181     M2 = R0;
    182     R0 = [P0 + M3_OFFSET];
    183     M3 = R0;
    184 
    185     /* save Length Registers */
    186     R0 = [P0 + L0_OFFSET];
    187     L0 = R0;
    188     R0 = [P0 + L1_OFFSET];
    189     L1 = R0;
    190     R0 = [P0 + L2_OFFSET];
    191     L2 = R0;
    192     R0 = [P0 + L3_OFFSET];
    193     L3 = R0;
    194 
    195     /* Base Registers */
    196     R0 = [P0 + B0_OFFSET];
    197     B0 = R0;
    198     R0 = [P0 + B1_OFFSET];
    199     B1 = R0;
    200     R0 = [P0 + B2_OFFSET];
    201     B2 = R0;
    202     R0 = [P0 + B3_OFFSET];
    203     B3 = R0;
    204 
    205     /* restore RETS */
    206     P1 = [P0 + RETS_OFFSET];
    207     RETS = P1;
    208 
    209     /* now restore the P1 + P0 */
    210     P1 = [P0 + R1_OFFSET];   
    211     P0 = [P0 + P0_OFFSET];
    212    
    213     rts;
    214    
     277        /* restore data registers */
     278        r4 = [p0++];
     279        r5 = [p0++];
     280        r6 = [p0++];
     281        r7 = [p0++];
     282
     283        /* restore pointer registers */
     284        p3 = [p0++];
     285        p4 = [p0++];
     286        p5 = [p0++];
     287        fp = [p0++];
     288        sp = [p0++];
     289
     290        /* restore length registers */
     291        r0 = [p0++];
     292        l0 = r0;
     293        r0 = [p0++];
     294        l1 = r0;
     295        r0 = [p0++];
     296        l2 = r0;
     297        r0 = [p0++];
     298        l3 = r0;
     299
     300        /* restore rets */
     301        r0 = [p0++];
     302        rets = r0;
     303
     304        /* restore IMASK */
     305        r0 = [p0++];
     306        p1.h = HI(IMASK);
     307        p1.l = LO(IMASK);
     308        [p1] = r0;
     309
     310        rts;
     311
    215312
    216313/*
     
    227324 *
    228325 */
    229 .globl __CPU_Context_restore
     326        .globl __CPU_Context_restore
    230327__CPU_Context_restore:
    231     jump restore;
    232 
    233 
    234 
    235 .globl __ISR_Thread_Dispatch
    236 __ISR_Thread_Dispatch:
    237 
    238     .extern __Thread_Dispatch
    239     R0.l = __Thread_Dispatch;
    240     R0.h = __Thread_Dispatch;
    241  
    242     /* Puts the address of th Thread_Dispatch function on Stack
    243      * Where it will be restored to the RTI register
    244      */
    245     P0 = [FP];
    246     /* save the old reti */
    247     R1 = [P0+0xc];
    248     [P0+0xc] = R0;
    249     /*
    250      * Overwriting the RETS Register is save because Thread_Dispatch is
    251      * disabled when we are between call/link or unlink/rts
    252      */
    253     [P0+0x8] = R1;
    254  
    255     /* save old rets */
    256  
    257     rts;
    258 
    259 
    260 .globl __ISR_Handler
     328        p0 = r0;
     329        jump restore;
     330
     331
     332        .globl __ISR_Handler
     333        .extern __CPU_Interrupt_stack_high;
     334        .extern __ISR_Nest_level
     335        .extern __Thread_Dispatch_disable_level
     336        .extern __Context_Switch_necessary
     337        .extern __ISR_Signals_to_thread_executing
    261338__ISR_Handler:
    262     /* First of all check the Stackpointer and */
    263     /* switch to Scratchpad if necessary        */
    264      
    265     /* save P0 and R0 in the scratchpad */
    266     USP = P0;
    267    
    268     /* load base adress of scratchpad */
    269     P0.H = HI(SCRATCH);
    270     P0.L = LO(SCRATCH);
    271  
    272         [--SP] = ASTAT; /*  save cc flag*/
    273     /* if SP is already inside the SCRATCHPAD */
    274     CC=SP<P0 (iu)
    275     if !CC jump continue;
    276    
    277     /* set PO to top of scratchpad */   
    278     P0.h=HI(SCRATCH_TOP);
    279     P0.l=LO(SCRATCH_TOP);
    280     /*save the old SP*/
    281     [P0] = SP;
    282     /*P0 += -4;*/
    283     /*set the new Stackpointer*/
    284     SP = P0;
    285     /*restore the old PO*/
    286    
    287     /* The Stackpointer is now setup as we want */ 
    288     continue:
    289     /* restore P0 and save some context */
    290     P0 = USP;
    291     /* save some state on the isr stack (scratchpad), this enables interrupt nesting */
    292     [--SP] = RETI;
    293     [--SP] = RETS;
    294     [--SP] = ASTAT;
    295     [--SP] = FP;
    296     FP = SP;
    297     [--SP] = (R7:0, P5:0) ;
    298    
    299    
    300     /* Context is saved, now check which Instruction we were executing
    301      * If we were between a call and link or between a unlink and rts
    302      * we have to disable Thread_Dispatch because correct restore of context after
    303      * Thread_Dispatch would not be possible. */
    304    
    305     P0 = RETI;
    306     R0 = P0;
    307     R0.L = 0x0000;
    308     R1.H = 0xffa0;
    309     R1.L = 0x0000;
    310     CC = R0 == R1;
    311     if CC jump disablethreaddispatch;
    312        
    313     R0 = W[P0](Z);   
    314    
    315     /* shift 16 bits to the right (select the high nibble ) */
    316     /*R0 >>= 16;*/
    317    
    318     R3 = 0;
    319     /* Check if RETI is a LINK instruction */
    320     R1.h = HI(0x0000);
    321     R1.l = LO(0xE800);
    322     CC=R0==R1;
    323     if cc jump disablethreaddispatch;
    324    
    325     /* Check if RETI is a RTS instruction */
    326     R1.h = HI(0x0000);
    327     R1.l = LO(0x0010);
    328     CC=R0==R1;
    329     if cc jump disablethreaddispatch;
    330    
    331     jump afterthreaddispatch;
    332    
    333     disablethreaddispatch:
    334     /*  _Thread_Dispatch_disable_level++   */
    335     .extern _Thread_Dispatch_disable_level
    336     P0.H = __Thread_Dispatch_disable_level;
    337     P0.L = __Thread_Dispatch_disable_level;
    338     R0 = [P0];
    339     R0 += 1;
    340     [P0] = R0;
    341     R3 = 1;
    342    
    343     afterthreaddispatch:
    344     /* Put R3 on the stack */
    345     [--SP] = R3;
    346 
    347     /* Obtain a bitlist of the pending interrupts. */
    348     P0.H = HI(IPEND);
    349     P0.L = LO(IPEND);   
    350     R1 = [P0];
    351    
    352     /*
    353      * Search through the bit list stored in R0 to find the first enabled
    354      * bit. The offset of this bit is the index of the interrupt that is
    355      * to be handled.
    356      */
    357     R0 = -1;
    358     intloop:
    359         R0 += 1;
    360         R1 = ROT R1 by -1;
    361         if !cc jump intloop;
    362      
    363 
    364     /* pass SP as parameter to the C function */
    365     R1 = SP
    366 
    367     /* pass values by register as well as by stack */
    368     /* to comply with the c calling conventions    */
    369     [--SP] = R0;
    370     [--SP] = R1;
    371    
    372     .extern _ISR_Handler2
    373     call    _ISR_Handler2
    374 
    375     /* inc 2 to compensate the passing of arguments */
    376     R3 = [SP++];
    377     R3 = [SP++];
    378     /* check if _Thread_Dispatch_disable_level has been incremented */
    379     R3 = [SP++]
    380     CC=R3==0
    381     if cc jump dont_decrement;
    382     .extern _Thread_Dispatch_disable_level
    383     P0.H = __Thread_Dispatch_disable_level;
    384     P0.L = __Thread_Dispatch_disable_level;
    385     R0 = [P0];
    386     R0 += -1;
    387     [P0] = R0;
    388    
    389     dont_decrement:
    390    
    391     (R7:0, P5:0) = [SP++];
    392     FP =    [SP++];
    393     ASTAT = [SP++];
    394     RETS =  [SP++];
    395     RETI =  [SP++];
    396     /* Interrupts are now disabled again */
    397    
    398     /*should restore the old stack !!!*/
    399     /*if sp now points to SCRATCH_TOP */
    400    
    401     /* load base adress of scratchpad */
    402     USP = P0;
    403     P0.H = HI(SCRATCH_TOP);
    404     P0.L = LO(SCRATCH_TOP);
    405    
    406     CC=SP==P0
    407     if !cc jump restoreP0
    408     /* restore the stack */
    409     SP=[P0];
    410    
    411     restoreP0:
    412     P0 = USP;
    413     ASTAT = [SP++]; /* restore cc flag */
    414        
    415     /*now we should be on the old "user-stack" again */
    416        
    417     /* return from interrupt, will jump to adress stored in RETI */
    418     RTI;
    419 
     339        /* all interrupts are disabled at this point */
     340        /* the following few items are pushed onto the task stack for at
     341           most one interrupt; nested interrupts will be using the interrupt
     342           stack for everything. */
     343        [--sp] = astat;
     344        [--sp] = p1;
     345        [--sp] = p0;
     346        [--sp] = r1;
     347        [--sp] = r0;
     348        p0.h = __ISR_Nest_level;
     349        p0.l = __ISR_Nest_level;
     350        r0 = [p0];
     351        r0 += 1;
     352        [p0] = r0;
     353        cc = r0 <= 1 (iu);
     354        if !cc jump noStackSwitch;
     355        /* setup interrupt stack */
     356        r0 = sp;
     357        p0.h = __CPU_Interrupt_stack_high;
     358        p0.l = __CPU_Interrupt_stack_high;
     359        sp = [p0];
     360        [--sp] = r0;
     361noStackSwitch:
     362        /* disable thread dispatch */
     363        p0.h = __Thread_Dispatch_disable_level;
     364        p0.l = __Thread_Dispatch_disable_level;
     365        r0 = [p0];
     366        r0 += 1;
     367        [p0] = r0;
     368
     369        [--sp] = reti;  /* interrupts are now enabled */
     370
     371        /* figure out what vector we are */
     372        p0.h = HI(IPEND);
     373        p0.l = LO(IPEND);
     374        r1 = [p0];
     375        /* we should only get here for events that require RTI to return */
     376        r1 = r1 >> 5;
     377        r0 = 4;
     378        /* at least one bit must be set, so this loop will exit */
     379vectorIDLoop:
     380        r0 += 1;
     381        r1 = rot r1 by -1;
     382        if !cc jump vectorIDLoop;
     383
     384        [--sp] = r2;
     385        p0.h = __ISR_Vector_table;
     386        p0.l = __ISR_Vector_table;
     387        r2 = [p0];
     388        r1 = r0 << 2;
     389        r1 = r1 + r2;
     390        p0 = r1;
     391        p0 = [p0];
     392        cc = p0 == 0;
     393        if cc jump noHandler;
     394
     395        /* r2, r0, r1, p0, p1, astat are already saved */
     396        [--sp] = a1.x;
     397        [--sp] = a1.w;
     398        [--sp] = a0.x;
     399        [--sp] = a0.w;
     400        [--sp] = r3;
     401        [--sp] = p3;
     402        [--sp] = p2;
     403        [--sp] = lt1;
     404        [--sp] = lt0;
     405        [--sp] = lc1;
     406        [--sp] = lc0;
     407        [--sp] = lb1;
     408        [--sp] = lb0;
     409        [--sp] = i3;
     410        [--sp] = i2;
     411        [--sp] = i1;
     412        [--sp] = i0;
     413        [--sp] = m3;
     414        [--sp] = m2;
     415        [--sp] = m1;
     416        [--sp] = m0;
     417        [--sp] = l3;
     418        [--sp] = l2;
     419        [--sp] = l1;
     420        [--sp] = l0;
     421        [--sp] = b3;
     422        [--sp] = b2;
     423        [--sp] = b1;
     424        [--sp] = b0;
     425        [--sp] = rets;
     426        r1 = fp; /* is this really what should be passed here? */
     427        /* call user isr; r0 = vector number, r1 = frame pointer */
     428        sp += -12; /* bizarre abi... */
     429        call (p0);
     430        sp += 12;
     431        rets = [sp++];
     432        b0 = [sp++];
     433        b1 = [sp++];
     434        b2 = [sp++];
     435        b3 = [sp++];
     436        l0 = [sp++];
     437        l1 = [sp++];
     438        l2 = [sp++];
     439        l3 = [sp++];
     440        m0 = [sp++];
     441        m1 = [sp++];
     442        m2 = [sp++];
     443        m3 = [sp++];
     444        i0 = [sp++];
     445        i1 = [sp++];
     446        i2 = [sp++];
     447        i3 = [sp++];
     448        lb0 = [sp++];
     449        lb1 = [sp++];
     450        lc0 = [sp++];
     451        lc1 = [sp++];
     452        lt0 = [sp++];
     453        lt1 = [sp++];
     454        p2 = [sp++];
     455        p3 = [sp++];
     456        r3 = [sp++];
     457        a0.w = [sp++];
     458        a0.x = [sp++];
     459        a1.w = [sp++];
     460        a1.x = [sp++];
     461
     462noHandler:
     463        r2 = [sp++];
     464        /* this disables interrupts again */
     465        reti = [sp++];
     466
     467        p0.h = __ISR_Nest_level;
     468        p0.l = __ISR_Nest_level;
     469        r0 = [p0];
     470        r0 += -1;
     471        [p0] = r0;
     472        cc = r0 == 0;
     473        if !cc jump noStackRestore;
     474        sp = [sp];
     475noStackRestore:
     476
     477        /* check this stuff to insure context_switch_necessary and
     478           isr_signals_to_thread_executing are being handled appropriately. */
     479        p0.h = __Thread_Dispatch_disable_level;
     480        p0.l = __Thread_Dispatch_disable_level;
     481        r0 = [p0];
     482        r0 += -1;
     483        [p0] = r0;
     484        cc = r0 == 0;
     485        if !cc jump noDispatch
     486
     487        /* do thread dispatch if necessary */
     488        p0.h = __Context_Switch_necessary;
     489        p0.l = __Context_Switch_necessary;
     490        r0 = [p0];
     491        cc = r0 == 0;
     492        p0.h = __ISR_Signals_to_thread_executing;
     493        p0.l = __ISR_Signals_to_thread_executing;
     494        if !cc jump doDispatch
     495        r0 = [p0];
     496        cc = r0 == 0;
     497        if cc jump noDispatch
     498doDispatch:
     499        r0 = 0;
     500        [p0] = r0;
     501        raise 15;
     502noDispatch:
     503        r0 = [sp++];
     504        r1 = [sp++];
     505        p0 = [sp++];
     506        p1 = [sp++];
     507        astat = [sp++];
     508        rti
     509
     510
     511/* the approach here is for the main interrupt handler, when a dispatch is
     512   wanted, to do a "raise 15".  when the main interrupt handler does its
     513   "rti", the "raise 15" takes effect and we end up here.  we can now
     514   safely call _Thread_Dispatch, and do an "rti" to get back to the
     515   original interrupted function.  this does require self-nesting to be
     516   enabled; the maximum nest depth is the number of tasks. */
     517        .global __ISR15_Handler
     518        .extern __Thread_Dispatch
     519__ISR15_Handler:
     520        [--sp] = reti;
     521        [--sp] = rets;
     522        [--sp] = astat;
     523        [--sp] = a1.x;
     524        [--sp] = a1.w;
     525        [--sp] = a0.x;
     526        [--sp] = a0.w;
     527        [--sp] = r3;
     528        [--sp] = r2;
     529        [--sp] = r1;
     530        [--sp] = r0;
     531        [--sp] = p3;
     532        [--sp] = p2;
     533        [--sp] = p1;
     534        [--sp] = p0;
     535        [--sp] = lt1;
     536        [--sp] = lt0;
     537        [--sp] = lc1;
     538        [--sp] = lc0;
     539        [--sp] = lb1;
     540        [--sp] = lb0;
     541        [--sp] = i3;
     542        [--sp] = i2;
     543        [--sp] = i1;
     544        [--sp] = i0;
     545        [--sp] = m3;
     546        [--sp] = m2;
     547        [--sp] = m1;
     548        [--sp] = m0;
     549        [--sp] = l3;
     550        [--sp] = l2;
     551        [--sp] = l1;
     552        [--sp] = l0;
     553        [--sp] = b3;
     554        [--sp] = b2;
     555        [--sp] = b1;
     556        [--sp] = b0;
     557        sp += -12; /* bizarre abi... */
     558        call __Thread_Dispatch;
     559        sp += 12;
     560        b0 = [sp++];
     561        b1 = [sp++];
     562        b2 = [sp++];
     563        b3 = [sp++];
     564        l0 = [sp++];
     565        l1 = [sp++];
     566        l2 = [sp++];
     567        l3 = [sp++];
     568        m0 = [sp++];
     569        m1 = [sp++];
     570        m2 = [sp++];
     571        m3 = [sp++];
     572        i0 = [sp++];
     573        i1 = [sp++];
     574        i2 = [sp++];
     575        i3 = [sp++];
     576        lb0 = [sp++];
     577        lb1 = [sp++];
     578        lc0 = [sp++];
     579        lc1 = [sp++];
     580        lt0 = [sp++];
     581        lt1 = [sp++];
     582        p0 = [sp++];
     583        p1 = [sp++];
     584        p2 = [sp++];
     585        p3 = [sp++];
     586        r0 = [sp++];
     587        r1 = [sp++];
     588        r2 = [sp++];
     589        r3 = [sp++];
     590        a0.w = [sp++];
     591        a0.x = [sp++];
     592        a1.w = [sp++];
     593        a1.x = [sp++];
     594        astat = [sp++];
     595        rets = [sp++];
     596        reti = [sp++];
     597        rti;
     598
  • cpukit/score/cpu/bfin/irq.c

    rb281e42 r4daebbd  
    1212 */
    1313 
     14
     15#if 0 /* this file no longer used */
    1416 
    1517#include <rtems/system.h>
     
    105107  }
    106108}
     109
     110#endif /* 0 */
     111
  • cpukit/score/cpu/bfin/rtems/score/cpu.h

    rb281e42 r4daebbd  
    106106 *  XXX document implementation including references if appropriate
    107107 */
    108 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
     108#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
     109
     110/*
     111 *  Does the CPU follow the simple vectored interrupt model?
     112 *
     113 *  If TRUE, then RTEMS allocates the vector table it internally manages.
     114 *  If FALSE, then the BSP is assumed to allocate and manage the vector
     115 *  table
     116 *
     117 *  BFIN Specific Information:
     118 *
     119 *  XXX document implementation including references if appropriate
     120 */
     121#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
    109122
    110123/*
     
    153166 *  XXX document implementation including references if appropriate
    154167 */
    155 #define CPU_ALLOCATE_INTERRUPT_STACK FALSE
     168#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
    156169
    157170/**
     
    306319 *  XXX document implementation including references if appropriate
    307320 */
    308 #define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
     321#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
    309322
    310323/**
     
    454467 *  to another.
    455468 */
     469
     470/* make sure this stays in sync with the assembly function
     471   __CPU_Context_switch in cpu_asm.S  */
    456472typedef struct {
    457     /* we are saving all registers, maybe we should not */
    458    
    459     uint32_t   register_r0;
    460     uint32_t   register_r1;
    461     uint32_t   register_r2;
    462     uint32_t   register_r3;
    463473    uint32_t   register_r4;
    464474    uint32_t   register_r5;
    465475    uint32_t   register_r6;
    466476    uint32_t   register_r7;
    467     uint32_t   register_p0;
    468     uint32_t   register_p1;
    469     uint32_t   register_p2;
     477
    470478    uint32_t   register_p3;
    471479    uint32_t   register_p4;
     
    474482    uint32_t   register_sp;
    475483   
    476     uint32_t   register_i0;                         
    477     uint32_t   register_i1;
    478     uint32_t   register_i2;
    479     uint32_t   register_i3;
    480    
    481     uint32_t   register_m0;
    482     uint32_t   register_m1;
    483     uint32_t   register_m2;
    484     uint32_t   register_m3;
    485 
    486     uint32_t   register_b0;
    487     uint32_t   register_b1;
    488     uint32_t   register_b2;
    489     uint32_t   register_b3;
    490 
    491484    uint32_t   register_l0;
    492485    uint32_t   register_l1;
     
    494487    uint32_t   register_l3;   
    495488   
    496     uint32_t   register_a0dotx;
    497     uint32_t   register_a0dotw;
    498     uint32_t   register_a1dotx;
    499     uint32_t   register_a1dotw;
    500     uint32_t   register_astat;
    501489    uint32_t   register_rets;
    502     uint32_t   register_lc0;
    503     uint32_t   register_lt0;
    504     uint32_t   register_lb0;
    505     uint32_t   register_lc1;
    506     uint32_t   register_lt1;
    507     uint32_t   register_lb1;
    508  
    509   /*BFIN_CYCLES_REGNUM,
    510   BFIN_CYCLES2_REGNUM, */
    511  
    512     uint32_t   register_usp;
    513     uint32_t   register_seqstat;
    514     uint32_t   register_syscfg;
    515     uint32_t   register_reti;
    516     uint32_t   register_retx;
    517     uint32_t   register_retn;
    518     uint32_t   register_rete;
    519 
    520     uint32_t   register_pc;
    521 
    522   /*
    523   Pseudo Registers
    524   BFIN_PC_REGNUM,
    525   BFIN_CC_REGNUM,
    526   BFIN_EXTRA1,       Address of .text section.
    527   BFIN_EXTRA2,       Address of .data section.
    528   BFIN_EXTRA3,       Address of .bss section. 
    529 
    530   BFIN_FDPIC_EXEC_REGNUM,
    531   BFIN_FDPIC_INTERP_REGNUM,
    532 
    533   MMRs
    534   BFIN_IPEND_REGNUM,
    535 
    536   LAST ENTRY SHOULD NOT BE CHANGED.
    537   BFIN_NUM_REGS      The number of all registers.
    538   */ 
     490
     491    uint32_t   imask; 
    539492} Context_Control;
    540493
     
    625578 *  XXX document implementation including references if appropriate
    626579 */
    627 SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
     580/* SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();*/
    628581
    629582/*
     
    791744#define _CPU_ISR_Disable( _level ) \
    792745  {                                     \
    793        asm volatile ("cli %0 \n"       \
    794                 : "=d" (_level) );     \
    795                                         \
     746       asm volatile ("cli %0 \n" : "=d" (_level) );     \
    796747  }
    797748 
     
    809760 *  XXX document implementation including references if appropriate
    810761 */
    811 #define _CPU_ISR_Enable( _level )  \
    812   {                                    \
    813     asm volatile ("STI %0 \n"                  \
    814                    : : "d" (_level) );         \
     762#define _CPU_ISR_Enable( _level ) { \
     763    __asm__ __volatile__ ("sti %0 \n" : : "d" (_level) );   \
    815764  }
    816765
     
    828777 *  XXX document implementation including references if appropriate
    829778 */
    830 #define _CPU_ISR_Flash( _level )
    831 /*  { \
    832     asm volatile ("cli %0;\n"          \
    833                   "ssync; \n"           \
    834                   "sti %1; \n"          \
    835                    : "=r" (_level) : "0"(_level) );  \
    836   }*/
     779#define _CPU_ISR_Flash( _level ) { \
     780    __asm__ __volatile__ ("sti %0; ssync; sti %1" \
     781                          : : "d"(0xffff), "d"(_level)); \
     782  }
    837783
    838784/**
     
    855801#define _CPU_ISR_Set_level( _new_level ) \
    856802  { \
    857     if ( _new_level ) asm volatile ( "cli R0;" : : : "R0" ); \
    858     else              asm volatile ( "R0.l = 0xFFFF;\n"\
    859                                      "sti R0;" : : : "R0" ); \
     803    __asm__ __volatile__ ( "sti %0" : : "d"(_new_level ? 0 : 0xffff) ); \
    860804  }
    861805
     
    1002946                    R1 = %0; \
    1003947                    _halt: \
     948                    idle; \
    1004949                    jump _halt;"\
    1005                     : "=r" (_error) ); \
     950                    : : "r" (_error) ); \
    1006951  }
    1007952
  • cpukit/score/cpu/bfin/rtems/score/cpu_asm.h

    rb281e42 r4daebbd  
    2121#define _RTEMS_SCORE_CPU_ASM_H
    2222
    23 /* offsets for the registers in the thread context */
    24 #define R0_OFFSET     0
    25 #define R1_OFFSET     4
    26 #define R2_OFFSET     8
    27 #define R3_OFFSET     12
    28 #define R4_OFFSET     16
    29 #define R5_OFFSET     20
    30 #define R6_OFFSET     24
    31 #define R7_OFFSET     28
    32 #define P0_OFFSET     32
    33 #define P1_OFFSET     36
    34 #define P2_OFFSET     40
    35 #define P3_OFFSET     44
    36 #define P4_OFFSET     48
    37 #define P5_OFFSET     52
    38 #define FP_OFFSET     56
    39 #define SP_OFFSET     60
    40 
    41 #define I0_OFFSET     64
    42 #define I1_OFFSET     68
    43 #define I2_OFFSET     72
    44 #define I3_OFFSET     76
    45 
    46 #define M0_OFFSET     80
    47 #define M1_OFFSET     84
    48 #define M2_OFFSET     88
    49 #define M3_OFFSET     92
    50 
    51 #define B0_OFFSET     96
    52 #define B1_OFFSET     100
    53 #define B2_OFFSET     104
    54 #define B3_OFFSET     108
    55 
    56 #define L0_OFFSET     112
    57 #define L1_OFFSET     116
    58 #define L2_OFFSET     120
    59 #define L3_OFFSET     124
    60 
    61 #define A0X_OFFSET     128
    62 #define A0W_OFFSET     132
    63 #define A1X_OFFSET     136
    64 #define A1W_OFFSET     140
    65 
    66 #define ASTAT_OFFSET   144
    67 #define RETS_OFFSET    148
    68 #define LC0_OFFSET     152
    69 #define LT0_OFFSET     156
    70 
    71 #define LB0_OFFSET     160
    72 #define LC1_OFFSET     164
    73 #define LT1_OFFSET     168
    74 #define LB1_OFFSET     172
    75 
    76 #define USP_OFFSET     174
    77 #define SEQSTAT_OFFSET 178
    78 #define SYSCFG_OFFSET  182
    79 #define RETI_OFFSET    184
    80 
    81 #define RETX_OFFSET    188
    82 #define RETN_OFFSET    192
    83 #define RETE_OFFSET    296
    84 
    85 #define PC_OFFSET      200
    8623
    8724
  • cpukit/score/include/rtems/score/coremutex.h

    rb281e42 r4daebbd  
    114114   *  than the ceiling priority attempted to lock this mutex.
    115115   */
    116   CORE_MUTEX_STATUS_CEILING_VIOLATED,
     116  CORE_MUTEX_STATUS_CEILING_VIOLATED
    117117
    118118}   CORE_mutex_Status;
  • cpukit/score/include/rtems/score/object.h

    rb281e42 r4daebbd  
    292292 */
    293293typedef enum {
    294   OBJECTS_LOCAL  = 0,         /* object is local */
    295   OBJECTS_ERROR  = 1,         /* id was invalid */
    296294#if defined(RTEMS_MULTIPROCESSING)
    297295  OBJECTS_REMOTE = 2,         /* object is remote */
    298296#endif
     297  OBJECTS_LOCAL  = 0,         /* object is local */
     298  OBJECTS_ERROR  = 1          /* id was invalid */
    299299} Objects_Locations;
    300300
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