Changeset 4d6b3b6 in rtems


Ignore:
Timestamp:
Jan 12, 2001, 1:28:27 PM (21 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
d9f6165
Parents:
3e7e859
Message:

2001-01-12 Joel Sherrill <joel@…>

  • include/bsp.h, timer/timer.c: Updated so timer appears to work and support tm27. I would prefer to time a software interrupt rather than an use an extra timer though.
Location:
c/src/lib/libbsp/mips/jmr3904
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/mips/jmr3904/ChangeLog

    r3e7e859 r4d6b3b6  
     12001-01-12      Joel Sherrill <joel@OARcorp.com>
     2
     3        * include/bsp.h, timer/timer.c: Updated so timer appears to
     4        work and support tm27.  I would prefer to time a software
     5        interrupt rather than an use an extra timer though.
     6
    172001-01-09      Joel Sherrill <joel@OARcorp.com>
    28
  • c/src/lib/libbsp/mips/jmr3904/include/bsp.h

    r3e7e859 r4d6b3b6  
    4545 */
    4646
    47 #define MUST_WAIT_FOR_INTERRUPT 0
     47#define MUST_WAIT_FOR_INTERRUPT 1
    4848
     49#if 0
    4950#define Install_tm27_vector( handler ) \
    5051    (void) set_vector( handler, TX3904_IRQ_SOFTWARE_1, 1 ); \
    5152
    5253#define Cause_tm27_intr() \
     54    asm volatile ( "syscall 0x01" : : );
     55
     56#define CLOCK_VECTOR TX3904_IRQ_TMR0
    5357
    5458#define Clear_tm27_intr() 
    5559
    5660#define Lower_tm27_intr()
     61#else
     62#define Install_tm27_vector( handler ) \
     63    (void) set_vector( handler, TX3904_IRQ_TMR0, 1 ); \
     64
     65#define Cause_tm27_intr() \
     66  do { \
     67    unsigned32 _clicks = 20; \
     68    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \
     69    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CPRA, _clicks ); \
     70    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR, 0x00 ); \
     71    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x8001 ); \
     72    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TCR,   0xC0 ); \
     73    *((volatile unsigned32 *) 0xFFFFC01C) = 0x00000700; \
     74  } while(0)
     75
     76#define Clear_tm27_intr() \
     77  TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TCR,   0x03 );
     78
     79#define Lower_tm27_intr() \
     80  mips_enable_in_interrupt_mask( 0xff01 );
     81
     82#endif
    5783
    5884/* Constants */
     
    78104void bsp_cleanup( void );
    79105
    80 rtems_isr_entry set_vector( rtems_isr_entry, unsigned int, unsigned int );
     106rtems_isr_entry set_vector(
     107  rtems_isr_entry, rtems_vector_number, int );
    81108
    82109#ifdef __cplusplus
  • c/src/lib/libbsp/mips/jmr3904/timer/timer.c

    r3e7e859 r4d6b3b6  
    2727   *  but if it ever does generate an interrupt, we will simply fault.
    2828   *
    29    *  NOTE:  This is identical to the clock driver initialization
     29   *  NOTE:  This is similar to the clock driver initialization
    3030   *         with the exception that the divider is disabled and
    3131   *         the compare register is set to the maximum value.
    3232   */
    3333
    34   TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 );
    35   TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TRR, 0x0 );
    36   TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CPRA, 0xFFFFFFFF );
    37   TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR, 0x00 );
    38   TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x8001 );
    39   TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TCR,   0xc0 );
    40   *((volatile unsigned32 *) 0xFFFFC01C) = 0x00000700;
     34  TX3904_TIMER_WRITE( TX3904_TIMER1_BASE, TX3904_TIMER_CCDR, 0x3 );
     35  TX3904_TIMER_WRITE( TX3904_TIMER1_BASE, TX3904_TIMER_TRR, 0x0 );
     36  TX3904_TIMER_WRITE( TX3904_TIMER1_BASE, TX3904_TIMER_CPRA, 0xFFFFFFFF );
     37  TX3904_TIMER_WRITE( TX3904_TIMER1_BASE, TX3904_TIMER_TISR, 0x00 );
     38  TX3904_TIMER_WRITE( TX3904_TIMER1_BASE, TX3904_TIMER_ITMR, 0x8001 );
     39  TX3904_TIMER_WRITE( TX3904_TIMER1_BASE, TX3904_TIMER_TCR,   0x20 );
     40  TX3904_TIMER_WRITE( TX3904_TIMER1_BASE, TX3904_TIMER_TCR,   0xe0 );
    4141}
    4242
    43 #define AVG_OVERHEAD      0  /* It typically takes 24 instructions */
     43#define AVG_OVERHEAD      0  /* It typically takes N instructions */
    4444                             /*     to start/stop the timer. */
    4545#define LEAST_VALID       1  /* Don't trust a value lower than this */
     
    5050  rtems_unsigned32  total;
    5151
    52   TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TCR,   0x03 );
    53   total = TX3904_TIMER_READ( TX3904_TIMER0_BASE, TX3904_TIMER_TRR );
     52  TX3904_TIMER_WRITE( TX3904_TIMER1_BASE, TX3904_TIMER_TCR,   0x03 );
     53  total = TX3904_TIMER_READ( TX3904_TIMER1_BASE, TX3904_TIMER_TRR );
    5454
    5555  if ( Timer_driver_Find_average_overhead == 1 )
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