Changeset 4cf93658 in rtems for bsps/or1k


Ignore:
Timestamp:
Jan 27, 2018, 1:37:51 PM (3 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
5, master
Children:
05015dc1
Parents:
d8d6a08
git-author:
Sebastian Huber <sebastian.huber@…> (01/27/18 13:37:51)
git-committer:
Sebastian Huber <sebastian.huber@…> (01/31/18 11:49:09)
Message:

bsps: Rework cache manager implementation

The previous cache manager support used a single souce file
(cache_manager.c) which included an implementation header (cache_.h).
This required the use of specialized include paths to find the right
header file. Change this to include a generic implementation header
(cacheimpl.h) in specialized source files.

Use the following directories and files:

  • bsps/shared/cache
  • bsps/@RTEMS_CPU@/shared/cache
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c

Update #3285.

Location:
bsps/or1k
Files:
1 deleted
1 edited
1 moved

Legend:

Unmodified
Added
Removed
  • bsps/or1k/headers.am

    rd8d6a08 r4cf93658  
    33include_bspdir = $(includedir)/bsp
    44include_bsp_HEADERS =
    5 include_bsp_HEADERS += ../../../../../bsps/or1k/include/bsp/cache_.h
    65include_bsp_HEADERS += ../../../../../bsps/or1k/include/bsp/linker-symbols.h
  • bsps/or1k/shared/cache/cache.c

    rd8d6a08 r4cf93658  
    2020#include <rtems/score/or1k-utility.h>
    2121#include <rtems/score/percpu.h>
    22 #include "cache_.h"
     22
     23#define CPU_DATA_CACHE_ALIGNMENT        32
     24#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
     25
     26#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS 1
     27#define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS 1
     28
     29static inline size_t
     30_CPU_cache_get_data_cache_size( const uint32_t level )
     31{
     32  return (level == 0 || level == 1)? 8192 : 0;
     33}
     34
     35static inline size_t
     36_CPU_cache_get_instruction_cache_size( const uint32_t level )
     37{
     38  return (level == 0 || level == 1)? 8192 : 0;
     39}
    2340
    2441static inline void _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr)
     
    8198/* Implement RTEMS cache manager functions */
    8299
    83 void _CPU_cache_flush_1_data_line(const void *d_addr)
     100static void _CPU_cache_flush_1_data_line(const void *d_addr)
    84101{
    85102  ISR_Level level;
     
    94111}
    95112
    96 void _CPU_cache_invalidate_1_data_line(const void *d_addr)
     113static void _CPU_cache_invalidate_1_data_line(const void *d_addr)
    97114{
    98115  ISR_Level level;
     
    105122}
    106123
    107 void _CPU_cache_freeze_data(void)
     124static void _CPU_cache_freeze_data(void)
    108125{
    109126  /* Do nothing */
    110127}
    111128
    112 void _CPU_cache_unfreeze_data(void)
     129static void _CPU_cache_unfreeze_data(void)
    113130{
    114131  /* Do nothing */
    115132}
    116133
    117 void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
     134static void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
    118135{
    119136  ISR_Level level;
     
    126143}
    127144
    128 void _CPU_cache_freeze_instruction(void)
     145static void _CPU_cache_freeze_instruction(void)
    129146{
    130147  /* Do nothing */
    131148}
    132149
    133 void _CPU_cache_unfreeze_instruction(void)
     150static void _CPU_cache_unfreeze_instruction(void)
    134151{
    135152  /* Do nothing */
    136153}
    137154
    138 void _CPU_cache_flush_entire_data(void)
     155static void _CPU_cache_flush_entire_data(void)
    139156{
    140157  size_t addr;
     
    155172}
    156173
    157 void _CPU_cache_invalidate_entire_data(void)
     174static void _CPU_cache_invalidate_entire_data(void)
    158175{
    159176  size_t addr;
     
    174191}
    175192
    176 void _CPU_cache_invalidate_entire_instruction(void)
     193static void _CPU_cache_invalidate_entire_instruction(void)
    177194{
    178195  size_t addr;
     
    207224 */
    208225
    209 void _CPU_cache_flush_data_range(const void *d_addr, size_t n_bytes)
     226static void _CPU_cache_flush_data_range(const void *d_addr, size_t n_bytes)
    210227{
    211228  const void * final_address;
     
    244261}
    245262
    246 void _CPU_cache_invalidate_data_range(const void *d_addr, size_t n_bytes)
     263static void _CPU_cache_invalidate_data_range(const void *d_addr, size_t n_bytes)
    247264{
    248265  const void * final_address;
     
    281298}
    282299
    283 void _CPU_cache_invalidate_instruction_range(const void *i_addr, size_t n_bytes)
     300static void _CPU_cache_invalidate_instruction_range(const void *i_addr, size_t n_bytes)
    284301{
    285302  const void * final_address;
     
    318335}
    319336
    320 void _CPU_cache_enable_data(void)
     337static void _CPU_cache_enable_data(void)
    321338{
    322339  uint32_t sr;
     
    331348}
    332349
    333 void _CPU_cache_disable_data(void)
     350static void _CPU_cache_disable_data(void)
    334351{
    335352  uint32_t sr;
     
    344361}
    345362
    346 void _CPU_cache_enable_instruction(void)
     363static void _CPU_cache_enable_instruction(void)
    347364{
    348365  uint32_t sr;
     
    357374}
    358375
    359 void _CPU_cache_disable_instruction(void)
     376static void _CPU_cache_disable_instruction(void)
    360377{
    361378  uint32_t sr;
     
    369386  _ISR_Local_enable(level);
    370387}
     388
     389#include "../../../shared/cache/cacheimpl.h"
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