Ignore:
Timestamp:
Jan 27, 2018, 1:37:51 PM (3 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
5, master
Children:
05015dc1
Parents:
d8d6a08
git-author:
Sebastian Huber <sebastian.huber@…> (01/27/18 13:37:51)
git-committer:
Sebastian Huber <sebastian.huber@…> (01/31/18 11:49:09)
Message:

bsps: Rework cache manager implementation

The previous cache manager support used a single souce file
(cache_manager.c) which included an implementation header (cache_.h).
This required the use of specialized include paths to find the right
header file. Change this to include a generic implementation header
(cacheimpl.h) in specialized source files.

Use the following directories and files:

  • bsps/shared/cache
  • bsps/@RTEMS_CPU@/shared/cache
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c

Update #3285.

File:
1 moved

Legend:

Unmodified
Added
Removed
  • bsps/m68k/shared/cache/cache-mcf5282.c

    rd8d6a08 r4cf93658  
    77#include <rtems.h>
    88#include <mcf5282/mcf5282.h>   /* internal MCF5282 modules */
    9 #include "cache_.h"
     9#include "cache.h"
    1010
    1111/*
     
    4141 * Cannot be frozen
    4242 */
    43 void _CPU_cache_freeze_data(void) {}
    44 void _CPU_cache_unfreeze_data(void) {}
    45 void _CPU_cache_freeze_instruction(void) {}
    46 void _CPU_cache_unfreeze_instruction(void) {}
     43static void _CPU_cache_freeze_data(void) {}
     44static void _CPU_cache_unfreeze_data(void) {}
     45static void _CPU_cache_freeze_instruction(void) {}
     46static void _CPU_cache_unfreeze_instruction(void) {}
    4747
    4848/*
    4949 * Write-through data cache -- flushes are unnecessary
    5050 */
    51 void _CPU_cache_flush_1_data_line(const void *d_addr) {}
    52 void _CPU_cache_flush_entire_data(void) {}
     51static void _CPU_cache_flush_1_data_line(const void *d_addr) {}
     52static void _CPU_cache_flush_entire_data(void) {}
    5353
    54 void _CPU_cache_enable_instruction(void)
     54static void _CPU_cache_enable_instruction(void)
    5555{
    5656  rtems_interrupt_level level;
     
    6363}
    6464
    65 void _CPU_cache_disable_instruction(void)
     65static void _CPU_cache_disable_instruction(void)
    6666{
    6767  rtems_interrupt_level level;
     
    7373}
    7474
    75 void _CPU_cache_invalidate_entire_instruction(void)
     75static void _CPU_cache_invalidate_entire_instruction(void)
    7676{
    7777  m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
     
    7979}
    8080
    81 void _CPU_cache_invalidate_1_instruction_line(const void *addr)
     81static void _CPU_cache_invalidate_1_instruction_line(const void *addr)
    8282{
    8383  /*
     
    8888}
    8989
    90 void _CPU_cache_enable_data(void)
     90static void _CPU_cache_enable_data(void)
    9191{
    9292  rtems_interrupt_level level;
     
    9898}
    9999
    100 void _CPU_cache_disable_data(void)
     100static void _CPU_cache_disable_data(void)
    101101{
    102102  rtems_interrupt_level level;
     
    108108}
    109109
    110 void _CPU_cache_invalidate_entire_data(void)
     110static void _CPU_cache_invalidate_entire_data(void)
    111111{
    112112  m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
    113113}
    114114
    115 void _CPU_cache_invalidate_1_data_line(const void *addr)
     115static void _CPU_cache_invalidate_1_data_line(const void *addr)
    116116{
    117117  /*
     
    121121  __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
    122122}
     123
     124#include "../../../shared/cache/cacheimpl.h"
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