Ignore:
Timestamp:
Jan 27, 2018, 1:37:51 PM (3 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
5, master
Children:
05015dc1
Parents:
d8d6a08
git-author:
Sebastian Huber <sebastian.huber@…> (01/27/18 13:37:51)
git-committer:
Sebastian Huber <sebastian.huber@…> (01/31/18 11:49:09)
Message:

bsps: Rework cache manager implementation

The previous cache manager support used a single souce file
(cache_manager.c) which included an implementation header (cache_.h).
This required the use of specialized include paths to find the right
header file. Change this to include a generic implementation header
(cacheimpl.h) in specialized source files.

Use the following directories and files:

  • bsps/shared/cache
  • bsps/@RTEMS_CPU@/shared/cache
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c

Update #3285.

File:
1 moved

Legend:

Unmodified
Added
Removed
  • bsps/m68k/shared/cache/cache-mcf5235.c

    rd8d6a08 r4cf93658  
    1010#include <rtems.h>
    1111#include <mcf5235/mcf5235.h>
    12 #include "cache_.h"
     12#include "cache.h"
    1313
    1414/*
     
    2020 * Cannot be frozen
    2121 */
    22 void _CPU_cache_freeze_data(void) {}
    23 void _CPU_cache_unfreeze_data(void) {}
    24 void _CPU_cache_freeze_instruction(void) {}
    25 void _CPU_cache_unfreeze_instruction(void) {}
     22static void _CPU_cache_freeze_data(void) {}
     23static void _CPU_cache_unfreeze_data(void) {}
     24static void _CPU_cache_freeze_instruction(void) {}
     25static void _CPU_cache_unfreeze_instruction(void) {}
    2626
    2727/*
    2828 * Write-through data cache -- flushes are unnecessary
    2929 */
    30 void _CPU_cache_flush_1_data_line(const void *d_addr) {}
    31 void _CPU_cache_flush_entire_data(void) {}
     30static void _CPU_cache_flush_1_data_line(const void *d_addr) {}
     31static void _CPU_cache_flush_entire_data(void) {}
    3232
    33 void _CPU_cache_enable_instruction(void)
     33static void _CPU_cache_enable_instruction(void)
    3434{
    3535    rtems_interrupt_level level;
     
    4141}
    4242
    43 void _CPU_cache_disable_instruction(void)
     43static void _CPU_cache_disable_instruction(void)
    4444{
    4545    rtems_interrupt_level level;
     
    5151}
    5252
    53 void _CPU_cache_invalidate_entire_instruction(void)
     53static void _CPU_cache_invalidate_entire_instruction(void)
    5454{
    5555    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
    5656}
    5757
    58 void _CPU_cache_invalidate_1_instruction_line(const void *addr)
     58static void _CPU_cache_invalidate_1_instruction_line(const void *addr)
    5959{
    6060    /*
     
    6565}
    6666
    67 void _CPU_cache_enable_data(void)
     67static void _CPU_cache_enable_data(void)
    6868{
    6969    rtems_interrupt_level level;
     
    7575}
    7676
    77 void _CPU_cache_disable_data(void)
     77static void _CPU_cache_disable_data(void)
    7878{
    7979    rtems_interrupt_level level;
     
    8585}
    8686
    87 void _CPU_cache_invalidate_entire_data(void)
     87static void _CPU_cache_invalidate_entire_data(void)
    8888{
    8989    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
    9090}
    9191
    92 void _CPU_cache_invalidate_1_data_line(const void *addr)
     92static void _CPU_cache_invalidate_1_data_line(const void *addr)
    9393{
    9494    /*
     
    9898    __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
    9999}
     100
     101#include "../../../shared/cache/cacheimpl.h"
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