Changeset 4cf93658 in rtems for bsps/m68k/shared


Ignore:
Timestamp:
Jan 27, 2018, 1:37:51 PM (3 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
5, master
Children:
05015dc1
Parents:
d8d6a08
git-author:
Sebastian Huber <sebastian.huber@…> (01/27/18 13:37:51)
git-committer:
Sebastian Huber <sebastian.huber@…> (01/31/18 11:49:09)
Message:

bsps: Rework cache manager implementation

The previous cache manager support used a single souce file
(cache_manager.c) which included an implementation header (cache_.h).
This required the use of specialized include paths to find the right
header file. Change this to include a generic implementation header
(cacheimpl.h) in specialized source files.

Use the following directories and files:

  • bsps/shared/cache
  • bsps/@RTEMS_CPU@/shared/cache
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c

Update #3285.

Location:
bsps/m68k/shared/cache
Files:
3 added
4 moved

Legend:

Unmodified
Added
Removed
  • bsps/m68k/shared/cache/cache-mcf5235.c

    rd8d6a08 r4cf93658  
    1010#include <rtems.h>
    1111#include <mcf5235/mcf5235.h>
    12 #include "cache_.h"
     12#include "cache.h"
    1313
    1414/*
     
    2020 * Cannot be frozen
    2121 */
    22 void _CPU_cache_freeze_data(void) {}
    23 void _CPU_cache_unfreeze_data(void) {}
    24 void _CPU_cache_freeze_instruction(void) {}
    25 void _CPU_cache_unfreeze_instruction(void) {}
     22static void _CPU_cache_freeze_data(void) {}
     23static void _CPU_cache_unfreeze_data(void) {}
     24static void _CPU_cache_freeze_instruction(void) {}
     25static void _CPU_cache_unfreeze_instruction(void) {}
    2626
    2727/*
    2828 * Write-through data cache -- flushes are unnecessary
    2929 */
    30 void _CPU_cache_flush_1_data_line(const void *d_addr) {}
    31 void _CPU_cache_flush_entire_data(void) {}
     30static void _CPU_cache_flush_1_data_line(const void *d_addr) {}
     31static void _CPU_cache_flush_entire_data(void) {}
    3232
    33 void _CPU_cache_enable_instruction(void)
     33static void _CPU_cache_enable_instruction(void)
    3434{
    3535    rtems_interrupt_level level;
     
    4141}
    4242
    43 void _CPU_cache_disable_instruction(void)
     43static void _CPU_cache_disable_instruction(void)
    4444{
    4545    rtems_interrupt_level level;
     
    5151}
    5252
    53 void _CPU_cache_invalidate_entire_instruction(void)
     53static void _CPU_cache_invalidate_entire_instruction(void)
    5454{
    5555    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
    5656}
    5757
    58 void _CPU_cache_invalidate_1_instruction_line(const void *addr)
     58static void _CPU_cache_invalidate_1_instruction_line(const void *addr)
    5959{
    6060    /*
     
    6565}
    6666
    67 void _CPU_cache_enable_data(void)
     67static void _CPU_cache_enable_data(void)
    6868{
    6969    rtems_interrupt_level level;
     
    7575}
    7676
    77 void _CPU_cache_disable_data(void)
     77static void _CPU_cache_disable_data(void)
    7878{
    7979    rtems_interrupt_level level;
     
    8585}
    8686
    87 void _CPU_cache_invalidate_entire_data(void)
     87static void _CPU_cache_invalidate_entire_data(void)
    8888{
    8989    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
    9090}
    9191
    92 void _CPU_cache_invalidate_1_data_line(const void *addr)
     92static void _CPU_cache_invalidate_1_data_line(const void *addr)
    9393{
    9494    /*
     
    9898    __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
    9999}
     100
     101#include "../../../shared/cache/cacheimpl.h"
  • bsps/m68k/shared/cache/cache-mcf5282.c

    rd8d6a08 r4cf93658  
    77#include <rtems.h>
    88#include <mcf5282/mcf5282.h>   /* internal MCF5282 modules */
    9 #include "cache_.h"
     9#include "cache.h"
    1010
    1111/*
     
    4141 * Cannot be frozen
    4242 */
    43 void _CPU_cache_freeze_data(void) {}
    44 void _CPU_cache_unfreeze_data(void) {}
    45 void _CPU_cache_freeze_instruction(void) {}
    46 void _CPU_cache_unfreeze_instruction(void) {}
     43static void _CPU_cache_freeze_data(void) {}
     44static void _CPU_cache_unfreeze_data(void) {}
     45static void _CPU_cache_freeze_instruction(void) {}
     46static void _CPU_cache_unfreeze_instruction(void) {}
    4747
    4848/*
    4949 * Write-through data cache -- flushes are unnecessary
    5050 */
    51 void _CPU_cache_flush_1_data_line(const void *d_addr) {}
    52 void _CPU_cache_flush_entire_data(void) {}
     51static void _CPU_cache_flush_1_data_line(const void *d_addr) {}
     52static void _CPU_cache_flush_entire_data(void) {}
    5353
    54 void _CPU_cache_enable_instruction(void)
     54static void _CPU_cache_enable_instruction(void)
    5555{
    5656  rtems_interrupt_level level;
     
    6363}
    6464
    65 void _CPU_cache_disable_instruction(void)
     65static void _CPU_cache_disable_instruction(void)
    6666{
    6767  rtems_interrupt_level level;
     
    7373}
    7474
    75 void _CPU_cache_invalidate_entire_instruction(void)
     75static void _CPU_cache_invalidate_entire_instruction(void)
    7676{
    7777  m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
     
    7979}
    8080
    81 void _CPU_cache_invalidate_1_instruction_line(const void *addr)
     81static void _CPU_cache_invalidate_1_instruction_line(const void *addr)
    8282{
    8383  /*
     
    8888}
    8989
    90 void _CPU_cache_enable_data(void)
     90static void _CPU_cache_enable_data(void)
    9191{
    9292  rtems_interrupt_level level;
     
    9898}
    9999
    100 void _CPU_cache_disable_data(void)
     100static void _CPU_cache_disable_data(void)
    101101{
    102102  rtems_interrupt_level level;
     
    108108}
    109109
    110 void _CPU_cache_invalidate_entire_data(void)
     110static void _CPU_cache_invalidate_entire_data(void)
    111111{
    112112  m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
    113113}
    114114
    115 void _CPU_cache_invalidate_1_data_line(const void *addr)
     115static void _CPU_cache_invalidate_1_data_line(const void *addr)
    116116{
    117117  /*
     
    121121  __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
    122122}
     123
     124#include "../../../shared/cache/cacheimpl.h"
  • bsps/m68k/shared/cache/cache-mcf532x.c

    rd8d6a08 r4cf93658  
    77#include <rtems.h>
    88#include <mcf532x/mcf532x.h>
    9 #include "cache_.h"
     9#include "cache.h"
    1010
    1111#define m68k_set_cacr(_cacr) \
     
    2424 * Cannot be frozen
    2525 */
    26 void _CPU_cache_freeze_data(void)
     26static void _CPU_cache_freeze_data(void)
    2727{
    2828}
    2929
    30 void _CPU_cache_unfreeze_data(void)
     30static void _CPU_cache_unfreeze_data(void)
    3131{
    3232}
    3333
    34 void _CPU_cache_freeze_instruction(void)
     34static void _CPU_cache_freeze_instruction(void)
    3535{
    3636}
    3737
    38 void _CPU_cache_unfreeze_instruction(void)
     38static void _CPU_cache_unfreeze_instruction(void)
    3939{
    4040}
    4141
    42 void _CPU_cache_flush_1_data_line(const void *d_addr)
     42static void _CPU_cache_flush_1_data_line(const void *d_addr)
    4343{
    4444  register unsigned long adr = (((unsigned long) d_addr >> 4) & 0xff) << 4;
     
    5353}
    5454
    55 void _CPU_cache_flush_entire_data(void)
     55static void _CPU_cache_flush_entire_data(void)
    5656{
    5757  register unsigned long set, adr;
     
    6969}
    7070
    71 void _CPU_cache_enable_instruction(void)
     71static void _CPU_cache_enable_instruction(void)
    7272{
    7373  rtems_interrupt_level level;
     
    8282}
    8383
    84 void _CPU_cache_disable_instruction(void)
     84static void _CPU_cache_disable_instruction(void)
    8585{
    8686  rtems_interrupt_level level;
     
    9595}
    9696
    97 void _CPU_cache_invalidate_entire_instruction(void)
     97static void _CPU_cache_invalidate_entire_instruction(void)
    9898{
    9999  m68k_set_cacr(cacr_mode | MCF_CACR_CINVA);
    100100}
    101101
    102 void _CPU_cache_invalidate_1_instruction_line(const void *addr)
     102static void _CPU_cache_invalidate_1_instruction_line(const void *addr)
    103103{
    104104  register unsigned long adr = (((unsigned long) addr >> 4) & 0xff) << 4;
     
    113113}
    114114
    115 void _CPU_cache_enable_data(void)
     115static void _CPU_cache_enable_data(void)
    116116{
    117117  /*
     
    122122}
    123123
    124 void _CPU_cache_disable_data(void)
     124static void _CPU_cache_disable_data(void)
    125125{
    126126  /*
     
    131131}
    132132
    133 void _CPU_cache_invalidate_entire_data(void)
     133static void _CPU_cache_invalidate_entire_data(void)
    134134{
    135135  _CPU_cache_invalidate_entire_instruction();
    136136}
    137137
    138 void _CPU_cache_invalidate_1_data_line(const void *addr)
     138static void _CPU_cache_invalidate_1_data_line(const void *addr)
    139139{
    140140  _CPU_cache_invalidate_1_instruction_line(addr);
    141141}
     142
     143#include "../../../shared/cache/cacheimpl.h"
  • bsps/m68k/shared/cache/cache.h

    rd8d6a08 r4cf93658  
    11/*
    2  *  Cache Management Support Routines for the MC68040
    3  */
    4 
    5 #include <rtems.h>
    6 #include "cache_.h"
     2 *  M68K Cache Manager Support
     3 */
     4
     5#if (defined(__mc68020__) && !defined(__mcpu32__))
     6# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
     7#elif defined(__mc68030__)
     8# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
     9# define M68K_DATA_CACHE_ALIGNMENT 16
     10#elif ( defined(__mc68040__) || defined (__mc68060__) )
     11# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
     12# define M68K_DATA_CACHE_ALIGNMENT 16
     13#elif ( defined(__mcf5200__) )
     14# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
     15# if ( defined(__mcf528x__) )
     16#  define M68K_DATA_CACHE_ALIGNMENT 16
     17# endif
     18#elif ( defined(__mcf5300__) )
     19# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
     20# define M68K_DATA_CACHE_ALIGNMENT 16
     21#elif defined(__mcfv4e__)
     22# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
     23# define M68K_DATA_CACHE_ALIGNMENT 16
     24#endif
     25
     26#if defined(M68K_DATA_CACHE_ALIGNMENT)
     27#define CPU_DATA_CACHE_ALIGNMENT M68K_DATA_CACHE_ALIGNMENT
     28#endif
     29
     30#if defined(M68K_INSTRUCTION_CACHE_ALIGNMENT)
     31#define CPU_INSTRUCTION_CACHE_ALIGNMENT M68K_INSTRUCTION_CACHE_ALIGNMENT
     32#endif
    733
    834/*
     
    188214}
    189215#endif
    190 /* end of file */
Note: See TracChangeset for help on using the changeset viewer.