Changeset 4cf93658 in rtems for bsps/bfin/shared


Ignore:
Timestamp:
Jan 27, 2018, 1:37:51 PM (3 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
5, master
Children:
05015dc1
Parents:
d8d6a08
git-author:
Sebastian Huber <sebastian.huber@…> (01/27/18 13:37:51)
git-committer:
Sebastian Huber <sebastian.huber@…> (01/31/18 11:49:09)
Message:

bsps: Rework cache manager implementation

The previous cache manager support used a single souce file
(cache_manager.c) which included an implementation header (cache_.h).
This required the use of specialized include paths to find the right
header file. Change this to include a generic implementation header
(cacheimpl.h) in specialized source files.

Use the following directories and files:

  • bsps/shared/cache
  • bsps/@RTEMS_CPU@/shared/cache
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c

Update #3285.

File:
1 moved

Legend:

Unmodified
Added
Removed
  • bsps/bfin/shared/cache/cache.c

    rd8d6a08 r4cf93658  
    1313#include <bsp.h>
    1414#include <libcpu/memoryRegs.h>
    15 #include "cache_.h"
    1615
     16#define CPU_DATA_CACHE_ALIGNMENT          32
     17#define CPU_INSTRUCTION_CACHE_ALIGNMENT   32
     18
     19#ifdef BSP_DATA_CACHE_CONFIG
     20#define LIBCPU_DATA_CACHE_CONFIG BSP_DATA_CACHE_CONFIG
     21#else
     22/* use 16K of each SRAM bank */
     23#define LIBCPU_DATA_CACHE_CONFIG (3 << DMEM_CONTROL_DMC_SHIFT)
     24#endif
    1725
    1826/* There are many syncs in the following code because they should be
     
    2230
    2331
    24 void _CPU_cache_flush_1_data_line(const void *d_addr) {
     32static void _CPU_cache_flush_1_data_line(const void *d_addr) {
    2533
    2634  __asm__ __volatile__ ("ssync; flush [%0]; ssync" :: "a" (d_addr));
     
    3341   way to insure the dirty line hadn't been written out anyway prior
    3442   to the invalidate. */
    35 void _CPU_cache_invalidate_1_data_line(const void *d_addr) {
     43static void _CPU_cache_invalidate_1_data_line(const void *d_addr) {
    3644
    3745  __asm__ __volatile__ ("ssync; flushinv [%0]; ssync" :: "a" (d_addr));
    3846}
    3947
    40 void _CPU_cache_freeze_data(void) {
     48static void _CPU_cache_freeze_data(void) {
    4149}
    4250
    43 void _CPU_cache_unfreeze_data(void) {
     51static void _CPU_cache_unfreeze_data(void) {
    4452}
    4553
    46 void _CPU_cache_invalidate_1_instruction_line(const void *d_addr) {
     54static void _CPU_cache_invalidate_1_instruction_line(const void *d_addr) {
    4755
    4856  __asm__ __volatile__ ("ssync; iflush [%0]; ssync" :: "a" (d_addr));
    4957}
    5058
    51 void _CPU_cache_freeze_instruction(void) {
     59static void _CPU_cache_freeze_instruction(void) {
    5260}
    5361
    54 void _CPU_cache_unfreeze_instruction(void) {
     62static void _CPU_cache_unfreeze_instruction(void) {
    5563}
    5664
     
    6068   seen on those is a bit sketchy, and I sure wouldn't want to get it
    6169   wrong. */
    62 void _CPU_cache_flush_entire_data(void) {
     70static void _CPU_cache_flush_entire_data(void) {
    6371  uint32_t i;
    6472
     
    7280}
    7381
    74 void _CPU_cache_invalidate_entire_data(void) {
     82static void _CPU_cache_invalidate_entire_data(void) {
    7583  uint32_t dmemControl;
    7684
     
    8492/* this does not actually enable data cache unless CPLBs are also enabled.
    8593   LIBCPU_DATA_CACHE_CONFIG contains the DMEM_CONTROL_DMC bits to set. */
    86 void _CPU_cache_enable_data(void) {
     94static void _CPU_cache_enable_data(void) {
    8795
    8896  __asm__ __volatile__ ("ssync");
     
    9199}
    92100
    93 void _CPU_cache_disable_data(void) {
     101static void _CPU_cache_disable_data(void) {
    94102
    95103  __asm__ __volatile__ ("ssync");
     
    98106}
    99107
    100 void _CPU_cache_invalidate_entire_instruction(void) {
     108static void _CPU_cache_invalidate_entire_instruction(void) {
    101109  uint32_t imemControl;
    102110
     
    110118/* this only actually enables the instruction cache if the CPLBs are also
    111119   enabled. */
    112 void _CPU_cache_enable_instruction(void) {
     120static void _CPU_cache_enable_instruction(void) {
    113121
    114122  __asm__ __volatile__ ("ssync");
     
    117125}
    118126
    119 void _CPU_cache_disable_instruction(void) {
     127static void _CPU_cache_disable_instruction(void) {
    120128
    121129  __asm__ __volatile__ ("ssync");
     
    124132}
    125133
     134#include "../../../shared/cache/cacheimpl.h"
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