Changeset 4cf93658 in rtems for bsps/bfin

Timestamp:

Jan 27, 2018, 1:37:51 PM (3 years ago)

Author:

Sebastian Huber <sebastian.huber@…>

Branches:

5, master

Children:

05015dc1

Parents:

d8d6a08

git-author:

Sebastian Huber <sebastian.huber@…> (01/27/18 13:37:51)

git-committer:

Sebastian Huber <sebastian.huber@…> (01/31/18 11:49:09)

Message:

bsps: Rework cache manager implementation

The previous cache manager support used a single souce file
(cache_manager.c) which included an implementation header (cache_.h).
This required the use of specialized include paths to find the right
header file. Change this to include a generic implementation header
(cacheimpl.h) in specialized source files.

Use the following directories and files:

• bsps/shared/cache

• bsps/@RTEMS_CPU@/shared/cache

• bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c

Update #3285.

File:

• bsps/bfin/shared/cache/cache.c (moved) (moved from c/src/lib/libcpu/bfin/cache/cache.c) (11 diffs)

bsps/bfin/shared/cache/cache.c

@@ -13 +13 @@
 #include <bsp.h>
 #include <libcpu/memoryRegs.h>
-#include "cache_.h"
 
+#define CPU_DATA_CACHE_ALIGNMENT          32
+#define CPU_INSTRUCTION_CACHE_ALIGNMENT   32
+
+#ifdef BSP_DATA_CACHE_CONFIG
+#define LIBCPU_DATA_CACHE_CONFIG BSP_DATA_CACHE_CONFIG
+#else
+/* use 16K of each SRAM bank */
+#define LIBCPU_DATA_CACHE_CONFIG (3 << DMEM_CONTROL_DMC_SHIFT)
+#endif
 
 /* There are many syncs in the following code because they should be
@@ -22 +30 @@
 
 
-void _CPU_cache_flush_1_data_line(const void *d_addr) {
+static void _CPU_cache_flush_1_data_line(const void *d_addr) {
 
   __asm__ __volatile__ ("ssync; flush [%0]; ssync" :: "a" (d_addr));
@@ -33 +41 @@
    way to insure the dirty line hadn't been written out anyway prior
    to the invalidate. */
-void _CPU_cache_invalidate_1_data_line(const void *d_addr) {
+static void _CPU_cache_invalidate_1_data_line(const void *d_addr) {
 
   __asm__ __volatile__ ("ssync; flushinv [%0]; ssync" :: "a" (d_addr));
 }
 
-void _CPU_cache_freeze_data(void) {
+static void _CPU_cache_freeze_data(void) {
 }
 
-void _CPU_cache_unfreeze_data(void) {
+static void _CPU_cache_unfreeze_data(void) {
 }
 
-void _CPU_cache_invalidate_1_instruction_line(const void *d_addr) {
+static void _CPU_cache_invalidate_1_instruction_line(const void *d_addr) {
 
   __asm__ __volatile__ ("ssync; iflush [%0]; ssync" :: "a" (d_addr));
 }
 
-void _CPU_cache_freeze_instruction(void) {
+static void _CPU_cache_freeze_instruction(void) {
 }
 
-void _CPU_cache_unfreeze_instruction(void) {
+static void _CPU_cache_unfreeze_instruction(void) {
 }
 
@@ -60 +68 @@
    seen on those is a bit sketchy, and I sure wouldn't want to get it
    wrong. */
-void _CPU_cache_flush_entire_data(void) {
+static void _CPU_cache_flush_entire_data(void) {
   uint32_t i;
 
@@ -72 +80 @@
 }
 
-void _CPU_cache_invalidate_entire_data(void) {
+static void _CPU_cache_invalidate_entire_data(void) {
   uint32_t dmemControl;
 
@@ -84 +92 @@
 /* this does not actually enable data cache unless CPLBs are also enabled.
    LIBCPU_DATA_CACHE_CONFIG contains the DMEM_CONTROL_DMC bits to set. */
-void _CPU_cache_enable_data(void) {
+static void _CPU_cache_enable_data(void) {
 
   __asm__ __volatile__ ("ssync");
@@ -91 +99 @@
 }
 
-void _CPU_cache_disable_data(void) {
+static void _CPU_cache_disable_data(void) {
 
   __asm__ __volatile__ ("ssync");
@@ -98 +106 @@
 }
 
-void _CPU_cache_invalidate_entire_instruction(void) {
+static void _CPU_cache_invalidate_entire_instruction(void) {
   uint32_t imemControl;
 
@@ -110 +118 @@
 /* this only actually enables the instruction cache if the CPLBs are also
    enabled. */
-void _CPU_cache_enable_instruction(void) {
+static void _CPU_cache_enable_instruction(void) {
 
   __asm__ __volatile__ ("ssync");
@@ -117 +125 @@
 }
 
-void _CPU_cache_disable_instruction(void) {
+static void _CPU_cache_disable_instruction(void) {
 
   __asm__ __volatile__ ("ssync");
@@ -124 +132 @@
 }
 
+#include "../../../shared/cache/cacheimpl.h"