Changeset 4c4974e in rtems


Ignore:
Timestamp:
May 20, 2010, 1:15:35 PM (9 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.10, 4.11, master
Children:
f780417
Parents:
a9485d7b
Message:

2010-05-20 Sebastian Huber <sebastian.huber@…>

  • make/custom/lpc32xx.inc, make/custom/lpc32xx_mzx_boot_int.cfg, startup/linkcmds.lpc32xx_mzx_boot_int: New files.
  • Makefile.am, configure.ac, preinstall.am, include/bsp.h, include/bspopts.h.in, include/lpc32xx.h, irq/irq.c, make/custom/lpc32xx_phycore.cfg, startup/bspstart.c, startup/bspstarthooks.c: Changes throughout.
Location:
c/src/lib/libbsp/arm/lpc32xx
Files:
3 added
11 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/lpc32xx/ChangeLog

    ra9485d7b r4c4974e  
     12010-05-20      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * make/custom/lpc32xx.inc, make/custom/lpc32xx_mzx_boot_int.cfg,
     4        startup/linkcmds.lpc32xx_mzx_boot_int: New files.
     5        * Makefile.am, configure.ac, preinstall.am, include/bsp.h,
     6        include/bspopts.h.in, include/lpc32xx.h, irq/irq.c,
     7        make/custom/lpc32xx_phycore.cfg, startup/bspstart.c,
     8        startup/bspstarthooks.c: Changes throughout.
     9
    1102010-05-20      Sebastian Huber <sebastian.huber@embedded-brains.de>
    211
  • c/src/lib/libbsp/arm/lpc32xx/Makefile.am

    ra9485d7b r4c4974e  
    3434include_bsp_HEADERS += ../../shared/include/irq-info.h
    3535include_bsp_HEADERS += ../../shared/include/stackalloc.h
     36include_bsp_HEADERS += ../../shared/include/uart-output-char.h
    3637include_bsp_HEADERS += ../../shared/tod.h
    3738include_bsp_HEADERS += ../shared/include/linker-symbols.h
     
    6162project_lib_DATA += ../shared/startup/linkcmds.base
    6263
    63 EXTRA_DIST = startup/linkcmds.lpc32xx_phycore
     64EXTRA_DIST = startup/linkcmds.lpc32xx_phycore \
     65        startup/linkcmds.lpc32xx_mzx_boot_int
    6466
    6567###############################################################################
     
    8486        ../../shared/sbrk.c \
    8587        ../../shared/src/stackalloc.c \
     88        ../../shared/src/uart-output-char.c \
    8689        ../shared/abort/simple_abort.c
    8790
  • c/src/lib/libbsp/arm/lpc32xx/configure.ac

    ra9485d7b r4c4974e  
    6464RTEMS_BSPOPTS_HELP([LPC32XX_CONFIG_UART_CLKMODE],[clock mode configuration for UARTs])
    6565
     66RTEMS_BSPOPTS_SET([LPC32XX_DISABLE_MMU],[lpc32xx_boot],[1])
     67RTEMS_BSPOPTS_SET([LPC32XX_DISABLE_MMU],[*],[])
     68RTEMS_BSPOPTS_HELP([LPC32XX_DISABLE_MMU],[disable MMU])
     69
    6670RTEMS_BSPOPTS_SET([LPC32XX_DISABLE_READ_WRITE_DATA_CACHE],[*],[])
    6771RTEMS_BSPOPTS_HELP([LPC32XX_DISABLE_READ_WRITE_DATA_CACHE],[disable cache for read-write data sections])
  • c/src/lib/libbsp/arm/lpc32xx/include/bsp.h

    ra9485d7b r4c4974e  
    101101}
    102102
     103#define BSP_CONSOLE_UART_BASE 0x40090000
     104
    103105/** @} */
    104106
  • c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in

    ra9485d7b r4c4974e  
    3333/* clock mode configuration for UARTs */
    3434#undef LPC32XX_CONFIG_UART_CLKMODE
     35
     36/* disable MMU */
     37#undef LPC32XX_DISABLE_MMU
    3538
    3639/* disable MMU protection of read-only sections */
  • c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h

    ra9485d7b r4c4974e  
    2222#ifndef LIBBSP_ARM_LPC32XX_LPC32XX_H
    2323#define LIBBSP_ARM_LPC32XX_LPC32XX_H
     24
     25#include <stdint.h>
    2426
    2527/**
  • c/src/lib/libbsp/arm/lpc32xx/irq/irq.c

    ra9485d7b r4c4974e  
    309309{
    310310  if ((unsigned) exception < MAX_EXCEPTIONS) {
    311     uint32_t *table = (uint32_t *) bsp_section_vector_begin + MAX_EXCEPTIONS;
     311    #ifndef LPC32XX_DISABLE_MMU
     312      uint32_t *table = (uint32_t *) bsp_section_vector_begin + MAX_EXCEPTIONS;
     313    #else
     314      uint32_t *table = (uint32_t *) bsp_section_start_begin + MAX_EXCEPTIONS;
     315    #endif
    312316
    313317    table [exception] = (uint32_t) handler;
    314318
    315     rtems_cache_flush_multiple_data_lines(NULL, 64);
    316     rtems_cache_invalidate_multiple_data_lines(NULL, 64);
     319    #ifndef LPC32XX_DISABLE_MMU
     320      rtems_cache_flush_multiple_data_lines(table, 64);
     321      rtems_cache_invalidate_multiple_instruction_lines(NULL, 64);
     322    #endif
    317323  }
    318324}
  • c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx_phycore.cfg

    ra9485d7b r4c4974e  
    55#
    66
    7 include $(RTEMS_ROOT)/make/custom/default.cfg
    8 
    9 RTEMS_CPU = arm
    10 
    11 CPU_CFLAGS = -mstructure-size-boundary=8 -mcpu=arm926ej-s -mfpu=vfp -mfloat-abi=soft -mthumb \
    12         -fno-schedule-insns2
    13 
    14 CFLAGS_OPTIMIZE_V = -Os -g
     7include $(RTEMS_ROOT)/make/custom/lpc32xx.inc
  • c/src/lib/libbsp/arm/lpc32xx/preinstall.am

    ra9485d7b r4c4974e  
    7979PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stackalloc.h
    8080
     81$(PROJECT_INCLUDE)/bsp/uart-output-char.h: ../../shared/include/uart-output-char.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     82        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart-output-char.h
     83PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/uart-output-char.h
     84
    8185$(PROJECT_INCLUDE)/bsp/tod.h: ../../shared/tod.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    8286        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tod.h
  • c/src/lib/libbsp/arm/lpc32xx/startup/bspstart.c

    ra9485d7b r4c4974e  
    88
    99/*
    10  * Copyright (c) 2009
     10 * Copyright (c) 2009, 2010
    1111 * embedded brains GmbH
    1212 * Obere Lagerstr. 30
     
    2828#include <bsp/lpc32xx.h>
    2929
    30 /* FIXME */
    31 #define CONSOLE_RBR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x00))
    32 #define CONSOLE_THR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x00))
    33 #define CONSOLE_DLL (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x00))
    34 #define CONSOLE_DLM (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x04))
    35 #define CONSOLE_IER (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x04))
    36 #define CONSOLE_IIR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x08))
    37 #define CONSOLE_FCR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x08))
    38 #define CONSOLE_LCR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x0C))
    39 #define CONSOLE_LSR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x14))
    40 #define CONSOLE_SCR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x1C))
    41 #define CONSOLE_ACR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x20))
    42 #define CONSOLE_ICR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x24))
    43 #define CONSOLE_FDR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x28))
    44 #define CONSOLE_TER (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x30))
    45 
    4630static void lpc32xx_timer_initialize(void)
    4731{
     
    6145void bsp_start(void)
    6246{
    63   uint32_t uartclk_ctrl = 0;
    64 
    65   #ifdef LPC32XX_CONFIG_U3CLK
    66     uartclk_ctrl |= 1U << 0;
    67     LPC32XX_U3CLK = LPC32XX_CONFIG_U3CLK;
    68   #endif
    69   #ifdef LPC32XX_CONFIG_U4CLK
    70     uartclk_ctrl |= 1U << 1;
    71     LPC32XX_U4CLK = LPC32XX_CONFIG_U4CLK;
    72   #endif
    73   #ifdef LPC32XX_CONFIG_U5CLK
    74     uartclk_ctrl |= 1U << 2;
    75     LPC32XX_U5CLK = LPC32XX_CONFIG_U5CLK;
    76   #endif
    77   #ifdef LPC32XX_CONFIG_U6CLK
    78     uartclk_ctrl |= 1U << 3;
    79     LPC32XX_U6CLK = LPC32XX_CONFIG_U6CLK;
    80   #endif
    81 
    82   #ifdef LPC32XX_CONFIG_UART_CLKMODE
    83     LPC32XX_UART_CLKMODE = LPC32XX_CONFIG_UART_CLKMODE;
    84   #endif
    85 
    86   LPC32XX_UARTCLK_CTRL = uartclk_ctrl;
    87   LPC32XX_UART_CTRL = 0x0;
    88   LPC32XX_UART_LOOP = 0x0;
    89 
    90   /* FIXME */
    91   CONSOLE_LCR = 0x0;
    92   CONSOLE_IER = 0x0;
    93   CONSOLE_LCR = 0x80;
    94   CONSOLE_DLL = 0x1; /* Clock is already set in LPC32XX_U5CLK */
    95   CONSOLE_DLM = 0x0;
    96   CONSOLE_LCR = 0x3;
    97   CONSOLE_FCR = 0x7;
    98 
    9947  if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) {
    10048    _CPU_Fatal_halt(0xe);
     
    10856  lpc32xx_timer_initialize();
    10957}
    110 
    111 #define UART_LSR_THRE 0x00000020U
    112 
    113 static void lpc32xx_console_wait(void)
    114 {
    115   while ((CONSOLE_LSR & UART_LSR_THRE) == 0) {
    116     /* Wait */
    117   }
    118 }
    119 
    120 static void lpc32xx_BSP_output_char(char c)
    121 {
    122   lpc32xx_console_wait();
    123 
    124   CONSOLE_THR = c;
    125 
    126   if (c == '\n') {
    127     lpc32xx_console_wait();
    128 
    129     CONSOLE_THR = '\r';
    130   }
    131 }
    132 
    133 BSP_output_char_function_type BSP_output_char = lpc32xx_BSP_output_char;
  • c/src/lib/libbsp/arm/lpc32xx/startup/bspstarthooks.c

    ra9485d7b r4c4974e  
    2727#include <bsp/mmu.h>
    2828#include <bsp/linker-symbols.h>
     29#include <bsp/uart-output-char.h>
    2930
    3031#ifdef LPC32XX_DISABLE_READ_WRITE_DATA_CACHE
     
    5758}
    5859
    59 typedef struct {
    60   uint32_t begin;
    61   uint32_t end;
    62   uint32_t flags;
    63 } lpc32xx_mmu_config;
    64 
    65 static const BSP_START_DATA_SECTION lpc32xx_mmu_config
    66   lpc32xx_mmu_config_table [] = {
     60#ifndef LPC32XX_DISABLE_MMU
     61  typedef struct {
     62    uint32_t begin;
     63    uint32_t end;
     64    uint32_t flags;
     65  } lpc32xx_mmu_config;
     66
     67  static const BSP_START_DATA_SECTION lpc32xx_mmu_config
     68    lpc32xx_mmu_config_table [] = {
     69    {
     70      .begin = (uint32_t) bsp_section_start_begin,
     71      .end = (uint32_t) bsp_section_start_end,
     72      .flags = LPC32XX_MMU_CODE
     73    }, {
     74      .begin = (uint32_t) bsp_section_vector_begin,
     75      .end = (uint32_t) bsp_section_vector_end,
     76      .flags = LPC32XX_MMU_READ_WRITE_CACHED
     77    }, {
     78      .begin = (uint32_t) bsp_section_text_begin,
     79      .end = (uint32_t) bsp_section_text_end,
     80      .flags = LPC32XX_MMU_CODE
     81    }, {
     82      .begin = (uint32_t) bsp_section_rodata_begin,
     83      .end = (uint32_t) bsp_section_rodata_end,
     84      .flags = LPC32XX_MMU_READ_ONLY_DATA
     85    }, {
     86      .begin = (uint32_t) bsp_section_data_begin,
     87      .end = (uint32_t) bsp_section_data_end,
     88      .flags = LPC32XX_MMU_READ_WRITE_DATA
     89    }, {
     90      .begin = (uint32_t) bsp_section_fast_begin,
     91      .end = (uint32_t) bsp_section_fast_end,
     92      .flags = LPC32XX_MMU_CODE
     93    }, {
     94      .begin = (uint32_t) bsp_section_bss_begin,
     95      .end = (uint32_t) bsp_section_bss_end,
     96      .flags = LPC32XX_MMU_READ_WRITE_DATA
     97    }, {
     98      .begin = (uint32_t) bsp_section_work_begin,
     99      .end = (uint32_t) bsp_section_work_end,
     100      .flags = LPC32XX_MMU_READ_WRITE_DATA
     101    }, {
     102      .begin = (uint32_t) bsp_section_stack_begin,
     103      .end = (uint32_t) bsp_section_stack_end,
     104      .flags = LPC32XX_MMU_READ_WRITE_DATA
     105    }, {
     106      .begin = 0x0U,
     107      .end = 0x100000U,
     108      .flags = LPC32XX_MMU_READ_ONLY_CACHED
     109    }, {
     110      .begin = 0x20000000U,
     111      .end = 0x200c0000U,
     112      .flags = LPC32XX_MMU_READ_WRITE
     113    }, {
     114      .begin = 0x30000000U,
     115      .end = 0x32000000U,
     116      .flags = LPC32XX_MMU_READ_WRITE
     117    }, {
     118      .begin = 0x40000000U,
     119      .end = 0x40100000U,
     120      .flags = LPC32XX_MMU_READ_WRITE
     121    }
     122  };
     123
     124  static void BSP_START_SECTION lpc32xx_mmu_set_entries(
     125    uint32_t *ttb,
     126    const lpc32xx_mmu_config *config
     127  )
    67128  {
    68     .begin = (uint32_t) bsp_section_start_begin,
    69     .end = (uint32_t) bsp_section_start_end,
    70     .flags = LPC32XX_MMU_CODE
    71   }, {
    72     .begin = (uint32_t) bsp_section_vector_begin,
    73     .end = (uint32_t) bsp_section_vector_end,
    74     .flags = LPC32XX_MMU_READ_WRITE_CACHED
    75   }, {
    76     .begin = (uint32_t) bsp_section_text_begin,
    77     .end = (uint32_t) bsp_section_text_end,
    78     .flags = LPC32XX_MMU_CODE
    79   }, {
    80     .begin = (uint32_t) bsp_section_rodata_begin,
    81     .end = (uint32_t) bsp_section_rodata_end,
    82     .flags = LPC32XX_MMU_READ_ONLY_DATA
    83   }, {
    84     .begin = (uint32_t) bsp_section_data_begin,
    85     .end = (uint32_t) bsp_section_data_end,
    86     .flags = LPC32XX_MMU_READ_WRITE_DATA
    87   }, {
    88     .begin = (uint32_t) bsp_section_fast_begin,
    89     .end = (uint32_t) bsp_section_fast_end,
    90     .flags = LPC32XX_MMU_CODE
    91   }, {
    92     .begin = (uint32_t) bsp_section_bss_begin,
    93     .end = (uint32_t) bsp_section_bss_end,
    94     .flags = LPC32XX_MMU_READ_WRITE_DATA
    95   }, {
    96     .begin = (uint32_t) bsp_section_work_begin,
    97     .end = (uint32_t) bsp_section_work_end,
    98     .flags = LPC32XX_MMU_READ_WRITE_DATA
    99   }, {
    100     .begin = (uint32_t) bsp_section_stack_begin,
    101     .end = (uint32_t) bsp_section_stack_end,
    102     .flags = LPC32XX_MMU_READ_WRITE_DATA
    103   }, {
    104     .begin = 0x0U,
    105     .end = 0x100000U,
    106     .flags = LPC32XX_MMU_READ_ONLY_CACHED
    107   }, {
    108     .begin = 0x20000000U,
    109     .end = 0x200c0000U,
    110     .flags = LPC32XX_MMU_READ_WRITE
    111   }, {
    112     .begin = 0x30000000U,
    113     .end = 0x32000000U,
    114     .flags = LPC32XX_MMU_READ_WRITE
    115   }, {
    116     .begin = 0x40000000U,
    117     .end = 0x40100000U,
    118     .flags = LPC32XX_MMU_READ_WRITE
     129    uint32_t i = ARM_MMU_SECT_GET_INDEX(config->begin);
     130    uint32_t iend =
     131      ARM_MMU_SECT_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(config->end));
     132
     133    if (config->begin != config->end) {
     134      while (i < iend) {
     135        ttb [i] = (i << ARM_MMU_SECT_BASE_SHIFT) | config->flags;
     136        ++i;
     137      }
     138    }
    119139  }
    120 };
    121 
    122 static void BSP_START_SECTION lpc32xx_mmu_set_entries(
    123   uint32_t *ttb,
    124   const lpc32xx_mmu_config *config
    125 )
    126 {
    127   uint32_t i = ARM_MMU_SECT_GET_INDEX(config->begin);
    128   uint32_t iend = ARM_MMU_SECT_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(config->end));
    129 
    130   if (config->begin != config->end) {
    131     while (i < iend) {
    132       ttb [i] = (i << ARM_MMU_SECT_BASE_SHIFT) | config->flags;
    133       ++i;
    134     }
     140
     141  static void BSP_START_SECTION
     142    lpc32xx_setup_translation_table_and_enable_mmu(uint32_t ctrl)
     143  {
     144    uint32_t const dac =
     145      ARM_CP15_DAC_DOMAIN(LPC32XX_MMU_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT);
     146    uint32_t *const ttb = (uint32_t *) bsp_section_work_end;
     147    size_t const config_entry_count =
     148      sizeof(lpc32xx_mmu_config_table) / sizeof(lpc32xx_mmu_config_table [0]);
     149    size_t i = 0;
     150
     151    arm_cp15_set_domain_access_control(dac);
     152    arm_cp15_set_translation_table_base(ttb);
     153
     154    /* Initialize translation table with invalid entries */
     155    for (i = 0; i < ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT; ++i) {
     156      ttb [i] = 0;
     157    }
     158
     159    for (i = 0; i < config_entry_count; ++i) {
     160      lpc32xx_mmu_set_entries(ttb, &lpc32xx_mmu_config_table [i]);
     161    }
     162
     163    /* Enable MMU and cache */
     164    ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M;
     165    arm_cp15_set_control(ctrl);
    135166  }
    136 }
     167#endif
    137168
    138169static void BSP_START_SECTION lpc32xx_mmu_and_cache_setup(void)
    139170{
    140   uint32_t const dac =
    141     ARM_CP15_DAC_DOMAIN(LPC32XX_MMU_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT);
    142171  uint32_t ctrl = 0;
    143   uint32_t *const ttb = (uint32_t *) bsp_section_work_end;
    144   size_t const config_entry_count =
    145     sizeof(lpc32xx_mmu_config_table) / sizeof(lpc32xx_mmu_config_table [0]);
    146   size_t i = 0;
    147172
    148173  /* Disable MMU and cache, basic settings */
     
    156181  arm_cp15_tlb_invalidate();
    157182
    158   arm_cp15_set_domain_access_control(dac);
    159   arm_cp15_set_translation_table_base(ttb);
    160 
    161   /* Initialize translation table with invalid entries */
    162   for (i = 0; i < ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT; ++i) {
    163     ttb [i] = 0;
    164   }
    165 
    166   for (i = 0; i < config_entry_count; ++i) {
    167     lpc32xx_mmu_set_entries(ttb, &lpc32xx_mmu_config_table [i]);
    168   }
    169 
    170   /* Enable MMU and cache */
    171   ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M;
    172   arm_cp15_set_control(ctrl);
     183  #ifndef LPC32XX_DISABLE_MMU
     184    lpc32xx_setup_translation_table_and_enable_mmu(ctrl);
     185  #endif
    173186}
    174187
     
    178191}
    179192
     193static void BSP_START_SECTION bsp_start_config_uarts(void)
     194{
     195  uint32_t uartclk_ctrl = 0;
     196
     197  #ifdef LPC32XX_CONFIG_U3CLK
     198    uartclk_ctrl |= 1U << 0;
     199    LPC32XX_U3CLK = LPC32XX_CONFIG_U3CLK;
     200  #endif
     201  #ifdef LPC32XX_CONFIG_U4CLK
     202    uartclk_ctrl |= 1U << 1;
     203    LPC32XX_U4CLK = LPC32XX_CONFIG_U4CLK;
     204  #endif
     205  #ifdef LPC32XX_CONFIG_U5CLK
     206    uartclk_ctrl |= 1U << 2;
     207    LPC32XX_U5CLK = LPC32XX_CONFIG_U5CLK;
     208  #endif
     209  #ifdef LPC32XX_CONFIG_U6CLK
     210    uartclk_ctrl |= 1U << 3;
     211    LPC32XX_U6CLK = LPC32XX_CONFIG_U6CLK;
     212  #endif
     213
     214  #ifdef LPC32XX_CONFIG_UART_CLKMODE
     215    LPC32XX_UART_CLKMODE = LPC32XX_CONFIG_UART_CLKMODE;
     216  #endif
     217
     218  LPC32XX_UARTCLK_CTRL = uartclk_ctrl;
     219  LPC32XX_UART_CTRL = 0x0;
     220  LPC32XX_UART_LOOP = 0x0;
     221
     222  #ifdef LPC32XX_CONFIG_U5CLK
     223    /* Clock is already set in LPC32XX_U5CLK */
     224    BSP_CONSOLE_UART_INIT(0x01);
     225  #endif
     226}
     227
    180228void BSP_START_SECTION bsp_start_hook_1(void)
    181229{
    182   /* TODO */
     230  bsp_start_config_uarts();
    183231
    184232  /* Copy .text section */
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