Changeset 4bafde5 in rtems


Ignore:
Timestamp:
Jun 21, 2011, 10:12:10 PM (8 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.11, master
Children:
dfe9034
Parents:
b375f06
Message:

2011-06-21 Joel Sherrill <joel.sherrill@…>

  • rtems/score/cpu.h, rtems/score/sparc.h, rtems/score/types.h: Convert comments to Doxygen style and improve.
Location:
cpukit/score/cpu/sparc
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/sparc/ChangeLog

    rb375f06 r4bafde5  
     12011-06-21      Joel Sherrill <joel.sherrill@oarcorp.com>
     2
     3        * rtems/score/cpu.h, rtems/score/sparc.h, rtems/score/types.h: Convert
     4        comments to Doxygen style and improve.
     5
    162011-05-17      Ralf Corsépius <ralf.corsepius@rtems.org>
    27
  • cpukit/score/cpu/sparc/rtems/score/cpu.h

    rb375f06 r4bafde5  
    11/**
    22 * @file rtems/score/cpu.h
    3  */
    4 
    5 /*
     3 *
    64 *  This include file contains information pertaining to the port of
    75 *  the executive to the SPARC processor.
    8  *
     6 */
     7
     8/*
    99 *  COPYRIGHT (c) 1989-2011.
    1010 *  On-Line Applications Research Corporation (OAR).
     
    2929/* conditional compilation parameters */
    3030
    31 /*
     31/**
    3232 *  Should the calls to _Thread_Enable_dispatch be inlined?
    3333 *
    34  *  If TRUE, then they are inlined.
    35  *  If FALSE, then a subroutine call is made.
    36  */
    37 
     34 *  - If TRUE, then they are inlined.
     35 *  - If FALSE, then a subroutine call is made.
     36 *
     37 *  On this port, it is faster to inline _Thread_Enable_dispatch.
     38 */
    3839#define CPU_INLINE_ENABLE_DISPATCH       TRUE
    3940
    40 /*
     41/**
    4142 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
    4243 *  be unrolled one time?  In unrolled each iteration of the loop examines
     
    4445 *  is examined per iteration.
    4546 *
    46  *  If TRUE, then the loops are unrolled.
    47  *  If FALSE, then the loops are not unrolled.
     47 *  - If TRUE, then the loops are unrolled.
     48 *  - If FALSE, then the loops are not unrolled.
    4849 *
    4950 *  This parameter could go either way on the SPARC.  The interrupt flash
     
    5253 *  not represent a great deal of time.
    5354 */
    54 
    5555#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
    5656
    57 /*
     57/**
    5858 *  Does the executive manage a dedicated interrupt stack in software?
    5959 *
     
    6464 *  been implemented in SW.
    6565 */
    66 
    6766#define CPU_HAS_SOFTWARE_INTERRUPT_STACK   TRUE
    6867
    69 /*
     68/**
    7069 *  Does the CPU follow the simple vectored interrupt model?
    7170 *
    72  *  If TRUE, then RTEMS allocates the vector table it internally manages.
    73  *  If FALSE, then the BSP is assumed to allocate and manage the vector
    74  *  table
    75  *
    76  *  SPARC Specific Information:
    77  *
    78  *  XXX document implementation including references if appropriate
     71 *  - If TRUE, then RTEMS allocates the vector table it internally manages.
     72 *  - If FALSE, then the BSP is assumed to allocate and manage the vector
     73 *    table
     74 *
     75 *  THe SPARC is a simple vectored architecture.  Usually there is no
     76 *  PIC and the CPU directly vectors the interrupts.
    7977 */
    8078#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
    8179
    82 /*
     80/**
    8381 *  Does this CPU have hardware support for a dedicated interrupt stack?
    8482 *
    85  *  If TRUE, then it must be installed during initialization.
    86  *  If FALSE, then no installation is performed.
     83 *  - If TRUE, then it must be installed during initialization.
     84 *  - If FALSE, then no installation is performed.
    8785 *
    8886 *  The SPARC does not have a dedicated HW interrupt stack.
    8987 */
    90 
    9188#define CPU_HAS_HARDWARE_INTERRUPT_STACK  FALSE
    9289
    93 /*
     90/**
    9491 *  Do we allocate a dedicated interrupt stack in the Interrupt Manager?
    9592 *
    96  *  If TRUE, then the memory is allocated during initialization.
    97  *  If FALSE, then the memory is allocated during initialization.
    98  */
    99 
     93 *  - If TRUE, then the memory is allocated during initialization.
     94 *  - If FALSE, then the memory is allocated during initialization.
     95 *
     96 *  The SPARC does not have hardware support for switching to a
     97 *  dedicated interrupt stack.  The port includes support for doing this
     98 *  in software.
     99 *
     100 */
    100101#define CPU_ALLOCATE_INTERRUPT_STACK      TRUE
    101102
    102 /*
     103/**
    103104 *  Does the RTEMS invoke the user's ISR with the vector number and
    104105 *  a pointer to the saved interrupt frame (1) or just the vector
    105106 *  number (0)?
    106  */
    107 
     107 *
     108 *  The SPARC port does not pass an Interrupt Stack Frame pointer to
     109 *  interrupt handlers.
     110 */
    108111#define CPU_ISR_PASSES_FRAME_POINTER 0
    109112
    110 /*
     113/**
    111114 *  Does the CPU have hardware floating point?
    112115 *
    113  *  If TRUE, then the FLOATING_POINT task attribute is supported.
    114  *  If FALSE, then the FLOATING_POINT task attribute is ignored.
    115  */
    116 
     116 *  - If TRUE, then the FLOATING_POINT task attribute is supported.
     117 *  - If FALSE, then the FLOATING_POINT task attribute is ignored.
     118 *
     119 *  This is set based upon the multilib settings.
     120 */
    117121#if ( SPARC_HAS_FPU == 1 )
    118 #define CPU_HARDWARE_FP     TRUE
     122  #define CPU_HARDWARE_FP     TRUE
    119123#else
    120 #define CPU_HARDWARE_FP     FALSE
     124  #define CPU_HARDWARE_FP     FALSE
    121125#endif
     126
     127/**
     128 *  The SPARC GCC port does not have a software floating point library
     129 *  that requires RTEMS assistance.
     130 */
    122131#define CPU_SOFTWARE_FP     FALSE
    123132
    124 /*
     133/**
    125134 *  Are all tasks FLOATING_POINT tasks implicitly?
    126135 *
    127  *  If TRUE, then the FLOATING_POINT task attribute is assumed.
    128  *  If FALSE, then the FLOATING_POINT task attribute is followed.
    129  */
    130 
     136 *  - If TRUE, then the FLOATING_POINT task attribute is assumed.
     137 *  - If FALSE, then the FLOATING_POINT task attribute is followed.
     138 *
     139 *  The SPARC GCC port does not implicitly use floating point registers.
     140 */
    131141#define CPU_ALL_TASKS_ARE_FP     FALSE
    132142
    133 /*
     143/**
    134144 *  Should the IDLE task have a floating point context?
    135145 *
    136  *  If TRUE, then the IDLE task is created as a FLOATING_POINT task
    137  *  and it has a floating point context which is switched in and out.
    138  *  If FALSE, then the IDLE task does not have a floating point context.
    139  */
    140 
     146 *  - If TRUE, then the IDLE task is created as a FLOATING_POINT task
     147 *    and it has a floating point context which is switched in and out.
     148 *  - If FALSE, then the IDLE task does not have a floating point context.
     149 *
     150 *  The IDLE task does not have to be floating point on the SPARC.
     151 */
    141152#define CPU_IDLE_TASK_IS_FP      FALSE
    142153
    143 /*
     154/**
    144155 *  Should the saving of the floating point registers be deferred
    145156 *  until a context switch is made to another different floating point
    146157 *  task?
    147158 *
    148  *  If TRUE, then the floating point context will not be stored until
     159 *  - If TRUE, then the floating point context will not be stored until
    149160 *  necessary.  It will remain in the floating point registers and not
    150161 *  disturned until another floating point task is switched to.
    151162 *
    152  *  If FALSE, then the floating point context is saved when a floating
     163 *  - If FALSE, then the floating point context is saved when a floating
    153164 *  point task is switched out and restored when the next floating point
    154165 *  task is restored.  The state of the floating point registers between
    155166 *  those two operations is not specified.
    156  */
    157 
     167 *
     168 *  On the SPARC, we can disable the FPU for integer only tasks so
     169 *  it is safe to defer floating point context switches.
     170 */
    158171#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
    159172
    160 /*
     173/**
    161174 *  Does this port provide a CPU dependent IDLE task implementation?
    162175 *
    163  *  If TRUE, then the routine _CPU_Thread_Idle_body
     176 *  - If TRUE, then the routine _CPU_Thread_Idle_body
    164177 *  must be provided and is the default IDLE thread body instead of
    165178 *  _CPU_Thread_Idle_body.
    166179 *
    167  *  If FALSE, then use the generic IDLE thread body if the BSP does
     180 *  - If FALSE, then use the generic IDLE thread body if the BSP does
    168181 *  not provide one.
    169  */
    170 
     182 *
     183 *  The SPARC architecture does not have a low power or halt instruction.
     184 *  It is left to the BSP and/or CPU specific code to provide an IDLE
     185 *  thread body which is aware of low power modes.
     186 */
    171187#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
    172188
    173 /*
     189/**
    174190 *  Does the stack grow up (toward higher addresses) or down
    175191 *  (toward lower addresses)?
    176192 *
    177  *  If TRUE, then the grows upward.
    178  *  If FALSE, then the grows toward smaller addresses.
     193 *  - If TRUE, then the grows upward.
     194 *  - If FALSE, then the grows toward smaller addresses.
    179195 *
    180196 *  The stack grows to lower addresses on the SPARC.
    181197 */
    182 
    183198#define CPU_STACK_GROWS_UP               FALSE
    184199
    185 /*
     200/**
    186201 *  The following is the variable attribute used to force alignment
    187202 *  of critical data structures.  On some processors it may make
     
    193208 *  requirements.  This value was chosen to take advantages of caches.
    194209 */
    195 
    196210#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (16)))
    197211
    198 /*
     212/**
    199213 *  Define what is required to specify how the network to host conversion
    200214 *  routines are handled.
    201  */
    202 
     215 *
     216 *  The SPARC is big endian.
     217 */
    203218#define CPU_BIG_ENDIAN                           TRUE
     219
     220/**
     221 *  Define what is required to specify how the network to host conversion
     222 *  routines are handled.
     223 *
     224 *  The SPARC is NOT little endian.
     225 */
    204226#define CPU_LITTLE_ENDIAN                        FALSE
    205227
    206 /*
     228/**
    207229 *  The following defines the number of bits actually used in the
    208230 *  interrupt field of the task mode.  How those bits map to the
     
    211233 *  The SPARC has 16 interrupt levels in the PIL field of the PSR.
    212234 */
    213 
    214235#define CPU_MODES_INTERRUPT_MASK   0x0000000F
    215236
    216 /*
     237#ifndef ASM
     238/**
    217239 *  This structure represents the organization of the minimum stack frame
    218240 *  for the SPARC.  More framing information is required in certain situaions
     
    220242 *  must save floating point registers.
    221243 */
    222 
    223 #ifndef ASM
    224 
    225244typedef struct {
     245  /** This is the offset of the l0 register. */
    226246  uint32_t    l0;
     247  /** This is the offset of the l1 register. */
    227248  uint32_t    l1;
     249  /** This is the offset of the l2 register. */
    228250  uint32_t    l2;
     251  /** This is the offset of the l3 register. */
    229252  uint32_t    l3;
     253  /** This is the offset of the l4 register. */
    230254  uint32_t    l4;
     255  /** This is the offset of the l5 register. */
    231256  uint32_t    l5;
     257  /** This is the offset of the l6 register. */
    232258  uint32_t    l6;
     259  /** This is the offset of the l7 register. */
    233260  uint32_t    l7;
     261  /** This is the offset of the l0 register. */
    234262  uint32_t    i0;
     263  /** This is the offset of the i1 register. */
    235264  uint32_t    i1;
     265  /** This is the offset of the i2 register. */
    236266  uint32_t    i2;
     267  /** This is the offset of the i3 register. */
    237268  uint32_t    i3;
     269  /** This is the offset of the i4 register. */
    238270  uint32_t    i4;
     271  /** This is the offset of the i5 register. */
    239272  uint32_t    i5;
     273  /** This is the offset of the i6 register. */
    240274  uint32_t    i6_fp;
     275  /** This is the offset of the i7 register. */
    241276  uint32_t    i7;
     277  /** This is the offset of the register used to return structures. */
    242278  void       *structure_return_address;
     279
    243280  /*
    244281   *  The following are for the callee to save the register arguments in
    245282   *  should this be necessary.
    246283   */
     284  /** This is the offset of the register for saved argument 0. */
    247285  uint32_t    saved_arg0;
     286  /** This is the offset of the register for saved argument 1. */
    248287  uint32_t    saved_arg1;
     288  /** This is the offset of the register for saved argument 2. */
    249289  uint32_t    saved_arg2;
     290  /** This is the offset of the register for saved argument 3. */
    250291  uint32_t    saved_arg3;
     292  /** This is the offset of the register for saved argument 4. */
    251293  uint32_t    saved_arg4;
     294  /** This is the offset of the register for saved argument 5. */
    252295  uint32_t    saved_arg5;
     296  /** This field pads the structure so ldd and std instructions can be used. */
    253297  uint32_t    pad0;
    254298}  CPU_Minimum_stack_frame;
     
    256300#endif /* ASM */
    257301
     302/** This macro defines an offset into the stack frame for use in assembly. */
    258303#define CPU_STACK_FRAME_L0_OFFSET             0x00
     304/** This macro defines an offset into the stack frame for use in assembly. */
    259305#define CPU_STACK_FRAME_L1_OFFSET             0x04
     306/** This macro defines an offset into the stack frame for use in assembly. */
    260307#define CPU_STACK_FRAME_L2_OFFSET             0x08
     308/** This macro defines an offset into the stack frame for use in assembly. */
    261309#define CPU_STACK_FRAME_L3_OFFSET             0x0c
     310/** This macro defines an offset into the stack frame for use in assembly. */
    262311#define CPU_STACK_FRAME_L4_OFFSET             0x10
     312/** This macro defines an offset into the stack frame for use in assembly. */
    263313#define CPU_STACK_FRAME_L5_OFFSET             0x14
     314/** This macro defines an offset into the stack frame for use in assembly. */
    264315#define CPU_STACK_FRAME_L6_OFFSET             0x18
     316/** This macro defines an offset into the stack frame for use in assembly. */
    265317#define CPU_STACK_FRAME_L7_OFFSET             0x1c
     318/** This macro defines an offset into the stack frame for use in assembly. */
    266319#define CPU_STACK_FRAME_I0_OFFSET             0x20
     320/** This macro defines an offset into the stack frame for use in assembly. */
    267321#define CPU_STACK_FRAME_I1_OFFSET             0x24
     322/** This macro defines an offset into the stack frame for use in assembly. */
    268323#define CPU_STACK_FRAME_I2_OFFSET             0x28
     324/** This macro defines an offset into the stack frame for use in assembly. */
    269325#define CPU_STACK_FRAME_I3_OFFSET             0x2c
     326/** This macro defines an offset into the stack frame for use in assembly. */
    270327#define CPU_STACK_FRAME_I4_OFFSET             0x30
     328/** This macro defines an offset into the stack frame for use in assembly. */
    271329#define CPU_STACK_FRAME_I5_OFFSET             0x34
     330/** This macro defines an offset into the stack frame for use in assembly. */
    272331#define CPU_STACK_FRAME_I6_FP_OFFSET          0x38
     332/** This macro defines an offset into the stack frame for use in assembly. */
    273333#define CPU_STACK_FRAME_I7_OFFSET             0x3c
     334/** This macro defines an offset into the stack frame for use in assembly. */
    274335#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET   0x40
     336/** This macro defines an offset into the stack frame for use in assembly. */
    275337#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET     0x44
     338/** This macro defines an offset into the stack frame for use in assembly. */
    276339#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET     0x48
     340/** This macro defines an offset into the stack frame for use in assembly. */
    277341#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET     0x4c
     342/** This macro defines an offset into the stack frame for use in assembly. */
    278343#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET     0x50
     344/** This macro defines an offset into the stack frame for use in assembly. */
    279345#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET     0x54
     346/** This macro defines an offset into the stack frame for use in assembly. */
    280347#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET     0x58
     348/** This macro defines an offset into the stack frame for use in assembly. */
    281349#define CPU_STACK_FRAME_PAD0_OFFSET           0x5c
    282350
     351/** This defines the size of the minimum stack frame. */
    283352#define CPU_MINIMUM_STACK_FRAME_SIZE          0x60
    284353
    285 /*
    286  * Contexts
     354/**
     355 * @defgroup Contexts SPARC Context Structures
    287356 *
    288357 *  Generally there are 2 types of context to save.
    289  *     1. Interrupt registers to save
    290  *     2. Task level registers to save
     358 *     + Interrupt registers to save
     359 *     + Task level registers to save
    291360 *
    292361 *  This means we have the following 3 context items:
    293  *     1. task level context stuff::  Context_Control
    294  *     2. floating point task stuff:: Context_Control_fp
    295  *     3. special interrupt level context :: Context_Control_interrupt
     362 *     + task level context stuff::  Context_Control
     363 *     + floating point task stuff:: Context_Control_fp
     364 *     + special interrupt level context :: Context_Control_interrupt
    296365 *
    297366 *  On the SPARC, we are relatively conservative in that we save most
     
    302371
    303372#ifndef ASM
    304 
     373/**
     374 *  @brief SPARC Basic Context
     375 *
     376 *  @ingroup Contexts
     377 *
     378 *  This structure defines the basic integer and processor state context
     379 *  for the SPARC architecture.
     380 */
    305381typedef struct {
    306     /*
    307      *  Using a double g0_g1 will put everything in this structure on a
    308      *  double word boundary which allows us to use double word loads
    309      *  and stores safely in the context switch.
    310      */
    311     double     g0_g1;
    312     uint32_t   g2;
    313     uint32_t   g3;
    314     uint32_t   g4;
    315     uint32_t   g5;
    316     uint32_t   g6;
    317     uint32_t   g7;
    318 
    319     uint32_t   l0;
    320     uint32_t   l1;
    321     uint32_t   l2;
    322     uint32_t   l3;
    323     uint32_t   l4;
    324     uint32_t   l5;
    325     uint32_t   l6;
    326     uint32_t   l7;
    327 
    328     uint32_t   i0;
    329     uint32_t   i1;
    330     uint32_t   i2;
    331     uint32_t   i3;
    332     uint32_t   i4;
    333     uint32_t   i5;
    334     uint32_t   i6_fp;
    335     uint32_t   i7;
    336 
    337     uint32_t   o0;
    338     uint32_t   o1;
    339     uint32_t   o2;
    340     uint32_t   o3;
    341     uint32_t   o4;
    342     uint32_t   o5;
    343     uint32_t   o6_sp;
    344     uint32_t   o7;
    345 
    346     uint32_t   psr;
    347     uint32_t   isr_dispatch_disable;
     382  /**
     383   *  Using a double g0_g1 will put everything in this structure on a
     384   *  double word boundary which allows us to use double word loads
     385   *  and stores safely in the context switch.
     386   */
     387  double     g0_g1;
     388  /** This will contain the contents of the g2 register. */
     389  uint32_t   g2;
     390  /** This will contain the contents of the g3 register. */
     391  uint32_t   g3;
     392  /** This will contain the contents of the g4 register. */
     393  uint32_t   g4;
     394  /** This will contain the contents of the g5 register. */
     395  uint32_t   g5;
     396  /** This will contain the contents of the g6 register. */
     397  uint32_t   g6;
     398  /** This will contain the contents of the g7 register. */
     399  uint32_t   g7;
     400
     401  /** This will contain the contents of the l0 register. */
     402  uint32_t   l0;
     403  /** This will contain the contents of the l1 register. */
     404  uint32_t   l1;
     405  /** This will contain the contents of the l2 register. */
     406  uint32_t   l2;
     407  /** This will contain the contents of the l3 register. */
     408  uint32_t   l3;
     409  /** This will contain the contents of the l4 register. */
     410  uint32_t   l4;
     411  /** This will contain the contents of the l5 registeer.*/
     412  uint32_t   l5;
     413  /** This will contain the contents of the l6 register. */
     414  uint32_t   l6;
     415  /** This will contain the contents of the l7 register. */
     416  uint32_t   l7;
     417
     418  /** This will contain the contents of the i0 register. */
     419  uint32_t   i0;
     420  /** This will contain the contents of the i1 register. */
     421  uint32_t   i1;
     422  /** This will contain the contents of the i2 register. */
     423  uint32_t   i2;
     424  /** This will contain the contents of the i3 register. */
     425  uint32_t   i3;
     426  /** This will contain the contents of the i4 register. */
     427  uint32_t   i4;
     428  /** This will contain the contents of the i5 register. */
     429  uint32_t   i5;
     430  /** This will contain the contents of the i6 (e.g. frame pointer) register. */
     431  uint32_t   i6_fp;
     432  /** This will contain the contents of the i7 register. */
     433  uint32_t   i7;
     434
     435  /** This will contain the contents of the o0 register. */
     436  uint32_t   o0;
     437  /** This will contain the contents of the o1 register. */
     438  uint32_t   o1;
     439  /** This will contain the contents of the o2 register. */
     440  uint32_t   o2;
     441  /** This will contain the contents of the o3 register. */
     442  uint32_t   o3;
     443  /** This will contain the contents of the o4 register. */
     444  uint32_t   o4;
     445  /** This will contain the contents of the o5 register. */
     446  uint32_t   o5;
     447  /** This will contain the contents of the o6 (e.g. frame pointer) register. */
     448  uint32_t   o6_sp;
     449  /** This will contain the contents of the o7 register. */
     450  uint32_t   o7;
     451
     452  /** This will contain the contents of the processor status register. */
     453  uint32_t   psr;
     454  /**
     455   * This field is used to prevent heavy nesting of calls to _Thread_Dispatch
     456   * on an interrupted  task's stack.  This is problematic on the slower
     457   * SPARC CPU models at high interrupt rates.
     458   */
     459  uint32_t   isr_dispatch_disable;
    348460} Context_Control;
    349461
     462/**
     463 *  This macro provides a CPU independent way for RTEMS to access the
     464 *  stack pointer in a context structure. The actual name and offset is
     465 *  CPU architecture dependent.
     466 */
    350467#define _CPU_Context_Get_SP( _context ) \
    351468  (_context)->o6_sp
     
    357474 */
    358475
     476/** This macro defines an offset into the context for use in assembly. */
    359477#define G0_OFFSET    0x00
     478/** This macro defines an offset into the context for use in assembly. */
    360479#define G1_OFFSET    0x04
     480/** This macro defines an offset into the context for use in assembly. */
    361481#define G2_OFFSET    0x08
     482/** This macro defines an offset into the context for use in assembly. */
    362483#define G3_OFFSET    0x0C
     484/** This macro defines an offset into the context for use in assembly. */
    363485#define G4_OFFSET    0x10
     486/** This macro defines an offset into the context for use in assembly. */
    364487#define G5_OFFSET    0x14
     488/** This macro defines an offset into the context for use in assembly. */
    365489#define G6_OFFSET    0x18
     490/** This macro defines an offset into the context for use in assembly. */
    366491#define G7_OFFSET    0x1C
    367492
     493/** This macro defines an offset into the context for use in assembly. */
    368494#define L0_OFFSET    0x20
     495/** This macro defines an offset into the context for use in assembly. */
    369496#define L1_OFFSET    0x24
     497/** This macro defines an offset into the context for use in assembly. */
    370498#define L2_OFFSET    0x28
     499/** This macro defines an offset into the context for use in assembly. */
    371500#define L3_OFFSET    0x2C
     501/** This macro defines an offset into the context for use in assembly. */
    372502#define L4_OFFSET    0x30
     503/** This macro defines an offset into the context for use in assembly. */
    373504#define L5_OFFSET    0x34
     505/** This macro defines an offset into the context for use in assembly. */
    374506#define L6_OFFSET    0x38
     507/** This macro defines an offset into the context for use in assembly. */
    375508#define L7_OFFSET    0x3C
    376509
     510/** This macro defines an offset into the context for use in assembly. */
    377511#define I0_OFFSET    0x40
     512/** This macro defines an offset into the context for use in assembly. */
    378513#define I1_OFFSET    0x44
     514/** This macro defines an offset into the context for use in assembly. */
    379515#define I2_OFFSET    0x48
     516/** This macro defines an offset into the context for use in assembly. */
    380517#define I3_OFFSET    0x4C
     518/** This macro defines an offset into the context for use in assembly. */
    381519#define I4_OFFSET    0x50
     520/** This macro defines an offset into the context for use in assembly. */
    382521#define I5_OFFSET    0x54
     522/** This macro defines an offset into the context for use in assembly. */
    383523#define I6_FP_OFFSET 0x58
     524/** This macro defines an offset into the context for use in assembly. */
    384525#define I7_OFFSET    0x5C
    385526
     527/** This macro defines an offset into the context for use in assembly. */
    386528#define O0_OFFSET    0x60
     529/** This macro defines an offset into the context for use in assembly. */
    387530#define O1_OFFSET    0x64
     531/** This macro defines an offset into the context for use in assembly. */
    388532#define O2_OFFSET    0x68
     533/** This macro defines an offset into the context for use in assembly. */
    389534#define O3_OFFSET    0x6C
     535/** This macro defines an offset into the context for use in assembly. */
    390536#define O4_OFFSET    0x70
     537/** This macro defines an offset into the context for use in assembly. */
    391538#define O5_OFFSET    0x74
     539/** This macro defines an offset into the context for use in assembly. */
    392540#define O6_SP_OFFSET 0x78
     541/** This macro defines an offset into the context for use in assembly. */
    393542#define O7_OFFSET    0x7C
    394543
     544/** This macro defines an offset into the context for use in assembly. */
    395545#define PSR_OFFSET   0x80
     546/** This macro defines an offset into the context for use in assembly. */
    396547#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x84
    397548
     549/** This defines the size of the context area for use in assembly. */
    398550#define CONTEXT_CONTROL_SIZE 0x88
    399551
    400 /*
    401  *  The floating point context area.
    402  */
    403 
    404552#ifndef ASM
    405 
     553/**
     554 *  @brief SPARC Basic Context
     555 *
     556 *  @ingroup Contexts
     557 *
     558 *  This structure defines floating point context area.
     559 */
    406560typedef struct {
    407     double      f0_f1;
    408     double      f2_f3;
    409     double      f4_f5;
    410     double      f6_f7;
    411     double      f8_f9;
    412     double      f10_f11;
    413     double      f12_f13;
    414     double      f14_f15;
    415     double      f16_f17;
    416     double      f18_f19;
    417     double      f20_f21;
    418     double      f22_f23;
    419     double      f24_f25;
    420     double      f26_f27;
    421     double      f28_f29;
    422     double      f30_f31;
    423     uint32_t    fsr;
     561  /** This will contain the contents of the f0 and f1 register. */
     562  double      f0_f1;
     563  /** This will contain the contents of the f2 and f3 register. */
     564  double      f2_f3;
     565  /** This will contain the contents of the f4 and f5 register. */
     566  double      f4_f5;
     567  /** This will contain the contents of the f6 and f7 register. */
     568  double      f6_f7;
     569  /** This will contain the contents of the f8 and f9 register. */
     570  double      f8_f9;
     571  /** This will contain the contents of the f10 and f11 register. */
     572  double      f10_f11;
     573  /** This will contain the contents of the f12 and f13 register. */
     574  double      f12_f13;
     575  /** This will contain the contents of the f14 and f15 register. */
     576  double      f14_f15;
     577  /** This will contain the contents of the f16 and f17 register. */
     578  double      f16_f17;
     579  /** This will contain the contents of the f18 and f19 register. */
     580  double      f18_f19;
     581  /** This will contain the contents of the f20 and f21 register. */
     582  double      f20_f21;
     583  /** This will contain the contents of the f22 and f23 register. */
     584  double      f22_f23;
     585  /** This will contain the contents of the f24 and f25 register. */
     586  double      f24_f25;
     587  /** This will contain the contents of the f26 and f27 register. */
     588  double      f26_f27;
     589  /** This will contain the contents of the f28 and f29 register. */
     590  double      f28_f29;
     591  /** This will contain the contents of the f30 and f31 register. */
     592  double      f30_f31;
     593  /** This will contain the contents of the floating point status register. */
     594  uint32_t    fsr;
    424595} Context_Control_fp;
    425596
     
    430601 */
    431602
     603/** This macro defines an offset into the FPU context for use in assembly. */
    432604#define FO_F1_OFFSET     0x00
     605/** This macro defines an offset into the FPU context for use in assembly. */
    433606#define F2_F3_OFFSET     0x08
     607/** This macro defines an offset into the FPU context for use in assembly. */
    434608#define F4_F5_OFFSET     0x10
     609/** This macro defines an offset into the FPU context for use in assembly. */
    435610#define F6_F7_OFFSET     0x18
     611/** This macro defines an offset into the FPU context for use in assembly. */
    436612#define F8_F9_OFFSET     0x20
     613/** This macro defines an offset into the FPU context for use in assembly. */
    437614#define F1O_F11_OFFSET   0x28
     615/** This macro defines an offset into the FPU context for use in assembly. */
    438616#define F12_F13_OFFSET   0x30
     617/** This macro defines an offset into the FPU context for use in assembly. */
    439618#define F14_F15_OFFSET   0x38
     619/** This macro defines an offset into the FPU context for use in assembly. */
    440620#define F16_F17_OFFSET   0x40
     621/** This macro defines an offset into the FPU context for use in assembly. */
    441622#define F18_F19_OFFSET   0x48
     623/** This macro defines an offset into the FPU context for use in assembly. */
    442624#define F2O_F21_OFFSET   0x50
     625/** This macro defines an offset into the FPU context for use in assembly. */
    443626#define F22_F23_OFFSET   0x58
     627/** This macro defines an offset into the FPU context for use in assembly. */
    444628#define F24_F25_OFFSET   0x60
     629/** This macro defines an offset into the FPU context for use in assembly. */
    445630#define F26_F27_OFFSET   0x68
     631/** This macro defines an offset into the FPU context for use in assembly. */
    446632#define F28_F29_OFFSET   0x70
     633/** This macro defines an offset into the FPU context for use in assembly. */
    447634#define F3O_F31_OFFSET   0x78
     635/** This macro defines an offset into the FPU context for use in assembly. */
    448636#define FSR_OFFSET       0x80
    449637
     638/** This defines the size of the FPU context area for use in assembly. */
    450639#define CONTEXT_CONTROL_FP_SIZE 0x84
    451640
    452641#ifndef ASM
    453642
    454 /*
     643/**
     644 *  @brief Interrupt Stack Frame (ISF)
     645 *
    455646 *  Context saved on stack for an interrupt.
    456647 *
    457  *  NOTE:  The PSR, PC, and NPC are only saved in this structure for the
    458  *         benefit of the user's handler.
    459  */
    460 
     648 *  @note The PSR, PC, and NPC are only saved in this structure for the
     649 *        benefit of the user's handler.
     650 */
    461651typedef struct {
     652  /** On an interrupt, we must save the minimum stack frame. */
    462653  CPU_Minimum_stack_frame  Stack_frame;
     654  /** This is the offset of the PSR on an ISF. */
    463655  uint32_t                 psr;
     656  /** This is the offset of the XXX on an ISF. */
    464657  uint32_t                 pc;
     658  /** This is the offset of the XXX on an ISF. */
    465659  uint32_t                 npc;
     660  /** This is the offset of the g1 register on an ISF. */
    466661  uint32_t                 g1;
     662  /** This is the offset of the g2 register on an ISF. */
    467663  uint32_t                 g2;
     664  /** This is the offset of the g3 register on an ISF. */
    468665  uint32_t                 g3;
     666  /** This is the offset of the g4 register on an ISF. */
    469667  uint32_t                 g4;
     668  /** This is the offset of the g5 register on an ISF. */
    470669  uint32_t                 g5;
     670  /** This is the offset of the g6 register on an ISF. */
    471671  uint32_t                 g6;
     672  /** This is the offset of the g7 register on an ISF. */
    472673  uint32_t                 g7;
     674  /** This is the offset of the i0 register on an ISF. */
    473675  uint32_t                 i0;
     676  /** This is the offset of the i1 register on an ISF. */
    474677  uint32_t                 i1;
     678  /** This is the offset of the i2 register on an ISF. */
    475679  uint32_t                 i2;
     680  /** This is the offset of the i3 register on an ISF. */
    476681  uint32_t                 i3;
     682  /** This is the offset of the i4 register on an ISF. */
    477683  uint32_t                 i4;
     684  /** This is the offset of the i5 register on an ISF. */
    478685  uint32_t                 i5;
     686  /** This is the offset of the i6 register on an ISF. */
    479687  uint32_t                 i6_fp;
     688  /** This is the offset of the i7 register on an ISF. */
    480689  uint32_t                 i7;
     690  /** This is the offset of the y register on an ISF. */
    481691  uint32_t                 y;
     692  /** This is the offset of the tpc register on an ISF. */
    482693  uint32_t                 tpc;
    483694} CPU_Interrupt_frame;
     
    489700 */
    490701
     702/** This macro defines an offset into the ISF for use in assembly. */
    491703#define ISF_STACK_FRAME_OFFSET 0x00
     704/** This macro defines an offset into the ISF for use in assembly. */
    492705#define ISF_PSR_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x00
     706/** This macro defines an offset into the ISF for use in assembly. */
    493707#define ISF_PC_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x04
     708/** This macro defines an offset into the ISF for use in assembly. */
    494709#define ISF_NPC_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x08
     710/** This macro defines an offset into the ISF for use in assembly. */
    495711#define ISF_G1_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x0c
     712/** This macro defines an offset into the ISF for use in assembly. */
    496713#define ISF_G2_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x10
     714/** This macro defines an offset into the ISF for use in assembly. */
    497715#define ISF_G3_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x14
     716/** This macro defines an offset into the ISF for use in assembly. */
    498717#define ISF_G4_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x18
     718/** This macro defines an offset into the ISF for use in assembly. */
    499719#define ISF_G5_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x1c
     720/** This macro defines an offset into the ISF for use in assembly. */
    500721#define ISF_G6_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x20
     722/** This macro defines an offset into the ISF for use in assembly. */
    501723#define ISF_G7_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x24
     724/** This macro defines an offset into the ISF for use in assembly. */
    502725#define ISF_I0_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x28
     726/** This macro defines an offset into the ISF for use in assembly. */
    503727#define ISF_I1_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x2c
     728/** This macro defines an offset into the ISF for use in assembly. */
    504729#define ISF_I2_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x30
     730/** This macro defines an offset into the ISF for use in assembly. */
    505731#define ISF_I3_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x34
     732/** This macro defines an offset into the ISF for use in assembly. */
    506733#define ISF_I4_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x38
     734/** This macro defines an offset into the ISF for use in assembly. */
    507735#define ISF_I5_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x3c
     736/** This macro defines an offset into the ISF for use in assembly. */
    508737#define ISF_I6_FP_OFFSET       CPU_MINIMUM_STACK_FRAME_SIZE + 0x40
     738/** This macro defines an offset into the ISF for use in assembly. */
    509739#define ISF_I7_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x44
     740/** This macro defines an offset into the ISF for use in assembly. */
    510741#define ISF_Y_OFFSET           CPU_MINIMUM_STACK_FRAME_SIZE + 0x48
     742/** This macro defines an offset into the ISF for use in assembly. */
    511743#define ISF_TPC_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c
    512744
    513 #define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0x50
     745/** This defines the size of the ISF area for use in assembly. */
     746#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE \
     747        CPU_MINIMUM_STACK_FRAME_SIZE + 0x50
     748
    514749#ifndef ASM
    515 /*
     750/**
    516751 *  This variable is contains the initialize context for the FP unit.
    517752 *  It is filled in by _CPU_Initialize and copied into the task's FP
    518753 *  context area during _CPU_Context_Initialize.
    519754 */
    520 
    521755SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT;
    522756
    523 /*
     757/**
    524758 *  This flag is context switched with each thread.  It indicates
    525759 *  that THIS thread has an _ISR_Dispatch stack frame on its stack.
     
    527761 *  attempts on a previously interrupted thread's stack.
    528762 */
    529 
    530763SCORE_EXTERN volatile uint32_t _CPU_ISR_Dispatch_disable;
    531764
    532 /*
     765/**
    533766 *  The following type defines an entry in the SPARC's trap table.
    534767 *
    535  *  NOTE: The instructions chosen are RTEMS dependent although one is
     768 *  @note The instructions chosen are RTEMS dependent although one is
    536769 *        obligated to use two of the four instructions to perform a
    537770 *        long jump.  The other instructions load one register with the
    538771 *        trap type (a.k.a. vector) and another with the psr.
    539772 */
    540 
    541773typedef struct {
    542   uint32_t     mov_psr_l0;                     /* mov   %psr, %l0           */
    543   uint32_t     sethi_of_handler_to_l4;         /* sethi %hi(_handler), %l4  */
    544   uint32_t     jmp_to_low_of_handler_plus_l4;  /* jmp   %l4 + %lo(_handler) */
    545   uint32_t     mov_vector_l3;                  /* mov   _vector, %l3        */
     774  /** This will contain a "mov %psr, %l0" instruction. */
     775  uint32_t     mov_psr_l0;
     776  /** This will contain a "sethi %hi(_handler), %l4" instruction. */
     777  uint32_t     sethi_of_handler_to_l4;
     778  /** This will contain a "jmp %l4 + %lo(_handler)" instruction. */
     779  uint32_t     jmp_to_low_of_handler_plus_l4;
     780  /** This will contain a " mov _vector, %l3" instruction. */
     781  uint32_t     mov_vector_l3;
    546782} CPU_Trap_table_entry;
    547783
    548 /*
     784/**
    549785 *  This is the set of opcodes for the instructions loaded into a trap
    550786 *  table entry.  The routine which installs a handler is responsible
     
    555791 *  must be filled in when the handler is installed.
    556792 */
    557 
    558793extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
    559794
    560 /*
     795/**
    561796 *  The size of the floating point context area.
    562797 */
    563 
    564798#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
    565799
    566800#endif
    567801
    568 /*
     802/**
    569803 *  Amount of extra stack (above minimum stack size) required by
    570804 *  MPCI receive server thread.  Remember that in a multiprocessor
    571805 *  system this thread must exist and be able to process all directives.
    572806 */
    573 
    574807#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
    575808
    576 /*
     809/**
    577810 *  This defines the number of entries in the ISR_Vector_table managed
    578811 *  by the executive.
     
    597830 *  address.
    598831 */
    599 
    600832#define CPU_INTERRUPT_NUMBER_OF_VECTORS     256
     833
     834/**
     835 * The SPARC has 256 vectors but the port treats 256-512 as synchronous
     836 * traps.
     837 */
    601838#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511
    602839
     840/**
     841 *  This is the bit step in a vector number to indicate it is being installed
     842 *  as a synchronous trap.
     843 */
    603844#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK     0x100
     845
     846/**
     847 *  This macro indicates that @a _trap as an asynchronous trap.
     848 */
    604849#define SPARC_ASYNCHRONOUS_TRAP( _trap )    (_trap)
     850
     851/**
     852 *  This macro indicates that @a _trap as a synchronous trap.
     853 */
    605854#define SPARC_SYNCHRONOUS_TRAP( _trap )     ((_trap) + 256 )
    606855
     856/**
     857 * This macro returns the real hardware vector number associated with @a _trap.
     858 */
    607859#define SPARC_REAL_TRAP_NUMBER( _trap )     ((_trap) % 256)
    608860
    609 /*
     861/**
    610862 *  This is defined if the port has a special way to report the ISR nesting
    611863 *  level.  Most ports maintain the variable _ISR_Nest_level.
    612864 */
    613 
    614865#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
    615866
    616 /*
     867/**
    617868 *  Should be large enough to run all tests.  This ensures
    618869 *  that a "reasonable" small application should not have any problems.
     
    622873 *  stack frame.
    623874 */
    624 
    625875#define CPU_STACK_MINIMUM_SIZE  (1024*4)
    626876
    627 /*
     877/**
    628878 *  CPU's worst alignment requirement for data types on a byte boundary.  This
    629879 *  alignment does not take into account the requirements for the stack.
     
    631881 *  On the SPARC, this is required for double word loads and stores.
    632882 */
    633 
    634883#define CPU_ALIGNMENT      8
    635884
    636 /*
     885/**
    637886 *  This number corresponds to the byte alignment requirement for the
    638887 *  heap handler.  This alignment requirement may be stricter than that
     
    642891 *  then this should be set to CPU_ALIGNMENT.
    643892 *
    644  *  NOTE:  This does not have to be a power of 2.  It does have to
     893 *  @note  This does not have to be a power of 2.  It does have to
    645894 *         be greater or equal to than CPU_ALIGNMENT.
    646895 */
    647 
    648896#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
    649897
    650 /*
     898/**
    651899 *  This number corresponds to the byte alignment requirement for memory
    652900 *  buffers allocated by the partition manager.  This alignment requirement
     
    656904 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
    657905 *
    658  *  NOTE:  This does not have to be a power of 2.  It does have to
     906 *  @note  This does not have to be a power of 2.  It does have to
    659907 *         be greater or equal to than CPU_ALIGNMENT.
    660908 */
    661 
    662909#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
    663910
    664 /*
     911/**
    665912 *  This number corresponds to the byte alignment requirement for the
    666913 *  stack.  This alignment requirement may be stricter than that for the
     
    668915 *  is strict enough for the stack, then this should be set to 0.
    669916 *
    670  *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
     917 *  @note  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
    671918 *
    672919 *  The alignment restrictions for the SPARC are not that strict but this
     
    675922 *  and stores.
    676923 */
    677 
    678924#define CPU_STACK_ALIGNMENT        16
    679925
     
    684930 */
    685931
    686 /*
     932/**
    687933 *  Support routine to initialize the RTEMS vector table after it is allocated.
    688934 */
    689 
    690935#define _CPU_Initialize_vectors()
    691936
    692 /*
     937/**
    693938 *  Disable all interrupts for a critical section.  The previous
    694939 *  level is returned in _level.
    695940 */
    696 
    697941#define _CPU_ISR_Disable( _level ) \
    698942  (_level) = sparc_disable_interrupts()
    699943
    700 /*
     944/**
    701945 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
    702946 *  This indicates the end of a critical section.  The parameter
    703947 *  _level is not modified.
    704948 */
    705 
    706949#define _CPU_ISR_Enable( _level ) \
    707950  sparc_enable_interrupts( _level )
    708951
    709 /*
     952/**
    710953 *  This temporarily restores the interrupt to _level before immediately
    711954 *  disabling them again.  This is used to divide long critical
     
    713956 *  modified.
    714957 */
    715 
    716958#define _CPU_ISR_Flash( _level ) \
    717959  sparc_flash_interrupts( _level )
    718960
    719 /*
     961/**
    720962 *  Map interrupt level in task mode onto the hardware that the CPU
    721963 *  actually provides.  Currently, interrupt levels which do not
    722964 *  map onto the CPU in a straight fashion are undefined.
    723965 */
    724 
    725966#define _CPU_ISR_Set_level( _newlevel ) \
    726967   sparc_enable_interrupts( _newlevel << 8)
    727968
     969/**
     970 *  @brief Obtain the Current Interrupt Disable Level
     971 *
     972 *  This method is invoked to return the current interrupt disable level.
     973 *
     974 *  @return This method returns the current interrupt disable level.
     975 */
    728976uint32_t   _CPU_ISR_Get_level( void );
    729977
     
    732980/* Context handler macros */
    733981
    734 /*
     982/**
    735983 *  Initialize the context to a state suitable for starting a
    736984 *  task after a context restore operation.  Generally, this
    737985 *  involves:
    738986 *
    739  *     - setting a starting address
    740  *     - preparing the stack
    741  *     - preparing the stack and frame pointers
    742  *     - setting the proper interrupt level in the context
    743  *     - initializing the floating point context
    744  *
    745  *  NOTE:  Implemented as a subroutine for the SPARC port.
    746  */
    747 
     987 *  - setting a starting address
     988 *  - preparing the stack
     989 *  - preparing the stack and frame pointers
     990 *  - setting the proper interrupt level in the context
     991 *  - initializing the floating point context
     992 *
     993 * @param[in] the_context points to the context area
     994 * @param[in] stack_base is the low address of the allocated stack area
     995 * @param[in] size is the size of the stack area in bytes
     996 * @param[in] new_level is the interrupt level for the task
     997 * @param[in] entry_point is the task's entry point
     998 * @param[in] is_fp is set to TRUE if the task is a floating point task
     999 *
     1000 *  @note  Implemented as a subroutine for the SPARC port.
     1001 */
    7481002void _CPU_Context_Initialize(
    7491003  Context_Control  *the_context,
     
    7551009);
    7561010
    757 /*
     1011/**
    7581012 *  This macro is invoked from _Thread_Handler to do whatever CPU
    7591013 *  specific magic is required that must be done in the context of
     
    7681022 *  _Thread_Handler is known to start with SAVE.
    7691023 */
    770 
    7711024#define _CPU_Context_Initialization_at_thread_begin() \
    7721025  do { \
     
    7741027  } while (0)
    7751028
    776 /*
     1029/**
    7771030 *  This routine is responsible for somehow restarting the currently
    7781031 *  executing task.
     
    7821035 *  of the context switch.
    7831036 */
    784 
    7851037#define _CPU_Context_Restart_self( _the_context ) \
    7861038   _CPU_Context_restore( (_the_context) );
    7871039
    788 /*
     1040/**
    7891041 *  The FP context area for the SPARC is a simple structure and nothing
    7901042 *  special is required to find the "starting load point"
    7911043 */
    792 
    7931044#define _CPU_Context_Fp_start( _base, _offset ) \
    7941045   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
    7951046
    796 /*
     1047/**
    7971048 *  This routine initializes the FP context area passed to it to.
    7981049 *
     
    8021053 *  context.
    8031054 */
    804 
    8051055#define _CPU_Context_Initialize_fp( _destination ) \
    8061056  do { \
     
    8121062/* Fatal Error manager macros */
    8131063
    814 /*
     1064/**
    8151065 *  This routine copies _error into a known place -- typically a stack
    8161066 *  location or a register, optionally disables interrupts, and
    8171067 *  halts/stops the CPU.
    8181068 */
    819 
    8201069#define _CPU_Fatal_halt( _error ) \
    8211070  do { \
     
    8311080/* Bitfield handler macros */
    8321081
    833 /*
    834  *  The SPARC port uses the generic C algorithm for bitfield scan if the
    835  *  CPU model does not have a scan instruction.
    836  */
    837 
    8381082#if ( SPARC_HAS_BITSCAN == 0 )
    839 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
    840 #define CPU_USE_GENERIC_BITFIELD_DATA TRUE
     1083  /**
     1084   *  The SPARC port uses the generic C algorithm for bitfield scan if the
     1085   *  CPU model does not have a scan instruction.
     1086   */
     1087  #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
     1088  /**
     1089   *  The SPARC port uses the generic C algorithm for bitfield scan if the
     1090   *  CPU model does not have a scan instruction.  Thus is needs the generic
     1091   *  data table used by that algorithm.
     1092   */
     1093  #define CPU_USE_GENERIC_BITFIELD_DATA TRUE
    8411094#else
    842 #error "scan instruction not currently supported by RTEMS!!"
     1095  #error "scan instruction not currently supported by RTEMS!!"
    8431096#endif
    8441097
    8451098/* end of Bitfield handler macros */
    8461099
    847 /* Priority handler handler macros */
    848 
    849 /*
    850  *  The SPARC port uses the generic C algorithm for bitfield scan if the
    851  *  CPU model does not have a scan instruction.
    852  */
    853 
    854 #if ( SPARC_HAS_BITSCAN == 1 )
    855 #error "scan instruction not currently supported by RTEMS!!"
    856 #endif
    857 
    858 /* end of Priority handler macros */
    859 
    8601100/* functions */
    8611101
    862 /*
    863  *  _CPU_Initialize
     1102/**
     1103 *  @brief SPARC Specific Initialization
    8641104 *
    8651105 *  This routine performs CPU dependent initialization.
    8661106 */
    867 
    8681107void _CPU_Initialize(void);
    8691108
    870 /*
    871  *  _CPU_ISR_install_raw_handler
    872  *
    873  *  This routine installs new_handler to be directly called from the trap
     1109/**
     1110 *  @brief SPARC Specific Raw ISR Installer
     1111 *
     1112 *  This routine installs @a new_handler to be directly called from the trap
    8741113 *  table.
    875  */
    876 
     1114 *
     1115 *  @param[in] vector is the vector number
     1116 *  @param[in] new_handler is the new ISR handler
     1117 *  @param[in] old_handler will contain the old ISR handler
     1118 */
    8771119void _CPU_ISR_install_raw_handler(
    8781120  uint32_t    vector,
     
    8811123);
    8821124
    883 /*
    884  *  _CPU_ISR_install_vector
     1125/**
     1126 *  @brief SPARC Specific RTEMS ISR Installer
    8851127 *
    8861128 *  This routine installs an interrupt vector.
     1129 *
     1130 *  @param[in] vector is the vector number
     1131 *  @param[in] new_handler is the new ISR handler
     1132 *  @param[in] old_handler will contain the old ISR handler
    8871133 */
    8881134
     
    8931139);
    8941140
    895 #if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
    896 
    897 /*
    898  *  _CPU_Thread_Idle_body
    899  *
    900  *  Some SPARC implementations have low power, sleep, or idle modes.  This
    901  *  tries to take advantage of those models.
    902  */
    903 
    904 void *_CPU_Thread_Idle_body( uintptr_t ignored );
    905 
    906 #endif /* CPU_PROVIDES_IDLE_THREAD_BODY */
    907 
    908 /*
    909  *  _CPU_Context_switch
     1141/**
     1142 *  @brief SPARC Specific Context Switch
    9101143 *
    9111144 *  This routine switches from the run context to the heir context.
    912  */
    913 
     1145 *
     1146 *  @param[in] run is the currently executing thread
     1147 *  @param[in] heir will become the currently executing thread
     1148 */
    9141149void _CPU_Context_switch(
    9151150  Context_Control  *run,
     
    9171152);
    9181153
    919 /*
    920  *  _CPU_Context_restore
     1154/**
     1155 *  @brief SPARC Specific Context Restore
    9211156 *
    9221157 *  This routine is generally used only to restart self in an
    9231158 *  efficient manner.
    924  */
    925 
     1159 *
     1160 *  @param[in] new_context is the context to restore
     1161 */
    9261162void _CPU_Context_restore(
    9271163  Context_Control *new_context
     
    9291165
    9301166#if defined(RTEMS_SMP)
    931   /*
    932    *  _CPU_Context_switch_to_first_task_smp
     1167  /**
     1168   *  @brief SPARC Specific Method to Switch to First Task
    9331169   *
    9341170   *  This routine is only used to switch to the first task on a
     
    9361172   *  flush all the windows and, in fact, this can be dangerous
    9371173   *  as they may or may not be initialized properly.
     1174   *
     1175   *  @param[in] new_context is the context to restore
    9381176   */
    9391177  void _CPU_Context_switch_to_first_task_smp(
     
    9411179  );
    9421180
    943   /* address space 1 is uncacheable */
     1181  /**
     1182   * Macro to access memory and bypass the cache.
     1183   *
     1184   * @note address space 1 is uncacheable
     1185   */
    9441186  #define SMP_CPU_SWAP( _address, _value, _previous ) \
    9451187    do { \
     
    9541196      _previous = _val; \
    9551197    } while (0)
    956 
    9571198#endif
    9581199
    959 /*
    960  *  _CPU_Context_save_fp
     1200/**
     1201 *  @brief SPARC Specific Save FPU Method
    9611202 *
    9621203 *  This routine saves the floating point context passed to it.
    963  */
    964 
     1204 *
     1205 *  @param[in] fp_context_ptr is the area to save into
     1206 */
    9651207void _CPU_Context_save_fp(
    9661208  Context_Control_fp **fp_context_ptr
    9671209);
    9681210
    969 /*
    970  *  _CPU_Context_restore_fp
     1211/**
     1212 *  @brief SPARC Specific Rstore FPU Method
    9711213 *
    9721214 *  This routine restores the floating point context passed to it.
    973  */
    974 
     1215 *
     1216 *  @param[in] fp_context_ptr is the area to restore from
     1217 */
    9751218void _CPU_Context_restore_fp(
    9761219  Context_Control_fp **fp_context_ptr
    9771220);
    9781221
    979 
    980 /*
    981  *  CPU_swap_u32
     1222/**
     1223 *  @brief SPARC Specific Method to Endian Swap an uint32_t
    9821224 *
    9831225 *  The following routine swaps the endian format of an unsigned int.
    9841226 *  It must be static because it is referenced indirectly.
     1227 *
     1228 *  @param[in] value is the value to endian swap
    9851229 *
    9861230 *  This version will work on any processor, but if you come across a better
     
    9881232 *  entity as shown below is not any more efficient on the SPARC.
    9891233 *
    990  *     swap least significant two bytes with 16-bit rotate
    991  *     swap upper and lower 16-bits
    992  *     swap most significant two bytes with 16-bit rotate
     1234 *     - swap least significant two bytes with 16-bit rotate
     1235 *     - swap upper and lower 16-bits
     1236 *     - swap most significant two bytes with 16-bit rotate
    9931237 *
    9941238 *  It is not obvious how the SPARC can do significantly better than the
     
    9961240 *  following code at optimization level four (i.e. -O4).
    9971241 */
    998 
    9991242static inline uint32_t CPU_swap_u32(
    10001243  uint32_t value
     
    10121255}
    10131256
     1257/**
     1258 *  @brief SPARC Specific Method to Endian Swap an uint16_t
     1259 *
     1260 *  The following routine swaps the endian format of a uint16_t.
     1261 *
     1262 *  @param[in] value is the value to endian swap
     1263 */
    10141264#define CPU_swap_u16( value ) \
    10151265  (((value&0xff) << 8) | ((value >> 8)&0xff))
  • cpukit/score/cpu/sparc/rtems/score/sparc.h

    rb375f06 r4bafde5  
    11/**
    22 * @file rtems/score/sparc.h
     3 *
     4 * This file contains the information required to build
     5 * RTEMS for a particular member of the SPARC family.  It does
     6 * this by setting variables to indicate which implementation
     7 * dependent features are present in a particular member
     8 * of the family.
    39 */
    410
    511/*
    6  *  This include file contains information pertaining to the SPARC
    7  *  processor family.
    8  *
    9  *  COPYRIGHT (c) 1989-1999.
     12 *  COPYRIGHT (c) 1989-2011.
    1013 *  On-Line Applications Research Corporation (OAR).
    1114 *
     
    2528
    2629/*
    27  *  This file contains the information required to build
    28  *  RTEMS for a particular member of the "sparc" family.  It does
    29  *  this by setting variables to indicate which implementation
    30  *  dependent features are present in a particular member
    31  *  of the family.
    3230 *
    3331 *  Currently recognized feature flags:
     
    4644 */
    4745
    48 /*
     46/**
    4947 *  Some higher end SPARCs have a bitscan instructions. It would
    5048 *  be nice to take advantage of them.  Right now, there is no
     
    5250 *  that is based on this feature flag.
    5351 */
    54 
    5552#define SPARC_HAS_BITSCAN                0
    5653
    57 /*
     54/**
    5855 *  This should be OK until a port to a higher end SPARC processor
    5956 *  is made that has more than 8 register windows.  If this cannot
     
    6158 *  cpu_asm.S code that depends on this will have to move to libcpu.
    6259 */
    63 
    6460#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
    6561
    66 /*
    67  *  This should be determined based on some soft float derived
    68  *  cpp predefine but gcc does not currently give us that information.
    69  */
    70 
    71 
     62/**
     63 *  This macro indicates whether this multilib variation has hardware
     64 *  floating point or not.  We use the gcc cpp predefine _SOFT_FLOAT
     65 *  to determine that.
     66 */
    7267#if defined(_SOFT_FLOAT)
    73 #define SPARC_HAS_FPU 0
     68  #define SPARC_HAS_FPU 0
    7469#else
    75 #define SPARC_HAS_FPU 1
    76 #endif
    77 
     70  #define SPARC_HAS_FPU 1
     71#endif
     72
     73/**
     74 *  This macro contains a string describing the multilib variant being
     75 *  build.
     76 */
    7877#if SPARC_HAS_FPU
    79 #define CPU_MODEL_NAME "w/FPU"
     78  #define CPU_MODEL_NAME "w/FPU"
    8079#else
    81 #define CPU_MODEL_NAME "w/soft-float"
    82 #endif
    83 
    84 /*
     80  #define CPU_MODEL_NAME "w/soft-float"
     81#endif
     82
     83/**
    8584 *  Define the name of the CPU family.
    8685 */
    87 
    8886#define CPU_NAME "SPARC"
    8987
     
    9290 */
    9391
    94 /*
     92/**
    9593 *  PSR masks and starting bit positions
    9694 *
    97  *  NOTE: Reserved bits are ignored.
    98  */
    99 
     95 *  @note Reserved bits are ignored.
     96 */
    10097#if (SPARC_NUMBER_OF_REGISTER_WINDOWS == 8)
    101 #define SPARC_PSR_CWP_MASK               0x07   /* bits  0 -  4 */
     98  #define SPARC_PSR_CWP_MASK               0x07   /* bits  0 -  4 */
    10299#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 16)
    103 #define SPARC_PSR_CWP_MASK               0x0F   /* bits  0 -  4 */
     100  #define SPARC_PSR_CWP_MASK               0x0F   /* bits  0 -  4 */
    104101#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 32)
    105 #define SPARC_PSR_CWP_MASK               0x1F   /* bits  0 -  4 */
     102  #define SPARC_PSR_CWP_MASK               0x1F   /* bits  0 -  4 */
    106103#else
    107 #error "Unsupported number of register windows for this cpu"
    108 #endif
    109 
     104  #error "Unsupported number of register windows for this cpu"
     105#endif
     106
     107/** This constant is a mask for the ET bits in the PSR. */
    110108#define SPARC_PSR_ET_MASK   0x00000020   /* bit   5 */
     109/** This constant is a mask for the PS bits in the PSR. */
    111110#define SPARC_PSR_PS_MASK   0x00000040   /* bit   6 */
     111/** This constant is a mask for the S bits in the PSR. */
    112112#define SPARC_PSR_S_MASK    0x00000080   /* bit   7 */
     113/** This constant is a mask for the PIL bits in the PSR. */
    113114#define SPARC_PSR_PIL_MASK  0x00000F00   /* bits  8 - 11 */
     115/** This constant is a mask for the EF bits in the PSR. */
    114116#define SPARC_PSR_EF_MASK   0x00001000   /* bit  12 */
     117/** This constant is a mask for the EC bits in the PSR. */
    115118#define SPARC_PSR_EC_MASK   0x00002000   /* bit  13 */
     119/** This constant is a mask for the ICC bits in the PSR. */
    116120#define SPARC_PSR_ICC_MASK  0x00F00000   /* bits 20 - 23 */
     121/** This constant is a mask for the VER bits in the PSR. */
    117122#define SPARC_PSR_VER_MASK  0x0F000000   /* bits 24 - 27 */
     123/** This constant is a mask for the IMPL bits in the PSR. */
    118124#define SPARC_PSR_IMPL_MASK 0xF0000000   /* bits 28 - 31 */
    119125
     126/** This constant is the starting bit position of the CWP in the PSR. */
    120127#define SPARC_PSR_CWP_BIT_POSITION   0   /* bits  0 -  4 */
     128/** This constant is the starting bit position of the ET in the PSR. */
    121129#define SPARC_PSR_ET_BIT_POSITION    5   /* bit   5 */
     130/** This constant is the starting bit position of the PS in the PSR. */
    122131#define SPARC_PSR_PS_BIT_POSITION    6   /* bit   6 */
     132/** This constant is the starting bit position of the S in the PSR. */
    123133#define SPARC_PSR_S_BIT_POSITION     7   /* bit   7 */
     134/** This constant is the starting bit position of the PIL in the PSR. */
    124135#define SPARC_PSR_PIL_BIT_POSITION   8   /* bits  8 - 11 */
     136/** This constant is the starting bit position of the EF in the PSR. */
    125137#define SPARC_PSR_EF_BIT_POSITION   12   /* bit  12 */
     138/** This constant is the starting bit position of the EC in the PSR. */
    126139#define SPARC_PSR_EC_BIT_POSITION   13   /* bit  13 */
     140/** This constant is the starting bit position of the ICC in the PSR. */
    127141#define SPARC_PSR_ICC_BIT_POSITION  20   /* bits 20 - 23 */
     142/** This constant is the starting bit position of the VER in the PSR. */
    128143#define SPARC_PSR_VER_BIT_POSITION  24   /* bits 24 - 27 */
     144/** This constant is the starting bit position of the IMPL in the PSR. */
    129145#define SPARC_PSR_IMPL_BIT_POSITION 28   /* bits 28 - 31 */
    130146
    131147#ifndef ASM
    132148
    133 /*
    134  *  Standard nop
    135  */
    136 
     149/**
     150 *  This macro is a standard nop instruction.
     151 */
    137152#define nop() \
    138153  do { \
     
    140155  } while ( 0 )
    141156
    142 /*
    143  *  Get and set the PSR
    144  */
    145 
     157/**
     158 *  @brief Macro to Obtain the PSR
     159 *
     160 *  This macro returns the current contents of the PSR register in @a _psr.
     161 */
    146162#define sparc_get_psr( _psr ) \
    147163  do { \
     
    150166  } while ( 0 )
    151167
     168/**
     169 *  @brief Macro to Set the PSR
     170 *
     171 *  This macro sets the PSR register to the value in @a _psr.
     172 */
    152173#define sparc_set_psr( _psr ) \
    153174  do { \
     
    158179  } while ( 0 )
    159180
    160 /*
    161  *  Get and set the TBR
    162  */
    163 
     181/**
     182 *  @brief Macro to Obtain the TBR
     183 *
     184 *  This macro returns the current contents of the TBR register in @a _tbr.
     185 */
    164186#define sparc_get_tbr( _tbr ) \
    165187  do { \
     
    168190  } while ( 0 )
    169191
     192/**
     193 *  @brief Macro to Set the TBR
     194 *
     195 *  This macro sets the TBR register to the value in @a _tbr.
     196 */
    170197#define sparc_set_tbr( _tbr ) \
    171198  do { \
     
    173200  } while ( 0 )
    174201
    175 /*
    176  *  Get and set the WIM
    177  */
    178 
     202/**
     203 *  @brief Macro to Obtain the WIM
     204 *
     205 *  This macro returns the current contents of the WIM field in @a _wim.
     206 */
    179207#define sparc_get_wim( _wim ) \
    180208  do { \
     
    182210  } while ( 0 )
    183211
     212/**
     213 *  @brief Macro to Set the WIM
     214 *
     215 *  This macro sets the WIM field to the value in @a _wim.
     216 */
    184217#define sparc_set_wim( _wim ) \
    185218  do { \
     
    190223  } while ( 0 )
    191224
    192 /*
    193  *  Get and set the Y
    194  */
    195 
     225/**
     226 *  @brief Macro to Obtain the Y Register
     227 *
     228 *  This macro returns the current contents of the Y register in @a _y.
     229 */
    196230#define sparc_get_y( _y ) \
    197231  do { \
     
    199233  } while ( 0 )
    200234
     235/**
     236 *  @brief Macro to Set the Y Register
     237 *
     238 *  This macro sets the Y register to the value in @a _y.
     239 */
    201240#define sparc_set_y( _y ) \
    202241  do { \
     
    204243  } while ( 0 )
    205244
    206 /*
    207  *  Manipulate the interrupt level in the psr
    208  */
    209 
     245/**
     246 *  @brief SPARC Disable Processor Interrupts
     247 *
     248 *  This method is invoked to disable all maskable interrupts.
     249 *
     250 *  @return This method returns the entire PSR contents.
     251 */
    210252uint32_t sparc_disable_interrupts(void);
    211 void sparc_enable_interrupts(uint32_t);
    212 
    213 #define sparc_flash_interrupts( _level ) \
    214   do { \
    215     sparc_enable_interrupts( (_level) ); \
    216     _level = sparc_disable_interrupts(); \
    217   } while ( 0 )
    218 
     253
     254/**
     255 *  @brief SPARC Enable Processor Interrupts
     256 *
     257 *  This method is invoked to enable all maskable interrupts.
     258 *
     259 *  @param[in] psr is the PSR returned by @ref sparc_disable_interrupts.
     260 */
     261void sparc_enable_interrupts(uint32_t psr);
     262
     263/**
     264 *  @brief SPARC Flash Processor Interrupts
     265 *
     266 *  This method is invoked to temporarily enable all maskable interrupts.
     267 *
     268 *  @param[in] _psr is the PSR returned by @ref sparc_disable_interrupts.
     269 */
     270#define sparc_flash_interrupts( _psr ) \
     271  do { \
     272    sparc_enable_interrupts( (_psr) ); \
     273    _psr = sparc_disable_interrupts(); \
     274  } while ( 0 )
     275
     276/**
     277 *  @brief SPARC Obtain Interrupt Level
     278 *
     279 *  This method is invoked to obtain the current interrupt disable level.
     280 *
     281 *  @param[in] _level is the PSR returned by @ref sparc_disable_interrupts.
     282 */
    219283#define sparc_get_interrupt_level( _level ) \
    220284  do { \
  • cpukit/score/cpu/sparc/rtems/score/types.h

    rb375f06 r4bafde5  
    11/**
    22 * @file rtems/score/types.h
     3 *
     4 * This include file contains type definitions pertaining to the
     5 * SPARC processor family.
    36 */
    47
    58/*
    6  *  This include file contains type definitions pertaining to the
    7  *  SPARC processor family.
    8  *
    9  *  COPYRIGHT (c) 1989-1999.
     9 *  COPYRIGHT (c) 1989-2011.
    1010 *  On-Line Applications Research Corporation (OAR).
    1111 *
     
    2828#endif
    2929
    30 /*
    31  *  This section defines the basic types for this processor.
     30/**
     31 * @brief Priority Bit Map Type
     32 *
     33 * On the SPARC, there is no bitscan instruction and no penalty associated
     34 * for using 16-bit variables.  With no overriding architectural factors,
     35 * just using a uint16_t.
    3236 */
     37typedef uint16_t Priority_bit_map_Control;
    3338
    34 typedef uint16_t         Priority_bit_map_Control;
     39/**
     40 *  @brief SPARC ISR Handler Return Type
     41 *
     42 *  This is the type which SPARC ISR Handlers return.
     43 */
    3544typedef void sparc_isr;
     45
     46/**
     47 *  @brief SPARC ISR Handler Prototype
     48 *
     49 *  This is the prototype for SPARC ISR Handlers.
     50 */
    3651typedef void ( *sparc_isr_entry )( void );
    3752
Note: See TracChangeset for help on using the changeset viewer.